Compiling Verilog HDL simulator
https://www.veripool.org/projects/verilator/wiki/Intro
Verilator compiles synthesizable Verilog (not test-bench code), plus
some PSL, SystemVerilog and Synthesis assertions into an optimized
model which is in turn wrapped inside a C++/SystemC module for faster
execution.
- Download package
-
Checkout Package
osc -A https://api.opensuse.org checkout hardware:FPGA/verilator && cd $_ - Create Badge
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Source Files
| Filename | Size | Changed |
|---|---|---|
| _service | 0000000554 554 Bytes | |
| _servicedata | 0000000240 240 Bytes | |
| fix-shebang.patch | 0000001976 1.93 KB | |
| verilator-4.106.1606957763.b350b6a0.tar.xz | 0001537448 1.47 MB | |
| verilator.changes | 0000002073 2.02 KB | |
| verilator.spec | 0000003168 3.09 KB |
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