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Python module for digital logic development

MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you can use Python as a hardware description and verification language. Furthermore, you can convert implementation-oriented MyHDL code to Verilog automatically, and take it to a silicon implementation from there.


Jan Decaluwe jan@jandecaluwe.com

Source Files

Filename Size Changed Actions
myhdl-0.6.tar.gz 181 KB over 9 years ago Download File
python-myhdl.spec 1.31 KB over 9 years ago Download File

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