File z10-sched-fixes3 of Package gcc43

Index: gcc/config/s390/s390.md
===================================================================
--- gcc/config/s390/s390.md.orig	2009-11-20 13:52:26.000000000 +0100
+++ gcc/config/s390/s390.md	2009-11-20 13:52:28.000000000 +0100
@@ -3375,27 +3375,28 @@
   [(set_attr "op_type" "RI")
    (set_attr "z10prop" "z10_super_E1")])
 
+; Update the left-most 32 bit of a DI.
+(define_insn "*insv_h_di_reg_extimm"
+  [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+			 (const_int 32)
+			 (const_int 0))
+	(match_operand:DI 1 "const_int_operand" "n"))]
+  "TARGET_EXTIMM"
+  "iihf\t%0,%o1"
+  [(set_attr "op_type" "RIL")
+   (set_attr "z10prop" "z10_fwd_E1")])
 
-(define_insn "*insv<mode>_reg_extimm"
+; Update the right-most 32 bit of a DI, or the whole of a SI.
+(define_insn "*insv_l<mode>_reg_extimm"
   [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
 			(const_int 32)
 			(match_operand 1 "const_int_operand" "n"))
 	(match_operand:P 2 "const_int_operand" "n"))]
   "TARGET_EXTIMM
-   && INTVAL (operands[1]) >= 0
-   && INTVAL (operands[1]) < BITS_PER_WORD
-   && INTVAL (operands[1]) % 32 == 0"
-{
-  switch (BITS_PER_WORD - INTVAL (operands[1]))
-    {
-      case 64: return "iihf\t%0,%o2"; break;
-      case 32: return "iilf\t%0,%o2"; break;
-      default: gcc_unreachable();
-    }
-}
+   && BITS_PER_WORD - INTVAL (operands[1]) == 32"
+  "iilf\t%0,%o2"
   [(set_attr "op_type" "RIL")
-   (set_attr "z10prop" "z10_fwd_E1")])
-
+   (set_attr "z10prop" "z10_fwd_A1")])
 
 ;
 ; extendsidi2 instruction pattern(s).