File riscv-support.patch of Package mozjs60

diff --git a/build/moz.configure/init.configure b/build/moz.configure/init.configure
index 83b8d70..e5f3182 100644
--- a/build/moz.configure/init.configure
+++ b/build/moz.configure/init.configure
@@ -676,6 +676,9 @@ def split_triplet(triplet, allow_unknown
     elif cpu == 'sh4':
         canonical_cpu = 'sh4'
         endianness = 'little'
+    elif cpu == 'riscv64':
+        canonical_cpu = 'riscv64'
+        endianness = 'little'
     elif allow_unknown:
         canonical_cpu = cpu
         endianness = 'unknown'
diff --git a/js/src/jit/AtomicOperations.h b/js/src/jit/AtomicOperations.h
index a8970b0..41503c8 100644
--- a/js/src/jit/AtomicOperations.h
+++ b/js/src/jit/AtomicOperations.h
@@ -393,6 +393,8 @@ inline bool AtomicOperations::isLockfree
 #include "jit/none/AtomicOperations-feeling-lucky.h"
 #elif defined(__s390__) || defined(__s390x__)
 #include "jit/none/AtomicOperations-feeling-lucky.h"
+#elif defined(__riscv)
+# include "jit/none/AtomicOperations-feeling-lucky.h"
 #else
 #error "No AtomicOperations support provided for this platform"
 #endif
diff --git a/js/src/jit/none/AtomicOperations-feeling-lucky.h b/js/src/jit/none/AtomicOperations-feeling-lucky.h
index da57228..5167e82 100644
--- a/js/src/jit/none/AtomicOperations-feeling-lucky.h
+++ b/js/src/jit/none/AtomicOperations-feeling-lucky.h
@@ -80,6 +80,14 @@
 #define GNUC_COMPATIBLE
 #endif
 
+#ifdef __riscv
+#  define GNUC_COMPATIBLE
+#  if  __riscv_xlen == 64
+#    define HAS_64BIT_ATOMICS
+#    define HAS_64BIT_LOCKFREE
+#  endif
+#endif
+
 // The default implementation tactic for gcc/clang is to use the newer
 // __atomic intrinsics added for use in C++11 <atomic>.  Where that
 // isn't available, we use GCC's older __sync functions instead.
diff --git a/mfbt/tests/TestPoisonArea.cpp b/mfbt/tests/TestPoisonArea.cpp
index 06c24ed..fba9263 100644
--- a/mfbt/tests/TestPoisonArea.cpp
+++ b/mfbt/tests/TestPoisonArea.cpp
@@ -168,6 +168,9 @@ static const ia64_instr _return_instr =
 #define RETURN_INSTR _return_instr
 #define RETURN_INSTR_TYPE ia64_instr
 
+#elif defined __riscv
+#define RETURN_INSTR 0x80828082 /* ret; ret */
+
 #else
 #error "Need return instruction for this architecture"
 #endif
diff --git a/python/mozbuild/mozbuild/configure/constants.py b/python/mozbuild/mozbuild/configure/constants.py
index 33ae5a4..b7be8ce 100644
--- a/python/mozbuild/mozbuild/configure/constants.py
+++ b/python/mozbuild/mozbuild/configure/constants.py
@@ -50,6 +50,7 @@ CPU_bitness = {
     'mips64': 64,
     'ppc': 32,
     'ppc64': 64,
+    'riscv64': 64,
     's390': 32,
     's390x': 64,
     'sh4': 32,
@@ -89,6 +90,7 @@ CPU_preprocessor_checks = OrderedDict((
     ('mips64', '__mips64'),
     ('mips32', '__mips__'),
     ('sh4', '__sh__'),
+    ('riscv64', '__riscv && __riscv_xlen == 64'),
 ))
 
 assert sorted(CPU_preprocessor_checks.keys()) == sorted(CPU.POSSIBLE_VALUES)