File 22231-x86-pv-ucode-msr-intel.patch of Package xen.import4929

# HG changeset patch
# User Keir Fraser <keir@xen.org>
# Date 1286784105 -3600
# Node ID a1405385db77c7c81aac27bd88d6c4b2d90b1389
# Parent  a33886146b45da46a5161a7ebed4d2f607642aee
x86: emulate MSR_IA32_UCODE_REV Intel access protocol

Intel requires a write of zeros (hence such writes now get silently
ignored) followed by a cpuid(1) followed by the actual read.

Includes some code redundancy elimination possible after the actual
change.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2290,6 +2290,14 @@ static int emulate_privileged_op(struct 
             if ( wrmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, eax, edx) != 0 )
                 goto fail;
             break;
+        case MSR_IA32_UCODE_REV:
+            if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
+                goto fail;
+            if ( rdmsr_safe(regs->ecx, l, h) )
+                goto fail;
+            if ( l | h )
+                goto invalid;
+            break;
         case MSR_IA32_MISC_ENABLE:
             if ( rdmsr_safe(regs->ecx, l, h) )
                 goto invalid;
@@ -2397,16 +2405,21 @@ static int emulate_privileged_op(struct 
                 regs->eax = regs->edx = 0;
                 break;
             }
-            if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) != 0 )
-                goto fail;
-            break;
+            goto rdmsr_normal;
+        case MSR_IA32_UCODE_REV:
+            BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
+            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+            {
+                if ( wrmsr_safe(MSR_IA32_UCODE_REV, 0, 0) )
+                    goto fail;
+                sync_core();
+            }
+            goto rdmsr_normal;
         case MSR_IA32_MISC_ENABLE:
             if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
                 goto fail;
             regs->eax = guest_misc_enable(regs->eax);
             break;
-        case MSR_EFER:
-        case MSR_AMD_PATCHLEVEL:
         default:
             if ( rdmsr_hypervisor_regs(regs->ecx, &val) )
             {
@@ -2422,6 +2435,8 @@ static int emulate_privileged_op(struct 
             if ( rc )
                 goto rdmsr_writeback;
 
+        case MSR_EFER:
+ rdmsr_normal:
             /* Everyone can read the MSR space. */
             /* gdprintk(XENLOG_WARNING,"Domain attempted RDMSR %p.\n",
                         _p(regs->ecx));*/