File 25735-x86-cpuid-masking-XeonE5.patch of Package xen.openSUSE_12.1_Update

# HG changeset patch
# User Matt Wilson <msw@amazon.com>
# Date 1344322193 -7200
# Node ID ca1db6da64e9a54cc6a5fc378dcdcea0a5715403
# Parent  a5f4efac996f030ba2f572b93ddbbcd1eff5ade7
Although the "Intel Virtualization Technology FlexMigration
Application Note" (http://www.intel.com/Assets/PDF/manual/323850.pdf)
does not document support for extended model 2H model DH (Intel Xeon
Processor E5 Family), empirical evidence shows that the same MSR
addresses can be used for cpuid masking as exdended model 2H model AH
(Intel Xen Processor E3-1200 Family).

Signed-off-by: Matt Wilson <msw@amazon.com>
Acked-by: Nakajima, Jun <jun.nakajima@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -107,7 +107,7 @@ static void __devinit set_cpuidmask(cons
 			return;
 		extra = "xsave ";
 		break;
-	case 0x2a:
+	case 0x2a: case 0x2d:
 		wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2,
 		      opt_cpuid_mask_ecx,
 		      opt_cpuid_mask_edx);