Overview

Request 1040204 accepted

- Update to release 20221201
* Clarified synth decoding for Intel Xeon D-1700.
* Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
instlatx64 sample.
* Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
* Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
* Added synth & uarch decoding for (10,15),(10,1) Bergamo.
* Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
* Added 0x8000001b/eax bit: IBS L3 miss filtering support.
* Added 0x8000001f/eax bits: RMPQUERY instruction support,
VMPL supervisor shadow stack support, VMGEXIT parameter support,
virtual TOM MSR support, IBS virtual support for SEV-ES guests,
SMT protection support, SVSM communication page MSR support,
VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
* Added 0x80000020/0/ecx bit: L3 range reservation support.
* Added 0x80000021/eax bits: automatic IBRS,
CPUID disable for non-privileged.
* Added 0x80000022/eax bit: AMD LBR & PMC freezing.
* Added 0x80000022/ebx field: number of LBR stack entries.
* Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
* Added 0x80000026 leaf: AMD Extended CPU Topology.
* cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
AMD LBR V2 flag, from LX*.

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Request History
Valentin Lefebvre's avatar

vlefebvre created request

- Update to release 20221201
* Clarified synth decoding for Intel Xeon D-1700.
* Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
instlatx64 sample.
* Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
* Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
* Added synth & uarch decoding for (10,15),(10,1) Bergamo.
* Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
* Added 0x8000001b/eax bit: IBS L3 miss filtering support.
* Added 0x8000001f/eax bits: RMPQUERY instruction support,
VMPL supervisor shadow stack support, VMGEXIT parameter support,
virtual TOM MSR support, IBS virtual support for SEV-ES guests,
SMT protection support, SVSM communication page MSR support,
VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
* Added 0x80000020/0/ecx bit: L3 range reservation support.
* Added 0x80000021/eax bits: automatic IBRS,
CPUID disable for non-privileged.
* Added 0x80000022/eax bit: AMD LBR & PMC freezing.
* Added 0x80000022/ebx field: number of LBR stack entries.
* Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
* Added 0x80000026 leaf: AMD Extended CPU Topology.
* cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
AMD LBR V2 flag, from LX*.


Jan Engelhardt's avatar

jengelh accepted request

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