File barcelona.patch of Package gcc41

Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c.orig
+++ gcc/config/i386/i386.c
@@ -1650,6 +1650,10 @@ override_options (void)
       {"amdfam10", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
 				         | PTA_3DNOW_A | PTA_SSE | PTA_SSE2| PTA_SSE3 | PTA_SSE4A
                                          | PTA_POPCNT | PTA_ABM},
+      {"barcelona", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
+                                       | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
+                                       | PTA_SSE2 | PTA_SSE3 | PTA_POPCNT
+                                       | PTA_ABM | PTA_SSE4A},
     };
 
   int const pta_size = ARRAY_SIZE (processor_alias_table);
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc.orig
+++ gcc/config.gcc
@@ -2396,7 +2396,7 @@ if test x$with_cpu = x ; then
       ;;
     i686-*-* | i786-*-*)
       case ${target_noncanonical} in
-        amdfam10-*)
+        amdfam10-*|barcelona-*)
           with_cpu=amdfam10
           ;;
         k8-*|opteron-*|athlon_64-*)
@@ -2436,7 +2436,7 @@ if test x$with_cpu = x ; then
       ;;
     x86_64-*-*)
       case ${target_noncanonical} in
-        amdfam10-*)
+        amdfam10-*|barcelona-*)
           with_cpu=amdfam10
           ;;
         k8-*|opteron-*|athlon_64-*)
@@ -2668,7 +2668,7 @@ case "${target}" in
 				esac
 				# OK
 				;;
-			"" | k8 | opteron | athlon64 | athlon-fx | nocona | generic | amdfam10 )
+			"" | k8 | opteron | athlon64 | athlon-fx | nocona | generic | amdfam10 | barcelona )
 				# OK
 				;;
 			*)
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi.orig
+++ gcc/doc/invoke.texi
@@ -9074,7 +9074,7 @@ instruction set support.
 @item k8, opteron, athlon64, athlon-fx
 AMD K8 core based CPUs with x86-64 instruction set support.  (This supersets
 MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
-@item amdfam10
+@item amdfam10, barcelona
 AMD Family 10 core based CPUs with x86-64 instruction set support.  (This supersets
 MMX, SSE, SSE2, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit instruction set
 extensions.)