File new_extended_kernel_struct.patch of Package mcelog
From: Andi Kleen <ak@linux.intel.com>
Subject: Update struct mce from kernel
References: bnc#569495
Patch-Mainline: yes
Commit-ID: 06bc75e3df483dcc50c604ae92262cb32cee96d2
Signed-off-by: Thomas Renninger <trenn@suse.de>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
mcelog.c | 8 ++++----
mcelog.h | 11 +++++++----
2 files changed, 11 insertions(+), 8 deletions(-)
Index: mcelog-0.7/mcelog.c
===================================================================
--- mcelog-0.7.orig/mcelog.c
+++ mcelog-0.7/mcelog.c
@@ -118,15 +118,15 @@ void dump_mce(struct mce *m)
m->tsc,
(m->mcgstatus & MCI_STATUS_UC) ?
"(upper bound, found by polled driver)" : "");
- if (m->rip)
+ if (m->ip)
Wprintf("RIP%s %02x:%Lx ",
!(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
- m->cs, m->rip);
+ m->cs, m->ip);
if (m->misc)
Wprintf("MISC %Lx ", m->misc);
if (m->addr)
Wprintf("ADDR %Lx ", m->addr);
- if (m->rip | m->misc | m->addr)
+ if (m->ip | m->misc | m->addr)
Wprintf("\n");
switch (cpu) {
case CPU_K8:
@@ -267,7 +267,7 @@ void decodefatal(FILE *inf)
n = sscanf(s, "%02x:<%016Lx> {%100s}",
&cs,
- &m.rip,
+ &m.ip,
symbol);
m.cs = cs;
if (n < 2)
Index: mcelog-0.7/mcelog.h
===================================================================
--- mcelog-0.7.orig/mcelog.h
+++ mcelog-0.7/mcelog.h
@@ -17,18 +17,21 @@ struct mce {
__u64 misc;
__u64 addr;
__u64 mcgstatus;
- __u64 rip;
+ __u64 ip;
__u64 tsc; /* cpu time stamp counter */
__u64 time; /* wall time_t when error was detected */
__u8 cpuvendor; /* cpu vendor as encoded in system.h */
__u8 pad1;
__u16 pad2;
__u32 cpuid; /* CPUID 1 EAX */
- __u8 cs; /* code segment */
+ __u8 cs; /* code segment */
__u8 bank; /* machine check bank */
- __u8 cpu; /* cpu that raised the error */
+ __u8 cpu; /* cpu number; obsolete; use extcpu now */
__u8 finished; /* entry is valid */
- __u32 extcpu; /* extended CPU number */
+ __u32 extcpu; /* linux cpu number that detected the error */
+ __u32 socketid; /* CPU socket ID */
+ __u32 apicid; /* CPU initial apic ID */
+ __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
};
#define X86_VENDOR_INTEL 0
