File qemuu-add-support-for-cpuid-MSR_IA32_SPEC_CTRL.patch of Package xen.11319
From: Wei Wang <wei.w.wang@intel.com>
Date: Tue, 7 Nov 2017 16:39:49 +0800
Subject: [PATCH] i386/kvm: MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD
CPUID(EAX=0X7,ECX=0).EDX[26]/[27] indicates the support of
MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD. Expose the CPUID
to the guest. Also add the support of transferring the MSRs during live
migration.
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
---
Index: xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/cpu.c
===================================================================
--- xen-4.4.4-testing.orig/tools/qemu-xen-dir-remote/target-i386/cpu.c
+++ xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/cpu.c
@@ -2004,10 +2004,11 @@ void cpu_x86_cpuid(CPUX86State *env, uin
case 7:
/* Structured Extended Feature Flags Enumeration Leaf */
if (count == 0) {
+ host_cpuid(index, 0, eax, ebx, ecx, edx);
*eax = 0; /* Maximum ECX value for sub-leaves */
*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
*ecx = 0; /* Reserved */
- *edx = 0; /* Reserved */
+ *edx = env->features[FEAT_7_0_EDX] | *edx;
} else {
*eax = 0;
*ebx = 0;
Index: xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/cpu.h
===================================================================
--- xen-4.4.4-testing.orig/tools/qemu-xen-dir-remote/target-i386/cpu.h
+++ xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/cpu.h
@@ -302,6 +302,7 @@
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
#define MSR_TSC_ADJUST 0x0000003b
+#define MSR_IA32_SPEC_CTRL 0x00000048
#define MSR_IA32_TSCDEADLINE 0x6e0
#define MSR_MTRRcap 0xfe
@@ -372,6 +373,8 @@ typedef enum FeatureWord {
FEAT_1_EDX, /* CPUID[1].EDX */
FEAT_1_ECX, /* CPUID[1].ECX */
FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
+ FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
+ FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
@@ -531,6 +534,8 @@ typedef uint32_t FeatureWordArray[FEATUR
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
+#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
+#define CPUID_7_0_EDX_PRED_CMD (1U << 27)
#define CPUID_VENDOR_SZ 12
@@ -882,6 +887,7 @@ typedef struct CPUX86State {
uint64_t xcr0;
+ uint64_t spec_ctrl;
TPRAccess tpr_access_type;
} CPUX86State;
Index: xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/kvm.c
===================================================================
--- xen-4.4.4-testing.orig/tools/qemu-xen-dir-remote/target-i386/kvm.c
+++ xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/kvm.c
@@ -64,6 +64,7 @@ const KVMCapabilityInfo kvm_arch_require
static bool has_msr_star;
static bool has_msr_hsave_pa;
static bool has_msr_tsc_adjust;
+static bool has_msr_spec_ctrl;
static bool has_msr_tsc_deadline;
static bool has_msr_async_pf_en;
static bool has_msr_pv_eoi_en;
@@ -724,6 +725,9 @@ static int kvm_get_supported_msrs(KVMSta
has_msr_tsc_adjust = true;
continue;
}
+ if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) {
+ has_msr_spec_ctrl = true;
+ break;
if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
has_msr_tsc_deadline = true;
continue;
@@ -1074,6 +1078,9 @@ static int kvm_put_msrs(X86CPU *cpu, int
kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
env->msr_ia32_misc_enable);
}
+ if (has_msr_spec_ctrl) {
+ kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
+ }
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1384,6 +1391,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (ret < 0) {
return ret;
}
+ if (has_msr_spec_ctrl) {
+ kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
+ }
for (i = 0; i < ret; i++) {
switch (msrs[i].index) {
@@ -1443,6 +1453,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_MISC_ENABLE:
env->msr_ia32_misc_enable = msrs[i].data;
break;
+ case MSR_IA32_SPEC_CTRL:
+ env->spec_ctrl = msrs[i].data;
+ break;
default:
if (msrs[i].index >= MSR_MC0_CTL &&
msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
Index: xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/machine.c
===================================================================
--- xen-4.4.4-testing.orig/tools/qemu-xen-dir-remote/target-i386/machine.c
+++ xen-4.4.4-testing/tools/qemu-xen-dir-remote/target-i386/machine.c
@@ -446,6 +446,24 @@ static const VMStateDescription vmstate_
}
};
+static bool spec_ctrl_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return env->spec_ctrl != 0;
+}
+
+static const VMStateDescription vmstate_spec_ctrl = {
+ .name = "cpu/spec_ctrl",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.spec_ctrl, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -571,6 +589,9 @@ const VMStateDescription vmstate_x86_cpu
}, {
.vmsd = &vmstate_msr_ia32_misc_enable,
.needed = misc_enable_needed,
+ }, {
+ .vmsd = &vmstate_spec_ctrl,
+ .needed = spec_ctrl_needed,
} , {
/* empty */
}
