File backport-llvm-r212612 of Package llvm

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r212612 | chandlerc | 2014-07-09 13:13:16 +0200 (Wed, 09 Jul 2014) | 2 lines

Sink two variables only used in an assert into the assert itself. Should
fix the release builds with Werror.
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Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp.orig
+++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -2356,7 +2356,6 @@ bool DAGTypeLegalizer::WidenVectorOperan
 SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
   SDLoc DL(N);
   EVT VT = N->getValueType(0);
-  unsigned NumElts = VT.getVectorNumElements();
 
   SDValue InOp = N->getOperand(0);
   // If some legalization strategy other than widening is used on the operand,
@@ -2365,8 +2364,9 @@ SDValue DAGTypeLegalizer::WidenVecOp_ZER
   if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
     return WidenVecOp_Convert(N);
   InOp = GetWidenedVector(InOp);
-  EVT InVT = InOp.getValueType();
-  assert(NumElts < InVT.getVectorNumElements() && "Input wasn't widened!");
+  assert(VT.getVectorNumElements() <
+             InOp.getValueType().getVectorNumElements() &&
+         "Input wasn't widened!");
 
   // Use a special DAG node to represent the operation of zero extending the
   // low lanes.