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SUSE:SLE-12-SP1:Update
qemu.11146
0287-i386-Add-support-for-SPEC_CTRL-MSR.patch
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File 0287-i386-Add-support-for-SPEC_CTRL-MSR.patch of Package qemu.11146
From fb92c2c1c28cdf797c7952f95677c757c9ddf520 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini <pbonzini@redhat.com> Date: Tue, 9 Jan 2018 13:45:14 -0200 Subject: [PATCH] i386: Add support for SPEC_CTRL MSR Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20180109154519.25634-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> (cherry picked from commit a33a2cfe2f771b360b3422f6cdf566a560860bfc) [BR: BSC#1068032 CVE-2017-5715] Signed-off-by: Bruce Rogers <brogers@suse.com> --- target-i386/cpu.h | 3 +++ target-i386/kvm.c | 15 +++++++++++++++ target-i386/machine.c | 21 +++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4ee12ca2e9..9e66db1474 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -308,6 +308,7 @@ #define MSR_IA32_APICBASE_BASE (0xfffff<<12) #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_TSC_ADJUST 0x0000003b +#define MSR_IA32_SPEC_CTRL 0x48 #define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_P6_PERFCTR0 0xc1 @@ -889,6 +890,8 @@ typedef struct CPUX86State { uint64_t pat; uint32_t smbase; + uint64_t spec_ctrl; + /* End of state preserved by INIT (dummy marker). */ struct {} end_init_save; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 41d09e52de..f7673fc378 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -81,6 +81,7 @@ static bool has_msr_hv_vapic; static bool has_msr_hv_tsc; static bool has_msr_mtrr; static bool has_msr_xss; +static bool has_msr_spec_ctrl; static bool has_msr_architectural_pmu; static uint32_t num_architectural_pmu_counters; @@ -831,6 +832,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_xss = true; continue; } + if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) { + has_msr_spec_ctrl = true; + continue; + } } } @@ -1251,6 +1256,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_xss) { kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_set(&msrs[n++], MSR_IA32_SPEC_CTRL, env->spec_ctrl); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); @@ -1259,6 +1267,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); } #endif + /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. Limit them to reset or full state updates. @@ -1615,6 +1624,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_xss) { msrs[n++].index = MSR_IA32_XSS; } + if (has_msr_spec_ctrl) { + msrs[n++].index = MSR_IA32_SPEC_CTRL; + } if (!env->tsc_valid) { @@ -1860,6 +1872,9 @@ static int kvm_get_msrs(X86CPU *cpu) env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; } break; + case MSR_IA32_SPEC_CTRL: + env->spec_ctrl = msrs[i].data; + break; } } diff --git a/target-i386/machine.c b/target-i386/machine.c index cd1ddd29e9..d78c41f8fa 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -708,6 +708,24 @@ static const VMStateDescription vmstate_xss = { } }; +static bool spec_ctrl_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->spec_ctrl != 0; +} + +static const VMStateDescription vmstate_spec_ctrl = { + .name = "cpu/spec_ctrl", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]){ + VMSTATE_UINT64(env.spec_ctrl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -856,6 +874,9 @@ VMStateDescription vmstate_x86_cpu = { }, { .vmsd = &vmstate_xss, .needed = xss_needed, + }, { + .vmsd = &vmstate_spec_ctrl, + .needed = spec_ctrl_needed, } , { /* empty */ }
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