File 0079-spapr-Limit-threads-per-core-accord.patch of Package qemu.6354

From 83a4c5ad4326c46f1b3c84f290929d03a48b9068 Mon Sep 17 00:00:00 2001
From: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: Fri, 23 May 2014 12:26:56 +1000
Subject: [PATCH] spapr: Limit threads per core according to current
 compatibility mode

This puts a limit to the number of threads per core based on the current
compatibility mode. Although PowerISA specs do not specify the maximum
threads per core number, the linux guest still expects that
PowerISA2.05-compatible CPU supports only 2 threads per core as this
is what POWER6 (2.05 compliant CPU) implements, the same is for
POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads).

This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of
threads which affects ibm,ppc-interrupt-server#s and
ibm,ppc-interrupt-gserver#s properties.

The number of CPU nodesremains unchanged.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/spapr.c              |  2 +-
 target-ppc/cpu.h            |  1 +
 target-ppc/translate_init.c | 27 +++++++++++++++++++++++++++
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 14cbef5fee..eddf4802fd 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -293,7 +293,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr)
         }
 
         ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
-                                     smp_threads);
+                                     ppc_get_compat_smt_threads(cpu));
         if (ret < 0) {
             return ret;
         }
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 6484289197..91214abff4 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1122,6 +1122,7 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
 void ppc_store_msr (CPUPPCState *env, target_ulong value);
 
 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
+int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
 
 /* Time-base and decrementer management */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 9c1a34a1ce..2c33881e54 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8185,6 +8185,33 @@ static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
     }
 }
 
+int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
+{
+    int ret = smp_threads;
+    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+    switch (cpu->cpu_version) {
+    case CPU_POWERPC_LOGICAL_2_05:
+        ret = 2;
+        break;
+    case CPU_POWERPC_LOGICAL_2_06:
+        ret = 4;
+        break;
+    case CPU_POWERPC_LOGICAL_2_07:
+        ret = 8;
+        break;
+    default:
+        if (pcc->pcr_mask & PCR_COMPAT_2_06) {
+            ret = 4;
+        } else if (pcc->pcr_mask & PCR_COMPAT_2_05) {
+            ret = 2;
+        }
+        break;
+    }
+
+    return MIN(ret, smp_threads);
+}
+
 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
 {
     int ret = 0;