File xsa297-1.patch of Package xen.11298
x86/spec-ctrl: CPUID/MSR definitions for Microarchitectural Data Sampling
The MD_CLEAR feature can be automatically offered to guests. No
infrastructure is needed in Xen to support the guest making use of it.
This is part of XSA-297, CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
--- a/docs/misc/xen-command-line.markdown
+++ b/docs/misc/xen-command-line.markdown
@@ -425,7 +425,7 @@ accounting for hardware capabilities as
Currently accepted:
-The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`,
+The Speculation Control hardware features `md-clear`, `ibrsb`, `stibp`, `ibpb`,
`l1d-flush` and `ssbd` are used by default if available and applicable. They can
be ignored, e.g. `no-ibrsb`, at which point Xen won't use them itself, and
won't offer them to guests.
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -158,6 +158,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1},
{"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
{"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
+ {"md-clear", 0x00000007, 0, CPUID_REG_EDX, 10, 1},
{"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1},
{"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1},
{"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1},
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -122,7 +122,12 @@ static int __init parse_xen_cpuid(const
if ( !ss )
ss = strchr(s, '\0');
- if ( (val = parse_boolean("ibpb", s, ss)) >= 0 )
+ if ( (val = parse_boolean("md-clear", s, ss)) >= 0 )
+ {
+ if ( !val )
+ setup_clear_cpu_cap(X86_FEATURE_MD_CLEAR);
+ }
+ else if ( (val = parse_boolean("ibpb", s, ss)) >= 0 )
{
if ( !val )
setup_clear_cpu_cap(X86_FEATURE_IBPB);
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -263,11 +263,12 @@ static void __init print_details(enum in
printk("Speculative mitigation facilities:\n");
/* Hardware features which pertain to speculative mitigations. */
- printk(" Hardware features:%s%s%s%s%s\n",
+ printk(" Hardware features:%s%s%s%s%s%s\n",
(_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "",
+ (_7d0 & cpufeat_mask(X86_FEATURE_MD_CLEAR)) ? " MD_CLEAR" : "",
(e8b & cpufeat_mask(X86_FEATURE_IBPB)) ? " IBPB" : "");
/* Compiled-in support which pertains to BTI mitigations. */
@@ -299,19 +300,21 @@ static void __init print_details(enum in
* Alternatives blocks for protecting against and/or virtualising
* mitigation support for guests.
*/
- printk(" Support for VMs: PV:%s%s%s%s, HVM:%s%s%s%s\n",
+ printk(" Support for VMs: PV:%s%s%s%s%s, HVM:%s%s%s%s%s\n",
(boot_cpu_has(X86_FEATURE_SC_MSR_PV) ||
boot_cpu_has(X86_FEATURE_SC_RSB_PV) ||
opt_eager_fpu) ? "" : " None",
boot_cpu_has(X86_FEATURE_SC_MSR_PV) ? " MSR_SPEC_CTRL" : "",
boot_cpu_has(X86_FEATURE_SC_RSB_PV) ? " RSB" : "",
opt_eager_fpu ? " EAGER_FPU" : "",
+ boot_cpu_has(X86_FEATURE_MD_CLEAR) ? " MD_CLEAR" : "",
(boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ||
boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ||
opt_eager_fpu) ? "" : " None",
boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_SPEC_CTRL" : "",
boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ? " RSB" : "",
- opt_eager_fpu ? " EAGER_FPU" : "");
+ opt_eager_fpu ? " EAGER_FPU" : "",
+ boot_cpu_has(X86_FEATURE_MD_CLEAR) ? " MD_CLEAR" : "");
printk(" PV L1TF shadowing: Dom0 %s, DomU %s\n",
opt_pv_l1tf & OPT_PV_L1TF_DOM0 ? "enabled" : "disabled",
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -170,6 +170,7 @@
#define X86_FEATURE_IBPB (8*32+12) /* IBPB support only (no IBRS, used by AMD) */
/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
+#define X86_FEATURE_MD_CLEAR (9*32+10) /* VERW clears microarchitectural buffers */
#define X86_FEATURE_TSX_FORCE_ABORT (9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */
#define X86_FEATURE_IBRSB (9*32+26) /* IBRS and IBPB support (used by Intel) */
#define X86_FEATURE_STIBP (9*32+27) /* STIBP */
