File 5aec7393-2-x86-xpti-write-cr3.patch of Package xen.7652

From cda05dcae6732fc9c5b782a97a09b5a0f0dd4b81 Mon Sep 17 00:00:00 2001
From: Juergen Gross <jgross@suse.com>
Date: Thu, 26 Apr 2018 13:33:11 +0200
Subject: [PATCH] xen/x86: add a function for modifying cr3

Instead of having multiple places with more or less identical asm
statements just have one function doing a write to cr3.

As this function should be named write_cr3() rename the current
write_cr3() function to switch_cr3().

Suggested-by: Andrew Copper <andrew.cooper3@citrix.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- sle12sp2.orig/xen/arch/x86/flushtlb.c	2018-05-23 11:45:26.000000000 +0200
+++ sle12sp2/xen/arch/x86/flushtlb.c	2018-05-23 11:45:31.000000000 +0200
@@ -73,7 +73,7 @@ static void post_flush(u32 t)
     this_cpu(tlbflush_time) = t;
 }
 
-void write_cr3(unsigned long cr3)
+void switch_cr3(unsigned long cr3)
 {
     unsigned long flags, cr4;
     u32 t;
@@ -85,7 +85,7 @@ void write_cr3(unsigned long cr3)
     cr4 = read_cr4();
 
     write_cr4(cr4 & ~X86_CR4_PGE);
-    asm volatile ( "mov %0, %%cr3" : : "r" (cr3) : "memory" );
+    write_cr3(cr3);
     write_cr4(cr4);
 
     post_flush(t);
--- sle12sp2.orig/xen/arch/x86/mm.c	2018-05-23 11:45:26.000000000 +0200
+++ sle12sp2/xen/arch/x86/mm.c	2018-05-23 11:45:31.000000000 +0200
@@ -500,7 +500,7 @@ void make_cr3(struct vcpu *v, unsigned l
 void write_ptbase(struct vcpu *v)
 {
     get_cpu_info()->root_pgt_changed = 1;
-    write_cr3(v->arch.cr3);
+    switch_cr3(v->arch.cr3);
 }
 
 /*
--- sle12sp2.orig/xen/arch/x86/x86_64/traps.c	2018-05-23 11:45:26.000000000 +0200
+++ sle12sp2/xen/arch/x86/x86_64/traps.c	2018-05-23 11:45:31.000000000 +0200
@@ -287,7 +287,7 @@ void toggle_guest_pt(struct vcpu *v)
     get_cpu_info()->root_pgt_changed = 1;
 
     /* Don't flush user global mappings from the TLB. Don't tick TLB clock. */
-    asm volatile ( "mov %0, %%cr3" : : "r" (v->arch.cr3) : "memory" );
+    write_cr3(v->arch.cr3);
 
     if ( !(v->arch.flags & TF_kernel_mode) )
         return;
--- sle12sp2.orig/xen/common/efi/runtime.c	2017-03-08 00:27:12.000000000 +0100
+++ sle12sp2/xen/common/efi/runtime.c	2018-05-23 11:45:31.000000000 +0200
@@ -106,7 +106,7 @@ struct efi_rs_state efi_rs_enter(void)
         asm volatile ( "lgdt %0" : : "m" (gdt_desc) );
     }
 
-    write_cr3(virt_to_maddr(efi_l4_pgtable));
+    switch_cr3(virt_to_maddr(efi_l4_pgtable));
 
     return state;
 }
@@ -115,7 +115,7 @@ void efi_rs_leave(struct efi_rs_state *s
 {
     if ( !state->cr3 )
         return;
-    write_cr3(state->cr3);
+    switch_cr3(state->cr3);
     if ( is_pv_vcpu(current) && !is_idle_vcpu(current) )
     {
         struct desc_ptr gdt_desc = {
--- sle12sp2.orig/xen/include/asm-x86/flushtlb.h	2018-05-23 11:45:26.000000000 +0200
+++ sle12sp2/xen/include/asm-x86/flushtlb.h	2018-05-23 11:45:31.000000000 +0200
@@ -84,7 +84,7 @@ static inline unsigned long read_cr3(voi
 }
 
 /* Write pagetable base and implicitly tick the tlbflush clock. */
-void write_cr3(unsigned long cr3);
+void switch_cr3(unsigned long cr3);
 
 /* flush_* flag fields: */
  /*
--- sle12sp2.orig/xen/include/asm-x86/processor.h	2018-04-18 14:40:31.000000000 +0200
+++ sle12sp2/xen/include/asm-x86/processor.h	2018-05-23 11:45:31.000000000 +0200
@@ -334,6 +334,11 @@ static inline unsigned long read_cr2(voi
     return cr2;
 }
 
+static inline void write_cr3(unsigned long val)
+{
+    asm volatile ( "mov %0, %%cr3" : : "r" (val) : "memory" );
+}
+
 static inline unsigned long read_cr4(void)
 {
     return get_cpu_info()->cr4;