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SUSE:SLE-12-SP3:Update
xen
5c87e6d1-x86-TSX-controls-for-RTM-force-abort-m...
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File 5c87e6d1-x86-TSX-controls-for-RTM-force-abort-mode.patch of Package xen
# Commit 6be613f29b4205349275d24367bd4c82fb2960dd # Date 2019-03-12 17:05:21 +0000 # Author Andrew Cooper <andrew.cooper3@citrix.com> # Committer Andrew Cooper <andrew.cooper3@citrix.com> x86/tsx: Implement controls for RTM force-abort mode The CPUID bit and MSR are deliberately not exposed to guests, because they won't exist on newer processors. As vPMU isn't security supported, the misbehaviour of PCR3 isn't expected to impact production deployments. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/docs/misc/xen-command-line.markdown +++ b/docs/misc/xen-command-line.markdown @@ -1892,7 +1892,7 @@ Use Virtual Processor ID support if avai flushes on VM entry and exit, increasing performance. ### vpmu -> `= ( <boolean> | { bts | ipc | arch [, ...] } )` +> `= ( <boolean> | { bts | ipc | arch | rtm-abort=<bool> [, ...] } )` > Default: `off` @@ -1918,6 +1918,21 @@ in the Pre-Defined Architectural Perform and IA-32 Architectures Software Developer's Manual, Volume 3B, System Programming Guide, Part 2. +vpmu=rtm-abort controls a trade-off between working Restricted Transactional +Memory, and working performance counters. + +All processors released to date (Q1 2019) supporting Transactional Memory +Extensions suffer an erratum which has been addressed in microcode. + +Processors based on the Skylake microarchitecture with up-to-date +microcode internally use performance counter 3 to work around the erratum. +A consequence is that the counter gets reprogrammed whenever an `XBEGIN` +instruction is executed. + +An alternative mode exists where PCR3 behaves as before, at the cost of +`XBEGIN` unconditionally aborting. Enabling `rtm-abort` mode will +activate this alternative mode. + If a boolean is not used, combinations of flags are allowed, comma separated. For example, vpmu=arch,bts. --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -157,7 +157,11 @@ static const char *str_7d0[32] = [ 2] = "avx512_4vnniw", [ 3] = "avx512_4fmaps", - [4 ... 25] = "REZ", + [4 ... 11] = "REZ", + + [12] = "REZ", [13] = "tsx-force-abort", + + [14 ... 25] = "REZ", [26] = "ibrsb", [27] = "stibp", [28] = "l1d_flush", [29] = "arch_caps", --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -356,6 +356,9 @@ static void Intel_errata_workarounds(str if (c->x86 == 6 && cpu_has_clflush && (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) __set_bit(X86_FEATURE_CLFLUSH_MONITOR, c->x86_capability); + + if (cpu_has_tsx_force_abort && opt_rtm_abort) + wrmsrl(MSR_TSX_FORCE_ABORT, TSX_FORCE_ABORT_RTM); } --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -53,6 +53,7 @@ CHECK_pmu_params; static unsigned int __read_mostly opt_vpmu_enabled; unsigned int __read_mostly vpmu_mode = XENPMU_MODE_OFF; unsigned int __read_mostly vpmu_features = 0; +bool __read_mostly opt_rtm_abort; static void parse_vpmu_params(char *s); custom_param("vpmu", parse_vpmu_params); @@ -63,6 +64,8 @@ static DEFINE_PER_CPU(struct vcpu *, las static int parse_vpmu_param(char *s, unsigned int len) { + int val; + if ( !*s || !len ) return 0; if ( !strncmp(s, "bts", len) ) @@ -71,6 +74,8 @@ static int parse_vpmu_param(char *s, uns vpmu_features |= XENPMU_FEATURE_IPC_ONLY; else if ( !strncmp(s, "arch", len) ) vpmu_features |= XENPMU_FEATURE_ARCH_ONLY; + else if ( (val = parse_boolean("rtm-abort", s, s + len)) >= 0 ) + opt_rtm_abort = val; else return 1; return 0; @@ -97,6 +102,10 @@ static void __init parse_vpmu_params(cha break; p = sep + 1; } + + if ( !vpmu_features ) /* rtm-abort doesn't imply vpmu=1 */ + return; + /* fall through */ case 1: /* Default VPMU mode */ --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3416,6 +3416,8 @@ int hvm_msr_read_intercept(unsigned int case MSR_PRED_CMD: case MSR_FLUSH_CMD: /* Write-only */ + case MSR_TSX_FORCE_ABORT: + /* Not offered to guests. */ goto gp_fault; case MSR_SPEC_CTRL: @@ -3638,6 +3640,8 @@ int hvm_msr_write_intercept(unsigned int case MSR_ARCH_CAPABILITIES: /* Read-only */ + case MSR_TSX_FORCE_ABORT: + /* Not offered to guests. */ goto gp_fault; case MSR_AMD64_NB_CFG: --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2640,6 +2640,8 @@ static int priv_op_read_msr(unsigned int case MSR_PRED_CMD: case MSR_FLUSH_CMD: /* Write-only */ + case MSR_TSX_FORCE_ABORT: + /* Not offered to guests. */ break; case MSR_SPEC_CTRL: @@ -2861,6 +2863,8 @@ static int priv_op_write_msr(unsigned in case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: /* The MSR is read-only. */ + case MSR_TSX_FORCE_ABORT: + /* Not offered to guests. */ break; case MSR_SPEC_CTRL: --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -100,6 +100,9 @@ /* CPUID level 0x80000007.edx */ #define cpu_has_itsc boot_cpu_has(X86_FEATURE_ITSC) +/* CPUID level 0x00000007:0.edx */ +#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) + /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -53,6 +53,9 @@ #define MSR_FLUSH_CMD 0x0000010b #define FLUSH_CMD_L1D (_AC(1, ULL) << 0) +#define MSR_TSX_FORCE_ABORT 0x0000010f +#define TSX_FORCE_ABORT_RTM (_AC(1, ULL) << 0) + /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_A_PERFCTR0 0x000004c1 --- a/xen/include/asm-x86/vpmu.h +++ b/xen/include/asm-x86/vpmu.h @@ -125,6 +125,7 @@ static inline int vpmu_do_rdmsr(unsigned extern unsigned int vpmu_mode; extern unsigned int vpmu_features; +extern bool opt_rtm_abort; /* Context switch */ static inline void vpmu_switch_from(struct vcpu *prev) --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -241,6 +241,7 @@ XEN_CPUFEATURE(IBPB, 8*32+12) / /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ +XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */
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