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SUSE:SLE-12-SP3:Update
xen
xsa435-0-15.patch
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File xsa435-0-15.patch of Package xen
From b4a23bf6293aadecfd03bf9e83974443e2eac9cb Mon Sep 17 00:00:00 2001 From: Andrew Cooper <andrew.cooper3@citrix.com> Date: Fri, 28 Oct 2022 11:40:00 +0100 Subject: x86/cpuid: Infrastructure for leaves 7:1{ecx,edx} We don't actually need ecx yet, but adding it in now will reduce the amount to which leaf 7 is out of order in a featureset. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -165,6 +165,10 @@ int libxl_cpuid_parse_config(libxl_cpuid {"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1}, {"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1}, {"ssbd", 0x00000007, 0, CPUID_REG_EDX, 31, 1}, + + {"intel-psfd", 0x00000007, 2, CPUID_REG_EDX, 0, 1}, + {"mcdt-no", 0x00000007, 2, CPUID_REG_EDX, 5, 1}, + {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1}, {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1}, {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1}, --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -192,6 +192,30 @@ static const char *str_e21a[32] = [4 ... 31] = "REZ", }; +static const char *str_7b1[32] = +{ + [0 ... 31] = "REZ", +}; + +static const char *str_7c1[32] = +{ + [0 ... 31] = "REZ", +}; + +static const char *str_7d1[32] = +{ + [0 ... 31] = "REZ", +}; + +static const char *str_7d2[32] = +{ + [ 0] = "intel-psfd", [ 1] = "REZ", + [ 2] = "REZ", [ 3] = "REZ", + [ 4] = "REZ", [ 5] = "mcdt-no", + + [6 ... 31] = "REZ", +}; + static struct { const char *name; const char *abbr; @@ -210,6 +234,10 @@ static struct { { "0x00000007:0.edx", "7d0", str_7d0 }, { "0x00000007:1.eax", "7a1", str_7a1 }, { "0x80000021.eax", "e21a", str_e21a }, + { "0x00000007:1.ebx", "7b1", str_7b1 }, + { "0x00000007:2.edx", "7d2", str_7d2 }, + { "0x00000007:1.ecx", "7c1", str_7c1 }, + { "0x00000007:1.edx", "7d1", str_7d1 }, }; #define COL_ALIGN "18" --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -346,11 +346,22 @@ static void generic_identify(struct cpui = cpuid_eax(0x80000021); /* Intel-defined flags: level 0x00000007 */ - if ( c->cpuid_level >= 0x00000007 ) - cpuid_count(0x00000007, 0, &tmp, + if (c->cpuid_level >= 7) { + cpuid_count(7, 0, &eax, &c->x86_capability[cpufeat_word(X86_FEATURE_FSGSBASE)], &c->x86_capability[cpufeat_word(X86_FEATURE_PKU)], &c->x86_capability[cpufeat_word(X86_FEATURE_AVX512_4VNNIW)]); + if (eax > 0) + cpuid_count(7, 1, + &c->x86_capability[FEATURESET_7a1], + &c->x86_capability[FEATURESET_7b1], + &c->x86_capability[FEATURESET_7c1], + &c->x86_capability[FEATURESET_7d1]); + if (eax >= 2) + cpuid_count(7, 2, + &tmp, &tmp, &tmp, + &c->x86_capability[FEATURESET_7d2]); + } } /* --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -623,6 +623,7 @@ void __init init_guest_cpuid(void) uint64_t msr_spec_ctrl_valid_bits(const struct cpuid_policy *cp) { bool ssbd = cp->feat.ssbd || cp->extd.amd_ssbd; + bool psfd = cp->feat.intel_psfd || cp->extd.psfd; /* * Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored) @@ -630,6 +631,7 @@ uint64_t msr_spec_ctrl_valid_bits(const */ return (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | (ssbd ? SPEC_CTRL_SSBD : 0) | + (psfd ? SPEC_CTRL_PSFD : 0) | 0); } --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -444,11 +444,13 @@ custom_param("pv-l1tf", parse_pv_l1tf); static void __init print_details(enum ind_thunk thunk, uint64_t caps) { - unsigned int _7d0 = 0, e8b = 0, tmp; + unsigned int _7d0 = 0, _7d2 = 0, e8b = 0, max = 0, tmp; /* Collect diagnostics about available mitigations. */ if ( boot_cpu_data.cpuid_level >= 7 ) - cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0); + cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0); + if ( max >= 2 ) + cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2); if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 ) cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp); @@ -488,6 +490,7 @@ static void __init print_details(enum in (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "", (e8b & cpufeat_mask(X86_FEATURE_AMD_SSBD)) || (_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "", + (_7d2 & cpufeat_mask(X86_FEATURE_INTEL_PSFD)) || (e8b & cpufeat_mask(X86_FEATURE_PSFD)) ? " PSFD" : "", (_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "", (_7d0 & cpufeat_mask(X86_FEATURE_MD_CLEAR)) ? " MD_CLEAR" : "", --- a/xen/include/asm-x86/cpuid.h +++ b/xen/include/asm-x86/cpuid.h @@ -16,6 +16,10 @@ #define FEATURESET_7d0 9 /* 0x00000007:0.edx */ #define FEATURESET_7a1 10 /* 0x00000007:1.eax */ #define FEATURESET_e21a 11 /* 0x80000021.eax */ +#define FEATURESET_7b1 12 /* 0x00000007:1.ebx */ +#define FEATURESET_7d2 13 /* 0x00000007:2.edx */ +#define FEATURESET_7c1 14 /* 0x00000007:1.ecx */ +#define FEATURESET_7d1 15 /* 0x00000007:1.edx */ #ifndef __ASSEMBLY__ #include <xen/types.h> @@ -63,8 +67,8 @@ extern struct cpuidmasks cpuidmask_defau DECLARE_PER_CPU(bool, cpuid_faulting_enabled); #define CPUID_GUEST_NR_BASIC (0xdu + 1) -#define CPUID_GUEST_NR_FEAT (0u + 1) #define CPUID_GUEST_NR_CACHE (5u + 1) +#define CPUID_GUEST_NR_FEAT (2u + 1) #define CPUID_GUEST_NR_XSTATE (62u + 1) #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) #define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1) @@ -143,6 +147,31 @@ struct cpuid_policy uint32_t _7d0; struct { DECL_BITFIELD(7d0); }; }; + + /* Subleaf 1. */ + union { + uint32_t _7a1; + struct { DECL_BITFIELD(7a1); }; + }; + union { + uint32_t _7b1; + struct { DECL_BITFIELD(7b1); }; + }; + union { + uint32_t _7c1; + struct { DECL_BITFIELD(7c1); }; + }; + union { + uint32_t _7d1; + struct { DECL_BITFIELD(7d1); }; + }; + + /* Subleaf 2. */ + uint32_t /* a */:32, /* b */:32, /* c */:32; + union { + uint32_t _7d2; + struct { DECL_BITFIELD(7d2); }; + }; }; } feat; @@ -270,6 +299,10 @@ static inline void cpuid_policy_to_featu fs[FEATURESET_7d0] = p->feat._7d0; fs[FEATURESET_7a1] = p->feat._7a1; fs[FEATURESET_e21a] = p->extd.e21a; + fs[FEATURESET_7b1] = p->feat._7b1; + fs[FEATURESET_7d2] = p->feat._7d2; + fs[FEATURESET_7c1] = p->feat._7c1; + fs[FEATURESET_7d1] = p->feat._7d1; } /* Fill in a CPUID policy from a featureset bitmap. */ @@ -288,6 +321,10 @@ static inline void cpuid_featureset_to_p p->feat._7d0 = fs[FEATURESET_7d0]; p->feat._7a1 = fs[FEATURESET_7a1]; p->extd.e21a = fs[FEATURESET_e21a]; + p->feat._7b1 = fs[FEATURESET_7b1]; + p->feat._7d2 = fs[FEATURESET_7d2]; + p->feat._7c1 = fs[FEATURESET_7c1]; + p->feat._7d1 = fs[FEATURESET_7d1]; } extern struct cpuid_policy raw_policy, host_policy, pv_max_policy, --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -267,6 +267,16 @@ XEN_CPUFEATURE(SSBD, 9*32+31) / /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ +/* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */ + +/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */ +XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */ +XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */ + +/* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */ + +/* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */ + #endif /* XEN_CPUFEATURE */ /* Clean up from a default include. Close the enum (for C). */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -260,7 +260,7 @@ def crunch_numbers(state): # not IBRSB, and we pass this MSR directly to guests. Treating them # as dependent features simplifies Xen's logic, and prevents the guest # from seeing implausible configurations. - IBRSB: [STIBP, SSBD], + IBRSB: [STIBP, SSBD, INTEL_PSFD], } deep_features = tuple(sorted(deps.keys()))
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