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File oprofile-add-support-for-intel-goldmont-plus-geminilake.patch of Package oprofile
From: Michael Petlan <mpetlan@redhat.com> Date: Mon, 15 Jan 2018 14:23:47 +0100 Subject: oprofile: Add support for Intel Goldmont Plus (Geminilake) Git-repo: git://git.code.sf.net/p/oprofile/oprofile Git-commit: 26715cad45225fa4fccdc48dd1814d6e64de33dd References: FATE#324985 [suse; adjust for context events/Makefile.am: no 0c142c3a libop/op_cpu_type.[ch]: no 9751bb834, 966ef44b8 or 8b82ba96b] Adds support for Intel Goldmont Plus microarchitecture to oprofile. Only core events are supported. For more docs, please refer to the Intel 64 and IA-32 Architecture Software Developer's Manual, volume 3b, chapter 19. This patch has been tested on a corresponding machine. Signed-off-by: Tony Jones <tonyj@suse.de> --- events/Makefile.am | 1 + events/i386/goldmontplus/events | 38 ++++++++ events/i386/goldmontplus/unit_masks | 173 ++++++++++++++++++++++++++++++++++++ libop/op_cpu_type.c | 1 + libop/op_cpu_type.h | 1 + libop/op_events.c | 1 + libop/op_hw_specific.h | 2 + utils/ophelp.c | 1 + 8 files changed, 218 insertions(+) diff --git a/events/Makefile.am b/events/Makefile.am index 13d063a2..174df0b3 100644 --- a/events/Makefile.am +++ b/events/Makefile.am @@ -21,6 +21,7 @@ event_files = \ i386/skylake/events i386/skylake/unit_masks \ i386/silvermont/events i386/silvermont/unit_masks \ i386/goldmont/events i386/goldmont/unit_masks \ + i386/goldmontplus/events i386/goldmontplus/unit_masks \ i386/knightslanding/events i386/knightslanding/unit_masks \ ia64/ia64/events ia64/ia64/unit_masks \ ia64/itanium2/events ia64/itanium2/unit_masks \ diff --git a/events/i386/goldmontplus/events b/events/i386/goldmontplus/events new file mode 100644 index 00000000..e2a86329 --- /dev/null +++ b/events/i386/goldmontplus/events @@ -0,0 +1,38 @@ +# +# Intel "Goldmont Plus" microarchitecture core events. +# +# See http://ark.intel.com/ for help in identifying Goldmont based CPUs +# +# Note the minimum counts are not discovered experimentally and could be likely +# lowered in many cases without ill effect. +# +event:0x3c counters:cpuid um:cpu_clk_unhalted minimum:2000003 name:cpu_clk_unhalted : +event:0x03 counters:cpuid um:ld_blocks minimum:200003 name:ld_blocks : +event:0x08 counters:cpuid um:dtlb_load_misses minimum:200003 name:dtlb_load_misses : +event:0x0e counters:cpuid um:uops_issued minimum:200003 name:uops_issued_any : +event:0x13 counters:cpuid um:misalign_mem_ref minimum:200003 name:misalign_mem_ref : +event:0x2e counters:cpuid um:longest_lat_cache minimum:200003 name:longest_lat_cache : +event:0x30 counters:cpuid um:l2_reject_xq minimum:200003 name:l2_reject_xq_all : +event:0x31 counters:cpuid um:core_reject_l2q minimum:200003 name:core_reject_l2q_all : +event:0x49 counters:cpuid um:dtlb_store_misses minimum:2000003 name:dtlb_store_misses : +event:0x4f counters:cpuid um:ept minimum:200003 name:ept : +event:0x51 counters:cpuid um:dl1 minimum:200003 name:dl1_dirty_eviction : +event:0x80 counters:cpuid um:icache minimum:200003 name:icache : +event:0x81 counters:cpuid um:itlb minimum:200003 name:itlb_miss : +event:0x85 counters:cpuid um:itlb_misses minimum:2000003 name:itlb_misses : +event:0x86 counters:cpuid um:fetch_stall minimum:200003 name:fetch_stall_icache_fill_pending_cycles : +event:0x9c counters:cpuid um:uops_not_delivered minimum:200003 name:uops_not_delivered_any : +event:0xbd counters:cpuid um:tlb_flushes minimum:20003 name:tlb_flushes : +event:0xc0 counters:cpuid um:inst_retired minimum:2000003 name:inst_retired : +event:0xc2 counters:cpuid um:uops_retired minimum:2000003 name:uops_retired : +event:0xc3 counters:cpuid um:machine_clears minimum:200003 name:machine_clears : +event:0xc4 counters:cpuid um:br_inst_retired minimum:200003 name:br_inst_retired : +event:0xc5 counters:cpuid um:br_misp_retired minimum:200003 name:br_misp_retired : +event:0xca counters:cpuid um:issue_slots_not_consumed minimum:200003 name:issue_slots_not_consumed : +event:0xcb counters:cpuid um:hw_interrupts minimum:200003 name:hw_interrupts : +event:0xcd counters:cpuid um:cycles_div_busy minimum:2000003 name:cycles_div_busy : +event:0xd0 counters:cpuid um:mem_uops_retired minimum:200003 name:mem_uops_retired : +event:0xd1 counters:cpuid um:mem_load_uops_retired minimum:200003 name:mem_load_uops_retired : +event:0xe6 counters:cpuid um:baclears minimum:200003 name:baclears : +event:0xe7 counters:cpuid um:ms_decoded minimum:200003 name:ms_decoded_ms_entry : +event:0xe9 counters:cpuid um:decode_restriction minimum:200003 name:decode_restriction_predecode_wrong : diff --git a/events/i386/goldmontplus/unit_masks b/events/i386/goldmontplus/unit_masks new file mode 100644 index 00000000..da7733c6 --- /dev/null +++ b/events/i386/goldmontplus/unit_masks @@ -0,0 +1,173 @@ +# +# Unit masks for the Intel "Goldmont Plus" micro architecture +# +# See http://ark.intel.com/ for help in identifying Goldmont based CPUs +# +name:core_reject_l2q type:mandatory default:0x0 + 0x0 extra: all Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops. +name:decode_restriction type:mandatory default:0x1 + 0x1 extra: predecode_wrong Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect. +name:dl1 type:mandatory default:0x1 + 0x1 extra: dirty_eviction Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback. +name:fetch_stall type:mandatory default:0x2 + 0x2 extra: icache_fill_pending_cycles Counts cycles that an ICache miss is outstanding, and instruction fetch is stalled. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes, while an Icache miss outstanding. Note this event is not the same as cycles to retrieve an instruction due to an Icache miss. Rather, it is the part of the Instruction Cache (ICache) miss time where no bytes are available for the decoder. +name:itlb type:mandatory default:0x4 + 0x4 extra: miss Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB. +name:l2_reject_xq type:mandatory default:0x0 + 0x0 extra: all Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims. +name:ms_decoded type:mandatory default:0x1 + 0x1 extra: ms_entry Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear. +name:uops_issued type:mandatory default:0x0 + 0x0 extra: any Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear. +name:uops_not_delivered type:mandatory default:0x0 + 0x0 extra: any This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue. +name:cpu_clk_unhalted type:exclusive default:core_p + 0x0 extra: core_p Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter. + 0x1 extra: ref Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter. +name:ld_blocks type:exclusive default:all_block + 0x10 extra: all_block Counts anytime a load that retires is blocked for any reason. + 0x10 extra:pebs all_block_pebs Counts anytime a load that retires is blocked for any reason. + 0x8 extra: utlb_miss Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB). + 0x8 extra:pebs utlb_miss_pebs Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB). + 0x2 extra: store_forward Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted. + 0x2 extra:pebs store_forward_pebs Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted. + 0x1 extra: data_unknown Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available. + 0x1 extra:pebs data_unknown_pebs Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available. + 0x4 extra: u4k_alias Counts loads that block because their address modulo 4K matches a pending store. + 0x4 extra:pebs u4k_alias_pebs Counts loads that block because their address modulo 4K matches a pending store. +name:dtlb_load_misses type:exclusive default:walk_pending + 0x2 extra: walk_completed_4k Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault. + 0x4 extra: walk_completed_2m_4m Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault. + 0x8 extra: walk_completed_1gb Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault. + 0x10 extra: walk_pending Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks. +name:dtlb_store_misses type:exclusive default:walk_pending + 0x2 extra: walk_completed_4k Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault. + 0x4 extra: walk_completed_2m_4m Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault. + 0x8 extra: walk_completed_1gb Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault. + 0x10 extra: walk_pending Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks. +name:ept type:exclusive default:walk_pending + 0x10 extra: walk_pending Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks. +name:itlb_misses type:exclusive default:walk_pending + 0x2 extra: walk_completed_4k Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault. + 0x4 extra: walk_completed_2m_4m Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault. + 0x8 extra: walk_completed_1gb Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault. + 0x10 extra: walk_pending Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks. +name:tlb_flushes type:exclusive default:stlb_any + 0x20 extra: stlb_any Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3. +name:misalign_mem_ref type:exclusive default:load_page_split + 0x2 extra: load_page_split Counts when a memory load of a uop spans a page boundary (a split) is retired. + 0x2 extra:pebs load_page_split_pebs Counts when a memory load of a uop spans a page boundary (a split) is retired. + 0x4 extra: store_page_split Counts when a memory store of a uop spans a page boundary (a split) is retired. + 0x4 extra:pebs store_page_split_pebs Counts when a memory store of a uop spans a page boundary (a split) is retired. +name:longest_lat_cache type:exclusive default:0x4f + 0x4f extra: reference Counts memory requests originating from the core that reference a cache line in the L2 cache. + 0x41 extra: miss Counts memory requests originating from the core that miss in the L2 cache. +name:icache type:exclusive default:0x1 + 0x1 extra: hit Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture. + 0x2 extra: misses Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture. + 0x3 extra: accesses Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line. This event counts differently than Intel processors based on Silvermont microarchitecture. +name:inst_retired type:exclusive default:any + 0x0 extra: any Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event. + 0x0 extra: any_p Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time. + 0x0 extra:pebs any_p_pebs Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time. +name:uops_retired type:exclusive default:any + 0x0 extra: any Counts uops which retired + 0x0 extra:pebs any_pebs Counts uops which retired + 0x1 extra: ms Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist. + 0x1 extra:pebs ms_pebs Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist. + 0x8 extra: fpdiv Counts the number of floating point divide uops retired. + 0x8 extra:pebs fpdiv_pebs Counts the number of floating point divide uops retired. + 0x10 extra: idiv Counts the number of integer divide uops retired. + 0x10 extra:pebs idiv_pebs Counts the number of integer divide uops retired. +name:machine_clears type:exclusive default:all + 0x0 extra: all Counts machine clears for any reason + 0x1 extra: smc Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors. + 0x2 extra: memory_ordering Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data. + 0x4 extra: fp_assist Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result. + 0x8 extra: disambiguation Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address. + 0x20 extra: page_fault Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation. +name:br_inst_retired type:exclusive default:all_branches + 0x0 extra: all_branches Counts branch instructions retired for all branch types. This is an architectural performance event. + 0x0 extra:pebs all_branches_pebs Counts branch instructions retired for all branch types. This is an architectural performance event. + 0x7e extra: jcc Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken. + 0x7e extra:pebs jcc_pebs Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken. + 0x80 extra: all_taken_branches Counts the number of taken branch instructions retired. + 0x80 extra:pebs all_taken_branches_pebs Counts the number of taken branch instructions retired. + 0xfe extra: taken_jcc Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken. + 0xfe extra:pebs taken_jcc_pebs Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken. + 0xf9 extra: call Counts near CALL branch instructions retired. + 0xf9 extra:pebs call_pebs Counts near CALL branch instructions retired. + 0xfd extra: rel_call Counts near relative CALL branch instructions retired. + 0xfd extra:pebs rel_call_pebs Counts near relative CALL branch instructions retired. + 0xfb extra: ind_call Counts near indirect CALL branch instructions retired. + 0xfb extra:pebs ind_call_pebs Counts near indirect CALL branch instructions retired. + 0xf7 extra: return Counts near return branch instructions retired. + 0xf7 extra:pebs return_pebs Counts near return branch instructions retired. + 0xeb extra: non_return_ind Counts near indirect call or near indirect jmp branch instructions retired. + 0xeb extra:pebs non_return_ind_pebs Counts near indirect call or near indirect jmp branch instructions retired. + 0xbf extra: far_branch Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return. + 0xbf extra:pebs far_branch_pebs Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return. +name:br_misp_retired type:exclusive default:all_branches + 0x0 extra: all_branches Counts mispredicted branch instructions retired including all branch types. + 0x0 extra:pebs all_branches_pebs Counts mispredicted branch instructions retired including all branch types. + 0x7e extra: jcc Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition). + 0x7e extra:pebs jcc_pebs Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition). + 0xfe extra: taken_jcc Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken. + 0xfe extra:pebs taken_jcc_pebs Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken. + 0xfb extra: ind_call Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted. + 0xfb extra:pebs ind_call_pebs counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted. + 0xf7 extra: return Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted. + 0xf7 extra:pebs return_pebs Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted. + 0xeb extra: non_return_ind Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted. + 0xeb extra:pebs non_return_ind_pebs Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted. +name:issue_slots_not_consumed type:exclusive default:0x0 + 0x0 extra: any Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY) + 0x1 extra: resource_full Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count. + 0x2 extra: recovery Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue. +name:hw_interrupts type:exclusive default:0x1 + 0x1 extra: received Counts hardware interrupts received by the processor. + 0x4 extra: pending_and_masked Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0). +name:cycles_div_busy type:exclusive default:0x0 + 0x0 extra: all Counts core cycles if either divide unit is busy. + 0x1 extra: idiv Counts core cycles the integer divide unit is busy. + 0x2 extra: fpdiv Counts core cycles the floating point divide unit is busy. +name:mem_uops_retired type:exclusive default:all + 0x83 extra: all Counts the number of memory uops retired that is either a loads or a store or both. + 0x81 extra: all_loads Counts the number of load uops retired + 0x81 extra:pebs all_loads_pebs Counts the number of load uops retired + 0x82 extra: all_stores Counts the number of store uops retired. + 0x82 extra:pebs all_stores_pebs Counts the number of store uops retired. + 0x83 extra:pebs all_pebs Counts the number of memory uops retired that is either a loads or a store or both. + 0x11 extra: dtlb_miss_loads Counts load uops retired that caused a DTLB miss. + 0x11 extra:pebs dtlb_miss_loads_pebs Counts load uops retired that caused a DTLB miss. + 0x12 extra: dtlb_miss_stores Counts store uops retired that caused a DTLB miss. + 0x12 extra:pebs dtlb_miss_stores_pebs Counts store uops retired that caused a DTLB miss. + 0x13 extra: dtlb_miss Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss. + 0x13 extra:pebs dtlb_miss_pebs Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss. + 0x21 extra: lock_loads Counts locked memory uops retired. This includes "regular" locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks. + 0x21 extra:pebs lock_loads_pebs Counts locked memory uops retired. This includes "regular" locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks. + 0x41 extra: split_loads Counts load uops retired where the data requested spans a 64 byte cache line boundary. + 0x41 extra:pebs split_loads_pebs Counts load uops retired where the data requested spans a 64 byte cache line boundary. + 0x42 extra: split_stores Counts store uops retired where the data requested spans a 64 byte cache line boundary. + 0x42 extra:pebs split_stores_pebs Counts store uops retired where the data requested spans a 64 byte cache line boundary. + 0x43 extra: split Counts memory uops retired where the data requested spans a 64 byte cache line boundary. + 0x43 extra:pebs split_pebs Counts memory uops retired where the data requested spans a 64 byte cache line boundary. +name:mem_load_uops_retired type:exclusive default:l1_hit + 0x1 extra: l1_hit Counts load uops retired that hit the L1 data cache. + 0x1 extra:pebs l1_hit_pebs Counts load uops retired that hit the L1 data cache. + 0x8 extra: l1_miss Counts load uops retired that miss the L1 data cache. + 0x8 extra:pebs l1_miss_pebs Counts load uops retired that miss the L1 data cache. + 0x2 extra: l2_hit Counts load uops retired that hit in the L2 cache. + 0x2 extra:pebs l2_hit_pebs Counts load uops retired that hit in the L2 cache. + 0x10 extra: l2_miss Counts load uops retired that miss in the L2 cache. + 0x10 extra:pebs l2_miss_pebs Counts load uops retired that miss in the L2 cache. + 0x20 extra: hitm Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks. + 0x20 extra:pebs hitm_pebs Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks. + 0x40 extra: wcb_hit Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs. + 0x40 extra:pebs wcb_hit_pebs Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs. + 0x80 extra: dram_hit Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response. + 0x80 extra:pebs dram_hit_pebs Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response. +name:baclears type:exclusive default:0x1 + 0x1 extra: all Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns. + 0x8 extra: return Counts BACLEARS on return instructions. + 0x10 extra: cond Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches. diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c index 610121ee..feea9487 100644 --- a/libop/op_cpu_type.c +++ b/libop/op_cpu_type.c @@ -117,6 +117,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = { { "Intel Broadwell microarchitecture", "i386/broadwell", CPU_BROADWELL, 4 }, { "Intel Skylake microarchitecture", "i386/skylake", CPU_SKYLAKE, 4 }, { "Intel Goldmont microarchitecture", "i386/goldmont", CPU_GOLDMONT, 4 }, + { "Intel Goldmont Plus microarchitecture", "i386/goldmontplus", CPU_GOLDMONTPLUS, 4 }, { "ppc64 POWER9", "ppc64/power9", CPU_PPC64_POWER9, 6 }, { "Intel Knights Landing", "i386/knightslanding", CPU_KNIGHTSLANDING, 4 }, }; diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h index e2f8f60f..3bfd4ebd 100644 --- a/libop/op_cpu_type.h +++ b/libop/op_cpu_type.h @@ -103,6 +103,7 @@ typedef enum { CPU_BROADWELL, /** < Intel Broadwell (Core-M) microarchitecture */ CPU_SKYLAKE, /** < Intel Skylake microarchitecture */ CPU_GOLDMONT, /** < Intel Goldmont microarchitecture */ + CPU_GOLDMONTPLUS, /** < Intel Goldmont Plus microarchitecture */ CPU_PPC64_POWER9, /**< ppc64 POWER8 family */ CPU_KNIGHTSLANDING, /** Intel Knights Landing microarchitecture */ MAX_CPU_TYPE diff --git a/libop/op_events.c b/libop/op_events.c index acadaa7e..5125647d 100644 --- a/libop/op_events.c +++ b/libop/op_events.c @@ -1214,6 +1214,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr) break; case CPU_GOLDMONT: + case CPU_GOLDMONTPLUS: case CPU_SKYLAKE: descr->name = "cpu_clk_unhalted"; break; diff --git a/libop/op_hw_specific.h b/libop/op_hw_specific.h index 840e7b3c..94969f48 100644 --- a/libop/op_hw_specific.h +++ b/libop/op_hw_specific.h @@ -170,6 +170,8 @@ static inline op_cpu op_cpu_specific_type(op_cpu cpu_type) case 0x57: case 0x85: return CPU_KNIGHTSLANDING; + case 0x7a: + return CPU_GOLDMONTPLUS; } } return cpu_type; diff --git a/utils/ophelp.c b/utils/ophelp.c index 9a2a7ddb..a07b2152 100644 --- a/utils/ophelp.c +++ b/utils/ophelp.c @@ -545,6 +545,7 @@ int main(int argc, char const * argv[]) case CPU_SKYLAKE: case CPU_SILVERMONT: case CPU_GOLDMONT: + case CPU_GOLDMONTPLUS: case CPU_WESTMERE: case CPU_SANDYBRIDGE: case CPU_IVYBRIDGE:
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