File 5eb1bbfb-x86-ucode-intel-WBINVD-before-updating.patch of Package xen.16555

# Commit 77c82949990edaf21130be842a289a7fb7a439e1
# Date 2020-05-05 20:18:19 +0100
# Author Ashok Raj <ashok.raj@intel.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86/ucode/intel: Writeback and invalidate caches before updating microcode

Updating microcode is less error prone when caches have been flushed and
depending on what exactly the microcode is updating. For example, some of the
issues around certain Broadwell parts can be addressed by doing a full cache
flush.

Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
[Linux commit 91df9fdf51492aec9fed6b4cbd33160886740f47, ported to Xen]
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/microcode_intel.c
+++ b/xen/arch/x86/microcode_intel.c
@@ -30,6 +30,7 @@
 
 #include <asm/msr.h>
 #include <asm/processor.h>
+#include <asm/system.h>
 #include <asm/microcode.h>
 
 #define pr_debug(x...) ((void)0)
@@ -294,6 +295,8 @@ static int apply_microcode(unsigned int
     /* serialize access to the physical write to MSR 0x79 */
     spin_lock_irqsave(&microcode_update_lock, flags);
 
+    wbinvd();
+
     /* write microcode via MSR 0x79 */
     wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)uci->mc.mc_intel->bits);
     wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);