File 5ac63737-x86-disable-XPTI-when-RDCL_NO.patch of Package xen.7652
# Commit bee0732d2066691d8204e418d10110930ee4d4f8
# Date 2018-04-05 15:48:23 +0100
# Author Jan Beulich <JBeulich@suse.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86: disable XPTI when RDCL_NO
Use the respective ARCH_CAPABILITIES MSR bit, but don't expose the MSR
to guests yet.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Tested-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
--- sle12sp2.orig/tools/libxl/libxl_cpuid.c 2018-03-28 16:33:59.000000000 +0200
+++ sle12sp2/tools/libxl/libxl_cpuid.c 2018-05-18 11:55:19.000000000 +0200
@@ -160,6 +160,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
{"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1},
{"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1},
+ {"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1},
{"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
{"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
{"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
--- sle12sp2.orig/tools/misc/xen-cpuid.c 2018-03-28 16:33:59.000000000 +0200
+++ sle12sp2/tools/misc/xen-cpuid.c 2018-05-18 11:55:19.000000000 +0200
@@ -152,8 +152,9 @@ static const char *str_7d0[32] =
[0 ... 25] = "REZ",
[26] = "ibrsb", [27] = "stibp",
+ [28] = "REZ", [29] = "arch_caps",
- [28 ... 31] = "REZ",
+ [30 ... 31] = "REZ",
};
static struct {
--- sle12sp2.orig/xen/arch/x86/cpu/common.c 2018-04-18 14:40:31.000000000 +0200
+++ sle12sp2/xen/arch/x86/cpu/common.c 2018-05-18 12:32:19.112352700 +0200
@@ -430,6 +430,9 @@ void identify_cpu(struct cpuinfo_x86 *c)
if (test_bit(X86_FEATURE_RSB_VMEXIT,
boot_cpu_data.x86_capability))
__set_bit(X86_FEATURE_RSB_VMEXIT, c->x86_capability);
+ if (test_bit(X86_FEATURE_NO_XPTI,
+ boot_cpu_data.x86_capability))
+ __set_bit(X86_FEATURE_NO_XPTI, c->x86_capability);
/* AND the already accumulated flags with these */
for ( i = 0 ; i < NCAPINTS ; i++ )
--- sle12sp2.orig/xen/arch/x86/mm.c 2018-03-28 16:33:59.000000000 +0200
+++ sle12sp2/xen/arch/x86/mm.c 2018-05-18 11:55:19.000000000 +0200
@@ -4011,7 +4011,7 @@ long do_mmu_update(
* to the page lock we hold, its pinned status, and uses on
* this (v)CPU.
*/
- if ( !rc && this_cpu(root_pgt) &&
+ if ( !rc && !cpu_has_no_xpti &&
((page->u.inuse.type_info & PGT_count_mask) >
(1 + !!(page->u.inuse.type_info & PGT_pinned) +
(pagetable_get_pfn(curr->arch.guest_table) == mfn) +
--- sle12sp2.orig/xen/arch/x86/setup.c 2018-03-29 00:00:00.000000000 +0200
+++ sle12sp2/xen/arch/x86/setup.c 2018-05-18 11:55:19.000000000 +0200
@@ -112,6 +112,9 @@ struct cpuinfo_x86 __read_mostly boot_cp
unsigned long __read_mostly mmu_cr4_features = XEN_MINIMAL_CR4;
+static int8_t __initdata opt_xpti = -1;
+boolean_param("xpti", opt_xpti);
+
bool_t __read_mostly acpi_disabled;
bool_t __initdata acpi_force;
static char __initdata acpi_param[10] = "";
@@ -1431,6 +1434,22 @@ void __init noreturn __start_xen(unsigne
cr4_pv32_mask = mmu_cr4_features & XEN_CR4_PV32_BITS;
+ if ( opt_xpti < 0 )
+ {
+ uint64_t caps = 0;
+
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+ caps = ARCH_CAPABILITIES_RDCL_NO;
+ else if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) )
+ rdmsrl(MSR_ARCH_CAPABILITIES, caps);
+
+ opt_xpti = !(caps & ARCH_CAPABILITIES_RDCL_NO);
+ }
+ if ( opt_xpti )
+ setup_clear_cpu_cap(X86_FEATURE_NO_XPTI);
+ else
+ __set_bit(X86_FEATURE_NO_XPTI, boot_cpu_data.x86_capability);
+
if ( cpu_has_fsgsbase )
set_in_cr4(X86_CR4_FSGSBASE);
--- sle12sp2.orig/xen/arch/x86/smpboot.c 2018-04-18 14:40:31.000000000 +0200
+++ sle12sp2/xen/arch/x86/smpboot.c 2018-05-18 11:55:19.000000000 +0200
@@ -748,8 +748,6 @@ static int clone_mapping(const void *ptr
return 0;
}
-static __read_mostly int8_t opt_xpti = -1;
-boolean_param("xpti", opt_xpti);
DEFINE_PER_CPU(root_pgentry_t *, root_pgt);
static root_pgentry_t common_pgt;
@@ -762,7 +760,7 @@ static int setup_cpu_root_pgt(unsigned i
unsigned int off;
int rc;
- if ( !opt_xpti )
+ if ( cpu_has_no_xpti )
return 0;
rpt = alloc_xen_pagetable();
@@ -1036,9 +1034,6 @@ void __init smp_prepare_cpus(unsigned in
stack_base[0] = stack_start;
- if ( opt_xpti < 0 )
- opt_xpti = boot_cpu_data.x86_vendor != X86_VENDOR_AMD;
-
rc = setup_cpu_root_pgt(0);
if ( rc )
panic("Error %d setting up PV root page table\n", rc);
--- sle12sp2.orig/xen/include/asm-x86/cpufeature.h 2018-03-29 00:00:00.000000000 +0200
+++ sle12sp2/xen/include/asm-x86/cpufeature.h 2018-05-18 11:55:19.000000000 +0200
@@ -26,6 +26,7 @@ XEN_CPUFEATURE(XEN_IBRS_CLEAR, (FSCAPINT
XEN_CPUFEATURE(RSB_NATIVE, (FSCAPINTS+0)*32+ 16) /* RSB overwrite needed for native */
XEN_CPUFEATURE(RSB_VMEXIT, (FSCAPINTS+0)*32+ 17) /* RSB overwrite needed for vmexit */
XEN_CPUFEATURE(MFENCE_RDTSC, (FSCAPINTS+0)*32+ 18) /* MFENCE synchronizes RDTSC */
+XEN_CPUFEATURE(NO_XPTI, (FSCAPINTS+0)*32+ 19) /* XPTI mitigation not in use */
#define NCAPINTS (FSCAPINTS + 1) /* N 32-bit words worth of info */
@@ -100,6 +101,7 @@ XEN_CPUFEATURE(MFENCE_RDTSC, (FSCAPINTS+
#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
#define cpu_has_cmp_legacy boot_cpu_has(X86_FEATURE_CMP_LEGACY)
#define cpu_has_lfence_dispatch boot_cpu_has(X86_FEATURE_LFENCE_DISPATCH)
+#define cpu_has_no_xpti boot_cpu_has(X86_FEATURE_NO_XPTI)
enum _cache_type {
CACHE_TYPE_NULL = 0,
--- sle12sp2.orig/xen/include/asm-x86/msr-index.h 2018-03-29 00:00:00.000000000 +0200
+++ sle12sp2/xen/include/asm-x86/msr-index.h 2018-05-18 11:55:19.000000000 +0200
@@ -40,6 +40,8 @@
#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
#define MSR_ARCH_CAPABILITIES 0x0000010a
+#define ARCH_CAPABILITIES_RDCL_NO (_AC(1, ULL) << 0)
+#define ARCH_CAPABILITIES_IBRS_ALL (_AC(1, ULL) << 1)
/* Intel MSRs. Some also available on other CPUs */
#define MSR_IA32_PERFCTR0 0x000000c1
--- sle12sp2.orig/xen/include/public/arch-x86/cpufeatureset.h 2018-03-28 16:33:59.000000000 +0200
+++ sle12sp2/xen/include/public/arch-x86/cpufeatureset.h 2018-05-18 11:55:19.000000000 +0200
@@ -229,6 +229,7 @@ XEN_CPUFEATURE(IBPB, 8*32+12) /
/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */
XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */
+XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */
#endif /* XEN_CPUFEATURE */
