File 5afc13ae-6-x86-elide-MSR_SPEC_CTRL-handling-in-idle.patch of Package xen.7652

# Commit 94df6e8588e35cc2028ccb3fd2921c6e6360605e
# Date 2018-05-16 12:19:10 +0100
# Author Andrew Cooper <andrew.cooper3@citrix.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86/spec_ctrl: Elide MSR_SPEC_CTRL handling in idle context when possible

If Xen is virtualising MSR_SPEC_CTRL handling for guests, but using 0 as its
own MSR_SPEC_CTRL value, spec_ctrl_{enter,exit}_idle() need not write to the
MSR.

Requested-by: Jan Beulich <JBeulich@suse.com>
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- sle12sp2.orig/xen/arch/x86/cpu/common.c	2018-05-23 11:11:55.000000000 +0200
+++ sle12sp2/xen/arch/x86/cpu/common.c	2018-05-23 11:13:56.000000000 +0200
@@ -429,6 +429,9 @@ void identify_cpu(struct cpuinfo_x86 *c)
 		if (test_bit(X86_FEATURE_NO_XPTI,
 		             boot_cpu_data.x86_capability))
 			__set_bit(X86_FEATURE_NO_XPTI, c->x86_capability);
+		if (test_bit(X86_FEATURE_SC_MSR_IDLE,
+			     boot_cpu_data.x86_capability))
+			__set_bit(X86_FEATURE_SC_MSR_IDLE, c->x86_capability);
 
 		/* AND the already accumulated flags with these */
 		for ( i = 0 ; i < NCAPINTS ; i++ )
--- sle12sp2.orig/xen/arch/x86/spec_ctrl.c	2018-05-23 11:11:55.000000000 +0200
+++ sle12sp2/xen/arch/x86/spec_ctrl.c	2018-05-23 11:13:56.000000000 +0200
@@ -327,6 +327,10 @@ void __init init_speculation_mitigations
     /* (Re)init BSP state now that default_spec_ctrl_flags has been calculated. */
     init_shadow_spec_ctrl_state();
 
+    /* If Xen is using any MSR_SPEC_CTRL settings, adjust the idle path. */
+    if ( default_xen_spec_ctrl )
+        __set_bit(X86_FEATURE_SC_MSR_IDLE, boot_cpu_data.x86_capability);
+
     print_details(thunk, caps);
 }
 
--- sle12sp2.orig/xen/include/asm-x86/cpufeature.h	2018-05-23 11:11:55.000000000 +0200
+++ sle12sp2/xen/include/asm-x86/cpufeature.h	2018-05-23 11:13:56.000000000 +0200
@@ -26,6 +26,7 @@ XEN_CPUFEATURE(SC_RSB_PV,	(FSCAPINTS+0)*
 XEN_CPUFEATURE(SC_RSB_HVM,	(FSCAPINTS+0)*32+ 17) /* RSB overwrite needed for HVM */
 XEN_CPUFEATURE(MFENCE_RDTSC,	(FSCAPINTS+0)*32+ 18) /* MFENCE synchronizes RDTSC */
 XEN_CPUFEATURE(NO_XPTI,		(FSCAPINTS+0)*32+ 19) /* XPTI mitigation not in use */
+XEN_CPUFEATURE(SC_MSR_IDLE,	(FSCAPINTS+0)*32+ 20) /* SC_MSR && default_xen_spec_ctrl */
 
 #define NCAPINTS (FSCAPINTS + 1) /* N 32-bit words worth of info */
 
--- sle12sp2.orig/xen/include/asm-x86/spec_ctrl.h	2018-05-23 11:11:24.000000000 +0200
+++ sle12sp2/xen/include/asm-x86/spec_ctrl.h	2018-05-23 11:13:56.000000000 +0200
@@ -54,7 +54,7 @@ static always_inline void spec_ctrl_ente
     barrier();
     asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", %c3)
                    :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
-                      "i" (X86_FEATURE_SC_MSR)
+                      "i" (X86_FEATURE_SC_MSR_IDLE)
                    : "memory" );
 }
 
@@ -71,7 +71,7 @@ static always_inline void spec_ctrl_exit
     barrier();
     asm volatile ( ALTERNATIVE(ASM_NOP3, "wrmsr", %c3)
                    :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0),
-                      "i" (X86_FEATURE_SC_MSR)
+                      "i" (X86_FEATURE_SC_MSR_IDLE)
                    : "memory" );
 }