File 0447-i386-Add-bit-2-of-SPEC_CTRL-MSR-sup.patch of Package qemu.7445

From 0b7b77c8b3102d56366bb5df59355170d7946733 Mon Sep 17 00:00:00 2001
From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Date: Wed, 11 Apr 2018 17:26:51 -0400
Subject: [PATCH] i386: Add bit(2) of SPEC_CTRL MSR support - SSBD

i386: Add bit(2) of SPEC_CTRL MSR support - Reduced Data Speculation

Now users can do:

cpu host,+spec-ctrl,+ssbd

to have both IBRS and SSBD support.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
[BR: BSC#1092885 CVE-2018-3639]
Signed-off-by: Bruce Rogers <brogers@suse.com>
---
 target-i386/cpu.c | 2 +-
 target-i386/cpu.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index d68ff6eedc..688082a265 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -270,7 +270,7 @@ static const char *cpuid_7_0_edx_feature_name[] = {
     NULL, NULL, NULL, NULL,
     NULL, NULL, NULL, NULL,
     NULL, NULL, "spec-ctrl", NULL,
-    NULL, NULL, NULL, NULL,
+    NULL, NULL, NULL, "ssbd",
 };
 
 static const char *cpuid_ibpb_ebx_feature_name[] = {
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index f6c6ea07f7..675ff254a9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -562,6 +562,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_EBX_ADX      (1U << 19)
 #define CPUID_7_0_EBX_SMAP     (1U << 20)
 #define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
+#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */
 
 #define CPUID_8000_0008_EBX_IBPB    (1U << 12) /* Indirect Branch Prediction Barrier */