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SUSE:SLE-15-SP3:GA
llvm9.27235
llvm-riscv64-fix-cffi.diff
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File llvm-riscv64-fix-cffi.diff of Package llvm9.27235
commit c6b09bff5671600f8e764d3847023d0996f328d9 Author: Luís Marques <luismarques@lowrisc.org> Date: Thu Nov 14 18:27:42 2019 +0000 [RISCV] Fix wrong CFI directives Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723 Index: llvm-9.0.1.src/lib/Target/RISCV/RISCVFrameLowering.cpp =================================================================== --- llvm-9.0.1.src.orig/lib/Target/RISCV/RISCVFrameLowering.cpp +++ llvm-9.0.1.src/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -205,7 +205,6 @@ void RISCVFrameLowering::emitEpilogue(Ma MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); DebugLoc DL = MBBI->getDebugLoc(); - const RISCVInstrInfo *TII = STI.getInstrInfo(); unsigned FPReg = getFPReg(STI); unsigned SPReg = getSPReg(STI); @@ -226,47 +225,8 @@ void RISCVFrameLowering::emitEpilogue(Ma MachineInstr::FrameDestroy); } - if (hasFP(MF)) { - // To find the instruction restoring FP from stack. - for (auto &I = LastFrameDestroy; I != MBBI; ++I) { - if (I->mayLoad() && I->getOperand(0).isReg()) { - unsigned DestReg = I->getOperand(0).getReg(); - if (DestReg == FPReg) { - // If there is frame pointer, after restoring $fp registers, we - // need adjust CFA to ($sp - FPOffset). - // Emit ".cfi_def_cfa $sp, -FPOffset" - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa( - nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset)); - BuildMI(MBB, std::next(I), DL, - TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); - break; - } - } - } - } - - // Add CFI directives for callee-saved registers. - const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); - // Iterate over list of callee-saved registers and emit .cfi_restore - // directives. - for (const auto &Entry : CSI) { - unsigned Reg = Entry.getReg(); - unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore( - nullptr, RI->getDwarfRegNum(Reg, true))); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); - } - // Deallocate stack adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy); - - // After restoring $sp, we need to adjust CFA to $(sp + 0) - // Emit ".cfi_def_cfa_offset 0" - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex); } int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, Index: llvm-9.0.1.src/test/CodeGen/RISCV/exception-pointer-register.ll =================================================================== --- llvm-9.0.1.src.orig/test/CodeGen/RISCV/exception-pointer-register.ll +++ llvm-9.0.1.src/test/CodeGen/RISCV/exception-pointer-register.ll @@ -40,11 +40,7 @@ define void @caller(i1* %p) personality ; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) -; RV32I-NEXT: .cfi_restore ra -; RV32I-NEXT: .cfi_restore s0 -; RV32I-NEXT: .cfi_restore s1 ; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB0_4: # %lpad ; RV32I-NEXT: .Ltmp4: @@ -81,11 +77,7 @@ define void @caller(i1* %p) personality ; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld ra, 24(sp) -; RV64I-NEXT: .cfi_restore ra -; RV64I-NEXT: .cfi_restore s0 -; RV64I-NEXT: .cfi_restore s1 ; RV64I-NEXT: addi sp, sp, 32 -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ; RV64I-NEXT: .LBB0_4: # %lpad ; RV64I-NEXT: .Ltmp4: @@ -119,12 +111,10 @@ end2: define internal void @callee(i1* %p) { ; RV32I-LABEL: callee: ; RV32I: # %bb.0: -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: callee: ; RV64I: # %bb.0: -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret ret void } Index: llvm-9.0.1.src/test/CodeGen/RISCV/frame-info.ll =================================================================== --- llvm-9.0.1.src.orig/test/CodeGen/RISCV/frame-info.ll +++ llvm-9.0.1.src/test/CodeGen/RISCV/frame-info.ll @@ -20,12 +20,8 @@ define void @foo(i32 signext %size) { ; RV32-NEXT: call bar ; RV32-NEXT: addi sp, s0, -16 ; RV32-NEXT: lw s0, 8(sp) -; RV32-NEXT: .cfi_def_cfa sp, 16 ; RV32-NEXT: lw ra, 12(sp) -; RV32-NEXT: .cfi_restore ra -; RV32-NEXT: .cfi_restore s0 ; RV32-NEXT: addi sp, sp, 16 -; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret ; ; RV64-LABEL: foo: @@ -50,12 +46,8 @@ define void @foo(i32 signext %size) { ; RV64-NEXT: call bar ; RV64-NEXT: addi sp, s0, -16 ; RV64-NEXT: ld s0, 0(sp) -; RV64-NEXT: .cfi_def_cfa sp, 16 ; RV64-NEXT: ld ra, 8(sp) -; RV64-NEXT: .cfi_restore ra -; RV64-NEXT: .cfi_restore s0 ; RV64-NEXT: addi sp, sp, 16 -; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret entry: %0 = alloca i8, i32 %size, align 16 Index: llvm-9.0.1.src/test/CodeGen/RISCV/split-offsets.ll =================================================================== --- llvm-9.0.1.src.orig/test/CodeGen/RISCV/split-offsets.ll +++ llvm-9.0.1.src/test/CodeGen/RISCV/split-offsets.ll @@ -22,7 +22,6 @@ define void @test1([65536 x i32]** %sp, ; RV32I-NEXT: add a0, a1, a2 ; RV32I-NEXT: sw a4, 4(a0) ; RV32I-NEXT: sw a3, 0(a0) -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test1: @@ -38,7 +37,6 @@ define void @test1([65536 x i32]** %sp, ; RV64I-NEXT: add a0, a1, a2 ; RV64I-NEXT: sw a4, 4(a0) ; RV64I-NEXT: sw a3, 0(a0) -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret entry: %s = load [65536 x i32]*, [65536 x i32]** %sp @@ -74,7 +72,6 @@ define void @test2([65536 x i32]** %sp, ; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: blt a3, a2, .LBB1_1 ; RV32I-NEXT: .LBB1_2: # %while_end -; RV32I-NEXT: .cfi_def_cfa_offset 0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test2: @@ -99,7 +96,6 @@ define void @test2([65536 x i32]** %sp, ; RV64I-NEXT: sext.w a4, a3 ; RV64I-NEXT: blt a4, a2, .LBB1_1 ; RV64I-NEXT: .LBB1_2: # %while_end -; RV64I-NEXT: .cfi_def_cfa_offset 0 ; RV64I-NEXT: ret entry: %s = load [65536 x i32]*, [65536 x i32]** %sp
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