File xsa435-0-13.patch of Package xen.32200
From b4a23bf6293aadecfd03bf9e83974443e2eac9cb Mon Sep 17 00:00:00 2001
From: Andrew Cooper <andrew.cooper3@citrix.com>
Date: Fri, 28 Oct 2022 11:40:00 +0100
Subject: x86/cpuid: Infrastructure for leaves 7:1{ecx,edx}
We don't actually need ecx yet, but adding it in now will reduce the amount to
which leaf 7 is out of order in a featureset.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -212,6 +212,9 @@ int libxl_cpuid_parse_config(libxl_cpuid
{"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1},
{"ssbd", 0x00000007, 0, CPUID_REG_EDX, 31, 1},
+ {"intel-psfd", 0x00000007, 2, CPUID_REG_EDX, 0, 1},
+ {"mcdt-no", 0x00000007, 2, CPUID_REG_EDX, 5, 1},
+
{"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1},
{"cmplegacy", 0x80000001, NA, CPUID_REG_ECX, 1, 1},
{"svm", 0x80000001, NA, CPUID_REG_ECX, 2, 1},
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -183,6 +183,25 @@ static const char *str_e21a[32] =
[ 2] = "lfence+",
};
+static const char *str_7b1[32] =
+{
+};
+
+static const char *str_7c1[32] =
+{
+};
+
+static const char *str_7d1[32] =
+{
+};
+
+static const char *str_7d2[32] =
+{
+ [ 0] = "intel-psfd",
+
+ /* 4 */ [ 5] = "mcdt-no",
+};
+
static struct {
const char *name;
const char *abbr;
@@ -201,6 +220,10 @@ static struct {
{ "0x00000007:0.edx", "7d0", str_7d0 },
{ "0x00000007:1.eax", "7a1", str_7a1 },
{ "0x80000021.eax", "e21a", str_e21a },
+ { "0x00000007:1.ebx", "7b1", str_7b1 },
+ { "0x00000007:2.edx", "7d2", str_7d2 },
+ { "0x00000007:1.ecx", "7c1", str_7c1 },
+ { "0x00000007:1.edx", "7d1", str_7d1 },
};
#define COL_ALIGN "18"
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -418,11 +418,23 @@ static void generic_identify(struct cpui
= cpuid_eax(0x80000021);
/* Intel-defined flags: level 0x00000007 */
- if ( c->cpuid_level >= 0x00000007 )
- cpuid_count(0x00000007, 0, &tmp,
+ if (c->cpuid_level >= 7) {
+ cpuid_count(7, 0, &eax,
&c->x86_capability[cpufeat_word(X86_FEATURE_FSGSBASE)],
&c->x86_capability[cpufeat_word(X86_FEATURE_PKU)],
&c->x86_capability[cpufeat_word(X86_FEATURE_AVX512_4VNNIW)]);
+ if (eax > 0)
+ cpuid_count(7, 1,
+ &c->x86_capability[FEATURESET_7a1],
+ &c->x86_capability[FEATURESET_7b1],
+ &c->x86_capability[FEATURESET_7c1],
+ &c->x86_capability[FEATURESET_7d1]);
+ if (eax >= 2)
+ cpuid_count(7, 2,
+ &tmp, &tmp, &tmp,
+ &c->x86_capability[FEATURESET_7d2]);
+ }
+
if (c->cpuid_level >= 0xd)
cpuid_count(0xd, 1,
&c->x86_capability[cpufeat_word(X86_FEATURE_XSAVEOPT)],
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -331,6 +331,7 @@ int guest_rdmsr(const struct vcpu *v, ui
uint64_t msr_spec_ctrl_valid_bits(const struct cpuid_policy *cp)
{
bool ssbd = cp->feat.ssbd || cp->extd.amd_ssbd;
+ bool psfd = cp->feat.intel_psfd || cp->extd.psfd;
/*
* Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
@@ -338,6 +339,7 @@ uint64_t msr_spec_ctrl_valid_bits(const
*/
return (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
(ssbd ? SPEC_CTRL_SSBD : 0) |
+ (psfd ? SPEC_CTRL_PSFD : 0) |
0);
}
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -404,11 +404,13 @@ custom_param("pv-l1tf", parse_pv_l1tf);
static void __init print_details(enum ind_thunk thunk, uint64_t caps)
{
- unsigned int _7d0 = 0, e8b = 0, tmp;
+ unsigned int _7d0 = 0, _7d2 = 0, e8b = 0, max = 0, tmp;
/* Collect diagnostics about available mitigations. */
if ( boot_cpu_data.cpuid_level >= 7 )
- cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0);
+ cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0);
+ if ( max >= 2 )
+ cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2);
if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
@@ -448,6 +450,7 @@ static void __init print_details(enum in
(_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "",
(e8b & cpufeat_mask(X86_FEATURE_AMD_SSBD)) ||
(_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "",
+ (_7d2 & cpufeat_mask(X86_FEATURE_INTEL_PSFD)) ||
(e8b & cpufeat_mask(X86_FEATURE_PSFD)) ? " PSFD" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_MD_CLEAR)) ? " MD_CLEAR" : "",
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -270,6 +270,16 @@ XEN_CPUFEATURE(SSBD, 9*32+31) /
/* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */
XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */
+/* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */
+
+/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
+XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
+XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */
+
+/* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
+
+/* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
+
#endif /* XEN_CPUFEATURE */
/* Clean up from a default include. Close the enum (for C). */
--- a/xen/include/xen/lib/x86/cpuid.h
+++ b/xen/include/xen/lib/x86/cpuid.h
@@ -16,6 +16,10 @@
#define FEATURESET_7d0 9 /* 0x00000007:0.edx */
#define FEATURESET_7a1 10 /* 0x00000007:1.eax */
#define FEATURESET_e21a 11 /* 0x80000021.eax */
+#define FEATURESET_7b1 12 /* 0x00000007:1.ebx */
+#define FEATURESET_7d2 13 /* 0x00000007:2.edx */
+#define FEATURESET_7c1 14 /* 0x00000007:1.ecx */
+#define FEATURESET_7d1 15 /* 0x00000007:1.edx */
struct cpuid_leaf
{
@@ -68,8 +72,8 @@ static inline void cpuid_count_leaf(
#undef XCHG
#define CPUID_GUEST_NR_BASIC (0xdu + 1)
-#define CPUID_GUEST_NR_FEAT (0u + 1)
#define CPUID_GUEST_NR_CACHE (5u + 1)
+#define CPUID_GUEST_NR_FEAT (2u + 1)
#define CPUID_GUEST_NR_TOPO (1u + 1)
#define CPUID_GUEST_NR_XSTATE (62u + 1)
#define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1)
@@ -166,6 +170,31 @@ struct cpuid_policy
uint32_t _7d0;
struct { DECL_BITFIELD(7d0); };
};
+
+ /* Subleaf 1. */
+ union {
+ uint32_t _7a1;
+ struct { DECL_BITFIELD(7a1); };
+ };
+ union {
+ uint32_t _7b1;
+ struct { DECL_BITFIELD(7b1); };
+ };
+ union {
+ uint32_t _7c1;
+ struct { DECL_BITFIELD(7c1); };
+ };
+ union {
+ uint32_t _7d1;
+ struct { DECL_BITFIELD(7d1); };
+ };
+
+ /* Subleaf 2. */
+ uint32_t /* a */:32, /* b */:32, /* c */:32;
+ union {
+ uint32_t _7d2;
+ struct { DECL_BITFIELD(7d2); };
+ };
};
} feat;
@@ -304,6 +333,10 @@ static inline void cpuid_policy_to_featu
fs[FEATURESET_7d0] = p->feat._7d0;
fs[FEATURESET_7a1] = p->feat._7a1;
fs[FEATURESET_e21a] = p->extd.e21a;
+ fs[FEATURESET_7b1] = p->feat._7b1;
+ fs[FEATURESET_7d2] = p->feat._7d2;
+ fs[FEATURESET_7c1] = p->feat._7c1;
+ fs[FEATURESET_7d1] = p->feat._7d1;
}
/* Fill in a CPUID policy from a featureset bitmap. */
@@ -322,6 +355,10 @@ static inline void cpuid_featureset_to_p
p->feat._7d0 = fs[FEATURESET_7d0];
p->feat._7a1 = fs[FEATURESET_7a1];
p->extd.e21a = fs[FEATURESET_e21a];
+ p->feat._7b1 = fs[FEATURESET_7b1];
+ p->feat._7d2 = fs[FEATURESET_7d2];
+ p->feat._7c1 = fs[FEATURESET_7c1];
+ p->feat._7d1 = fs[FEATURESET_7d1];
}
const uint32_t *x86_cpuid_lookup_deep_deps(uint32_t feature);
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -269,7 +269,7 @@ def crunch_numbers(state):
# not IBRSB, and we pass this MSR directly to guests. Treating them
# as dependent features simplifies Xen's logic, and prevents the guest
# from seeing implausible configurations.
- IBRSB: [STIBP, SSBD],
+ IBRSB: [STIBP, SSBD, INTEL_PSFD],
}
deep_features = tuple(sorted(deps.keys()))
