File target-arm-Introduce-PREDDESC-field-defi.patch of Package qemu.30222
From: Richard Henderson <richard.henderson@linaro.org> Date: Tue, 12 Jan 2021 20:26:47 -1000 Subject: target/arm: Introduce PREDDESC field definitions Git-commit: b64ee454a4a086ed459bcda4c0bbb54e197841e4 SVE predicate operations cannot use the "usual" simd_desc encoding, because the lengths are not a multiple of 8. But we were abusing the SIMD_* fields to store values anyway. This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214. Introduce a new set of field definitions for exclusive use of predicates, so that it is obvious what kind of predicate we are manipulating. To be used in future patches. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bruce Rogers <brogers@suse.com> --- target/arm/internals.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756d3c4e5f34abe5f6411..73698587d6b8eeffd6ccd1515e7a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1312,6 +1312,15 @@ void arm_log_exception(int idx); #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) +/* + * SVE predicates are 1/8 the size of SVE vectors, and cannot use + * the same simd_desc() encoding due to restrictions on size. + * Use these instead. + */ +FIELD(PREDDESC, OPRSZ, 0, 6) +FIELD(PREDDESC, ESZ, 6, 2) +FIELD(PREDDESC, DATA, 8, 24) + /* * The SVE simd_data field, for memory ops, contains either * rd (5 bits) or a shift count (2 bits).
