File U_0005-dri2-Sync-i965_pci_ids.h-from-mesa-iris_pci_ids.h.patch of Package xorg-x11-server.28109
From 3ea46f9336693d713ab63f422fffce42f9060a2c Mon Sep 17 00:00:00 2001 From: "Mazlan, Hazwan Arif" <hazwan.arif.mazlan@intel.com> Date: Thu, 30 Jul 2020 10:12:27 +0800 Subject: [PATCH 5/5] dri2: Sync i965_pci_ids.h from mesa iris_pci_ids.h Copied TGL PCI ID from MESA iris_pci_ids.h This update brings in a significant number of new platform ID's Sync up until commit f02ae698 Signed-off-by: Mazlan, Hazwan Arif <hazwan.arif.mazlan@intel.com> --- hw/xfree86/dri2/pci_ids/i965_pci_ids.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h b/hw/xfree86/dri2/pci_ids/i965_pci_ids.h index 646df447b..c4072e2ee 100644 --- a/hw/xfree86/dri2/pci_ids/i965_pci_ids.h +++ b/hw/xfree86/dri2/pci_ids/i965_pci_ids.h @@ -239,3 +239,14 @@ CHIPSET(0x4500, ehl_4x8, "Intel(R) HD Graphics (Elkhart Lake 4x8)") CHIPSET(0x4571, ehl_4x8, "Intel(R) HD Graphics (Elkhart Lake 4x8)") CHIPSET(0x4551, ehl_4x4, "Intel(R) HD Graphics (Elkhart Lake 4x4)") CHIPSET(0x4541, ehl_2x4, "Intel(R) HD Graphics (Elkhart Lake 2x4)") +CHIPSET(0x9A40, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)") +CHIPSET(0x9A49, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)") +CHIPSET(0x9A59, tgl_1x6x16, "Intel(R) HD Graphics (Tigerlake 1x6x16 GT2)") +CHIPSET(0x9A60, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +CHIPSET(0x9A68, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +CHIPSET(0x9A70, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +CHIPSET(0x9A78, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT1)") +CHIPSET(0x9AC0, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)") +CHIPSET(0x9AC9, tg1_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)") +CHIPSET(0x9AD9, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1x2x16 GT2)") +CHIPSET(0x9AF8, tgl_1x2x16, "Intel(R) HD Graphics (Tigerlake 1X2X16 GT2)") -- 2.34.1
