File xsa456-0b.patch of Package xen.33138
# Commit 478e4787fa64b621061177a7843c452e9a19916d
# Date 2024-02-01 19:52:44 +0000
# Author Roger Pau Monné <roger.pau@citrix.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86/spec-ctrl: Expose RRSBA_CTRL to guests
The CPUID feature bit signals the presence of the RRSBA_DIS_{U,S} controls in
SPEC_CTRL MSR, first available in Intel AlderLake and Sapphire Rapids CPUs.
Xen already knows how to context switch MSR_SPEC_CTRL properly between guest
and hypervisor context.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -251,6 +251,8 @@ uint64_t msr_spec_ctrl_valid_bits(const
(psfd ? SPEC_CTRL_PSFD : 0) |
(cp->feat.ipred_ctrl
? (SPEC_CTRL_IPRED_DIS_U | SPEC_CTRL_IPRED_DIS_S) : 0) |
+ (cp->feat.rrsba_ctrl
+ ? (SPEC_CTRL_RRSBA_DIS_U | SPEC_CTRL_RRSBA_DIS_S) : 0) |
0);
}
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -43,6 +43,8 @@
#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2)
#define SPEC_CTRL_IPRED_DIS_U (_AC(1, ULL) << 3)
#define SPEC_CTRL_IPRED_DIS_S (_AC(1, ULL) << 4)
+#define SPEC_CTRL_RRSBA_DIS_U (_AC(1, ULL) << 5)
+#define SPEC_CTRL_RRSBA_DIS_S (_AC(1, ULL) << 6)
#define SPEC_CTRL_PSFD (_AC(1, ULL) << 7)
#define MSR_PRED_CMD 0x00000049
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -289,6 +289,7 @@ XEN_CPUFEATURE(SRSO_NO, 11*32
/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*A MSR_SPEC_CTRL.IPRED_DIS_* */
+XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*A MSR_SPEC_CTRL.RRSBA_DIS_* */
XEN_CPUFEATURE(DDP_CTRL, 13*32+ 3) /* MSR_SPEC_CTRL.DDP_DIS_U */
XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -307,7 +307,7 @@ def crunch_numbers(state):
# as dependent features simplifies Xen's logic, and prevents the guest
# from seeing implausible configurations.
IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS,
- IPRED_CTRL],
+ IPRED_CTRL, RRSBA_CTRL],
IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE],
# The ARCH_CAPS CPUID bit enumerates the availability of the whole register.