File 5bdc31d5-VMX-fix-vmx_handle_eoi.patch of Package xen.9798
References: bsc#1108940
# Commit 45cb9a4123b5550eb1f84846fe5482acae1c13a3
# Date 2018-11-02 12:15:33 +0100
# Author Jan Beulich <jbeulich@suse.com>
# Committer Jan Beulich <jbeulich@suse.com>
VMX: fix vmx_handle_eoi()
In commit 303066fdb1e ("VMX: fix interaction of APIC-V and Viridian
emulation") I screwed up: Instead of clearing SVI, other ISR bits
should be taken into account.
Introduce a new helper set_svi(), split out of vmx_process_isr(), and
use it also from vmx_handle_eoi().
Following the problems in vmx_intr_assist() (see the still present big
block of debugging code there) also warn (once) if EOI'd vector and
original SVI don't match.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Chao Gao <chao.gao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -427,7 +427,7 @@ void vlapic_EOI_set(struct vlapic *vlapi
vlapic_clear_vector(vector, &vlapic->regs->data[APIC_ISR]);
if ( hvm_funcs.handle_eoi )
- hvm_funcs.handle_eoi(vector);
+ hvm_funcs.handle_eoi(vector, vlapic_find_highest_isr(vlapic));
vlapic_handle_EOI(vlapic, vector);
}
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1981,17 +1981,14 @@ static int vmx_virtual_intr_delivery_ena
return cpu_has_vmx_virtual_intr_delivery;
}
-static void vmx_process_isr(int isr, struct vcpu *v)
+static u8 set_svi(int isr)
{
unsigned long status;
u8 old;
- unsigned int i;
- const struct vlapic *vlapic = vcpu_vlapic(v);
if ( isr < 0 )
isr = 0;
- vmx_vmcs_enter(v);
__vmread(GUEST_INTR_STATUS, &status);
old = status >> VMX_GUEST_INTR_STATUS_SVI_OFFSET;
if ( isr != old )
@@ -2001,6 +1998,18 @@ static void vmx_process_isr(int isr, str
__vmwrite(GUEST_INTR_STATUS, status);
}
+ return old;
+}
+
+static void vmx_process_isr(int isr, struct vcpu *v)
+{
+ unsigned int i;
+ const struct vlapic *vlapic = vcpu_vlapic(v);
+
+ vmx_vmcs_enter(v);
+
+ set_svi(isr);
+
/*
* Theoretically, only level triggered interrupts can have their
* corresponding bits set in the eoi exit bitmap. That is, the bits
@@ -2151,14 +2160,13 @@ static bool vmx_test_pir(const struct vc
return pi_test_pir(vec, &v->arch.hvm_vmx.pi_desc);
}
-static void vmx_handle_eoi(u8 vector)
+static void vmx_handle_eoi(uint8_t vector, int isr)
{
- unsigned long status;
+ uint8_t old_svi = set_svi(isr);
+ static bool warned;
- /* We need to clear the SVI field. */
- __vmread(GUEST_INTR_STATUS, &status);
- status &= VMX_GUEST_INTR_STATUS_SUBFIELD_BITMASK;
- __vmwrite(GUEST_INTR_STATUS, status);
+ if ( vector != old_svi && !test_and_set_bool(warned) )
+ printk(XENLOG_WARNING "EOI for %02x but SVI=%02x\n", vector, old_svi);
}
static void vmx_enable_msr_interception(struct domain *d, uint32_t msr)
--- a/xen/include/asm-x86/hvm/hvm.h
+++ b/xen/include/asm-x86/hvm/hvm.h
@@ -196,7 +196,7 @@ struct hvm_function_table {
void (*deliver_posted_intr)(struct vcpu *v, u8 vector);
void (*sync_pir_to_irr)(struct vcpu *v);
bool (*test_pir)(const struct vcpu *v, uint8_t vector);
- void (*handle_eoi)(u8 vector);
+ void (*handle_eoi)(uint8_t vector, int isr);
/*Walk nested p2m */
int (*nhvm_hap_walk_L1_p2m)(struct vcpu *v, paddr_t L2_gpa,