File 68ac5f69-x86-adjustments-to-intel_init_ppin.patch of Package xen

# Commit 49e6eb744eba01f5d4b4cfce49154c0802d4f5c6
# Date 2025-08-25 14:04:41 +0100
# Author Andrew Cooper <andrew.cooper3@citrix.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86/mce: Adjustments to intel_init_ppin()

There's no family check gating intel_init_ppin(), making it incorrect to
use on non Fam6 CPUs.

Emerald Rapids is the final CPU to have PPIN but lack the architectural
enumeration, so include it too.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -10,6 +10,7 @@
 #include <xen/cpu.h>
 #include <asm/processor.h>
 #include <public/sysctl.h>
+#include <asm/intel-family.h>
 #include <asm/system.h>
 #include <asm/msr.h>
 #include <asm/p2m.h>
@@ -859,7 +860,7 @@ static void intel_init_ppin(const struct
      * other purposes.  Despite the late addition of a CPUID bit (rendering
      * the MSR architectural), keep using the same detection logic there.
      */
-    switch ( c->x86_model )
+    switch ( c->x86 == 6 ? c->x86_model : 0 )
     {
         uint64_t val;
 
@@ -870,14 +871,15 @@ static void intel_init_ppin(const struct
             return;
         }
         fallthrough;
-    case 0x3e: /* IvyBridge X */
-    case 0x3f: /* Haswell X */
-    case 0x4f: /* Broadwell X */
-    case 0x55: /* Skylake X */
-    case 0x56: /* Broadwell Xeon D */
-    case 0x6a: /* Icelake X */
-    case 0x6c: /* Icelake D */
-    case 0x8f: /* Sapphire Rapids X */
+    case INTEL_FAM6_IVYBRIDGE_X:
+    case INTEL_FAM6_HASWELL_X:
+    case INTEL_FAM6_BROADWELL_X:
+    case INTEL_FAM6_BROADWELL_D:
+    case INTEL_FAM6_SKYLAKE_X:
+    case INTEL_FAM6_ICELAKE_X:
+    case INTEL_FAM6_ICELAKE_D:
+    case INTEL_FAM6_SAPPHIRERAPIDS_X:
+    case INTEL_FAM6_EMERALDRAPIDS_X:
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, val) )