File ibm304071-z10-5 of Package gcc43
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From: "Andreas Krebbel" <Andreas dot Krebbel at de dot ibm dot com>
Date: Wed, 28 May 2008 16:14:55 +0200
To: gcc-patches at gcc dot gnu dot org
Subject: [Committed] S/390: Add the -march=z10/-mtune=z10 options for the new System z10 Enterprise Class Mainframe
Message-ID: <20080528141455.GA17975@homer.boeblingen.de.ibm.com>
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Committed to mainline.
Bye,
-Andreas-
2008-05-28 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.c (z10_cost): New cost function for z10.
(s390_handle_arch_option, override_options): Support
-march=z10 switch.
(s390_issue_rate): Adjust issue rate for z10.
* config/s390/s390.h (processor_type): Add PROCESSOR_2097_Z10.
(processor_flags): Add PF_Z10.
(TARGET_CPU_Z10, TARGET_Z10): New macro definitions.
* config/s390/s390.md (cpu, cpu_facility attributes): Add z10.
* gcc/config.gcc: Add z10.
Index: gcc/config/s390/s390.c
===================================================================
--- gcc/config/s390/s390.c.orig 2008-02-19 10:55:43.000000000 +0100
+++ gcc/config/s390/s390.c 2009-11-20 13:51:31.000000000 +0100
@@ -188,6 +188,38 @@ struct processor_costs z9_109_cost =
COSTS_N_INSNS (24), /* DSGR */
};
+static const
+struct processor_costs z10_cost =
+{
+ COSTS_N_INSNS (4), /* M */
+ COSTS_N_INSNS (2), /* MGHI */
+ COSTS_N_INSNS (2), /* MH */
+ COSTS_N_INSNS (2), /* MHI */
+ COSTS_N_INSNS (4), /* ML */
+ COSTS_N_INSNS (4), /* MR */
+ COSTS_N_INSNS (5), /* MS */
+ COSTS_N_INSNS (6), /* MSG */
+ COSTS_N_INSNS (4), /* MSGF */
+ COSTS_N_INSNS (4), /* MSGFR */
+ COSTS_N_INSNS (4), /* MSGR */
+ COSTS_N_INSNS (4), /* MSR */
+ COSTS_N_INSNS (1), /* multiplication in DFmode */
+ COSTS_N_INSNS (28), /* MXBR */
+ COSTS_N_INSNS (130), /* SQXBR */
+ COSTS_N_INSNS (66), /* SQDBR */
+ COSTS_N_INSNS (38), /* SQEBR */
+ COSTS_N_INSNS (1), /* MADBR */
+ COSTS_N_INSNS (1), /* MAEBR */
+ COSTS_N_INSNS (60), /* DXBR */
+ COSTS_N_INSNS (40), /* DDBR */
+ COSTS_N_INSNS (26), /* DEBR */
+ COSTS_N_INSNS (30), /* DLGR */
+ COSTS_N_INSNS (23), /* DLR */
+ COSTS_N_INSNS (23), /* DR */
+ COSTS_N_INSNS (24), /* DSGFR */
+ COSTS_N_INSNS (24), /* DSGR */
+};
+
extern int reload_completed;
/* Save information from a "cmpxx" operation until the branch or scc is
@@ -1365,6 +1397,8 @@ s390_handle_arch_option (const char *arg
| PF_LONG_DISPLACEMENT | PF_EXTIMM},
{"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
+ {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
+ | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
};
size_t i;
@@ -1472,13 +1506,21 @@ override_options (void)
}
/* Set processor cost function. */
- if (s390_tune == PROCESSOR_2094_Z9_109)
- s390_cost = &z9_109_cost;
- else if (s390_tune == PROCESSOR_2084_Z990)
- s390_cost = &z990_cost;
- else
- s390_cost = &z900_cost;
-
+ switch (s390_tune)
+ {
+ case PROCESSOR_2084_Z990:
+ s390_cost = &z990_cost;
+ break;
+ case PROCESSOR_2094_Z9_109:
+ s390_cost = &z9_109_cost;
+ break;
+ case PROCESSOR_2097_Z10:
+ s390_cost = &z10_cost;
+ break;
+ default:
+ s390_cost = &z900_cost;
+ }
+
if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
error ("-mbackchain -mpacked-stack -mhard-float are not supported "
"in combination");
@@ -4930,10 +4972,16 @@ s390_adjust_priority (rtx insn ATTRIBUTE
static int
s390_issue_rate (void)
{
- if (s390_tune == PROCESSOR_2084_Z990
- || s390_tune == PROCESSOR_2094_Z9_109)
- return 3;
- return 1;
+ switch (s390_tune)
+ {
+ case PROCESSOR_2084_Z990:
+ case PROCESSOR_2094_Z9_109:
+ return 3;
+ case PROCESSOR_2097_Z10:
+ return 2;
+ default:
+ return 1;
+ }
}
static int
Index: gcc/config/s390/s390.h
===================================================================
--- gcc/config/s390/s390.h.orig 2008-11-20 11:39:20.000000000 +0100
+++ gcc/config/s390/s390.h 2009-11-20 13:51:31.000000000 +0100
@@ -40,6 +40,7 @@ enum processor_type
PROCESSOR_2064_Z900,
PROCESSOR_2084_Z990,
PROCESSOR_2094_Z9_109,
+ PROCESSOR_2097_Z10,
PROCESSOR_max
};
@@ -51,7 +52,8 @@ enum processor_flags
PF_ZARCH = 2,
PF_LONG_DISPLACEMENT = 4,
PF_EXTIMM = 8,
- PF_DFP = 16
+ PF_DFP = 16,
+ PF_Z10 = 32
};
extern enum processor_type s390_tune;
@@ -70,6 +72,8 @@ extern enum processor_flags s390_arch_fl
(s390_arch_flags & PF_EXTIMM)
#define TARGET_CPU_DFP \
(s390_arch_flags & PF_DFP)
+#define TARGET_CPU_Z10 \
+ (s390_arch_flags & PF_Z10)
#define TARGET_LONG_DISPLACEMENT \
(TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
@@ -77,6 +81,8 @@ extern enum processor_flags s390_arch_fl
(TARGET_ZARCH && TARGET_CPU_EXTIMM)
#define TARGET_DFP \
(TARGET_ZARCH && TARGET_CPU_DFP)
+#define TARGET_Z10 \
+ (TARGET_ZARCH && TARGET_CPU_Z10)
/* Run-time target specification. */
Index: gcc/config/s390/s390.md
===================================================================
--- gcc/config/s390/s390.md.orig 2009-11-20 13:51:31.000000000 +0100
+++ gcc/config/s390/s390.md 2009-11-20 13:51:31.000000000 +0100
@@ -228,10 +228,10 @@
;; distinguish between g5 and g6, but there are differences between the two
;; CPUs could in theory be modeled.
-(define_attr "cpu" "g5,g6,z900,z990,z9_109"
+(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
(const (symbol_ref "s390_tune")))
-(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp"
+(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
(const_string "standard"))
(define_attr "enabled" ""
@@ -256,6 +256,10 @@
(and (eq_attr "cpu_facility" "dfp")
(ne (symbol_ref "TARGET_DFP") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z10")
+ (ne (symbol_ref "TARGET_Z10") (const_int 0)))
(const_int 1)]
(const_int 0)))
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc.orig 2009-11-20 13:51:21.000000000 +0100
+++ gcc/config.gcc 2009-11-20 13:51:31.000000000 +0100
@@ -3155,7 +3155,7 @@ case "${target}" in
for which in arch tune; do
eval "val=\$with_$which"
case ${val} in
- "" | g5 | g6 | z900 | z990 | z9-109 | z9-ec)
+ "" | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10)
# OK
;;
*)
