File verilator.spec of Package verilator

#
# spec file for package verilator
#
# Copyright (c) 2020 SUSE LLC
#
# All modifications and additions to the file contributed by third parties
# remain the property of their copyright owners, unless otherwise agreed
# upon. The license for this file, and modifications and additions to the
# file, is the same license as for the pristine package itself (unless the
# license for the pristine package is not an Open Source License, in which
# case the license is the MIT License). An "Open Source License" is a
# license that conforms to the Open Source Definition (Version 1.9)
# published by the Open Source Initiative.

# Please submit bugfixes or comments via https://bugs.opensuse.org/
#


Name:           verilator
Version:        4.106.1606957763.b350b6a0
Release:        0
Summary:        Compiling Verilog HDL simulator
License:        Artistic-2.0 OR LGPL-3.0-only
Group:          Productivity/Scientific/Electronics
URL:            https://www.veripool.org/projects/verilator/wiki/Intro
Source0:        %{name}-%{version}.tar.xz
Patch0:         fix-shebang.patch
BuildRequires:  autoconf
BuildRequires:  bison
BuildRequires:  fdupes
BuildRequires:  flex
BuildRequires:  gcc-c++
BuildRequires:  gdb
BuildRequires:  perl
BuildRequires:  pkg-config
BuildRoot:      %{_tmppath}/%{name}-%{version}-build

%description
Verilator compiles synthesizable Verilog (not test-bench code), plus
some PSL, SystemVerilog and Synthesis assertions into an optimized
model which is in turn wrapped inside a C++/SystemC module for faster
execution.

%package devel
Summary:        Verilator library header files
Group:          Development/Languages/C and C++
Requires:       %{name} = %{version}
BuildArch:      noarch

%description devel
Development files for Verilator, a compiling Verilog HDL simulator.
It includes header files and a pkgconfig file.

%package        examples
Summary:        Examples for verilator
Group:          Documentation/Other
Requires:       %{name} = %{version}
BuildArch:      noarch

%description    examples
Verilator is a compiling Verilog HDL simulator.

This package contains examples of using verilator.

%prep
%setup -q
%patch0 -p1


%build
autoconf
%configure
make %{?_smp_mflags}

%install
%make_install

# install examples
mkdir -p %{buildroot}%{_docdir}/%{name}
mv %{buildroot}%{_datadir}/verilator/examples %{buildroot}%{_docdir}/%{name}/examples
%fdupes %{buildroot}%{_docdir}/%{name}/examples

# fix install of devel files
mkdir -p %{buildroot}%{_includedir}/
mv %{buildroot}%{_datadir}/verilator/include/ %{buildroot}%{_includedir}/verilator

%check
make test

%files
%license Artistic LICENSE
%doc Changes README.adoc
%{_bindir}/verilator
%{_bindir}/verilator_bin
%{_bindir}/verilator_bin_dbg
%{_bindir}/verilator_coverage
%{_bindir}/verilator_coverage_bin_dbg
%{_bindir}/verilator_gantt
%{_bindir}/verilator_profcfunc
%{_datadir}/verilator
%{_mandir}/man1/verilator.1.gz
%{_mandir}/man1/verilator_coverage.1.gz
%{_mandir}/man1/verilator_gantt.1.gz
%{_mandir}/man1/verilator_profcfunc.1.gz

%files devel
%{_datadir}/pkgconfig/verilator.pc
%{_includedir}/verilator

%files examples
%doc %{_docdir}/%{name}/examples/

%changelog