File gcc41-power6-2.patch of Package gcc

2006-08-08  Pete Steinmetz <steinmtz@us.ibm.com>

	* config/rs6000/rs6000.h (SECONDARY_MEMORY_NEEDED): Added mode!=DFmode
	and mode!=DImode conditions.
	* config/rs6000/rs6000.c (rs6000_register_move_cost): Revert
	rs6000_memory_move_cost if mf{t,f}gpr are available change.
	* config/rs6000/rs6000.md (fix_truncdfsi2): Use gpc_reg_operand
	constraint.

--- gcc/config/rs6000/rs6000.h.orig	2006-08-08 12:48:57.972143448 -0500
+++ gcc/config/rs6000/rs6000.h	2006-08-08 13:05:00.667303659 -0500
@@ -1209,9 +1209,11 @@ enum reg_class
 
 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE)			\
  ((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS			\
-                            && (!TARGET_MFPGPR || !TARGET_POWERPC64))	\
+                            && (!TARGET_MFPGPR || !TARGET_POWERPC64	\
+				|| ((MODE != DFmode) && (MODE != DImode)))) \
 			   || ((CLASS2) == FLOAT_REGS			\
-                               && (!TARGET_MFPGPR || !TARGET_POWERPC64))\
+                               && (!TARGET_MFPGPR || !TARGET_POWERPC64	\
+				|| ((MODE != DFmode) && (MODE != DImode)))) \
 			   || (CLASS1) == ALTIVEC_REGS			\
 			   || (CLASS2) == ALTIVEC_REGS))
 
--- gcc/config/rs6000/rs6000.c.orig	2006-08-08 12:48:54.257184227 -0500
+++ gcc/config/rs6000/rs6000.c	2006-08-08 12:49:18.841128070 -0500
@@ -19403,8 +19403,7 @@ rs6000_register_move_cost (enum machine_
       if (! reg_classes_intersect_p (to, GENERAL_REGS))
 	from = to;
 
-      if ((from == FLOAT_REGS && (!TARGET_MFPGPR || !TARGET_POWERPC64))
-          || from == ALTIVEC_REGS)
+      if (from == FLOAT_REGS || from == ALTIVEC_REGS)
 	return (rs6000_memory_move_cost (mode, from, 0)
 		+ rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
 
--- gcc/config/rs6000/rs6000.md.orig	2006-08-08 12:48:50.255134210 -0500
+++ gcc/config/rs6000/rs6000.md	2006-08-08 12:49:18.851126531 -0500
@@ -5323,7 +5323,8 @@
      DONE;
     }
   operands[2] = gen_reg_rtx (DImode);
-  if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
+  if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
+      && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
     {
       operands[3] = gen_reg_rtx (DImode);
       emit_insn (gen_fix_truncdfsi2_internal_mfpgpr (operands[0], operands[1],