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gcc41-power6x.patch
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File gcc41-power6x.patch of Package gcc
2006-09-27 Peter Bergner <bergner@vnet.ibm.com> * config.gcc: Add cpu_type power6x. * config/rs6000/aix52.h (ASM_CPU_SPEC): Add power6x. * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define _ARCH_PWR6X, not _ARCH_PWR6, if features enabled. * config/rs6000/rs6000.c (processor_target_table): Add power6x. Remove MASK_MFPGPR from power6. (rs6000_issue_rate): Add CPU_POWER6X. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add power6x. * config/rs6000/rs6000.md (define_attr "cpu"): Add power6x. * config/rs6000/rs6000.opt (mmfpgpr): Fixup comment. * doc/invoke.texi: Add cpu_type power6x (RS/6000 and PowerPC Options): Modify -mmfpgpr to be a power6x option. --- gcc/config.gcc.jj 2006-09-27 10:39:25.000000000 -0500 +++ gcc/config.gcc 2006-09-27 10:36:32.000000000 -0500 @@ -296,7 +296,7 @@ powerpc*-*-*) extra_headers="ppc-asm.h altivec.h spe.h" need_64bit_hwint=yes case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456]|xrs64a) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456]|xpower6x|xrs64a) cpu_is_64bit=yes ;; esac @@ -2719,7 +2719,7 @@ case "${target}" in eval "with_$which=405" ;; "" | common \ - | power | power[23456] | powerpc | powerpc64 \ + | power | power[23456] | power6x | powerpc | powerpc64 \ | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \ | 601 | 602 | 603 | 603e | ec603e | 604 \ --- gcc/config/rs6000/aix52.h.jj 2006-09-27 10:39:41.462677579 -0500 +++ gcc/config/rs6000/aix52.h 2006-09-27 10:36:40.000000000 -0500 @@ -69,6 +69,7 @@ do { \ %{mcpu=power5: -m620} \ %{mcpu=power5+: -m620} \ %{mcpu=power6: -m620} \ +%{mcpu=power6x: -m620} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rs64a: -mppc} \ %{mcpu=603: -m603} \ --- gcc/config/rs6000/rs6000-c.c.jj 2006-09-27 10:39:51.096655963 -0500 +++ gcc/config/rs6000/rs6000-c.c 2006-09-27 10:36:49.000000000 -0500 @@ -107,7 +107,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfi if (TARGET_FPRND) builtin_define ("_ARCH_PWR5X"); if (TARGET_MFPGPR) - builtin_define ("_ARCH_PWR6"); + builtin_define ("_ARCH_PWR6X"); if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC) builtin_define ("_ARCH_COM"); if (TARGET_ALTIVEC) --- gcc/config/rs6000/rs6000.c.jj 2006-09-27 10:39:55.649757533 -0500 +++ gcc/config/rs6000/rs6000.c 2006-09-27 13:02:34.643862118 -0500 @@ -1197,6 +1197,9 @@ rs6000_override_options (const char *def | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND}, {"power6", PROCESSOR_POWER6, POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB + | MASK_FPRND}, + {"power6x", PROCESSOR_POWER6, + POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MFPGPR}, {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, {"powerpc64", PROCESSOR_POWERPC64, @@ -16950,6 +16953,7 @@ rs6000_issue_rate (void) case CPU_POWER4: case CPU_POWER5: case CPU_POWER6: + case CPU_POWER6X: return 5; default: return 1; --- gcc/config/rs6000/rs6000.h.jj 2006-09-27 10:39:58.361737453 -0500 +++ gcc/config/rs6000/rs6000.h 2006-09-27 10:37:03.000000000 -0500 @@ -75,6 +75,7 @@ %{mcpu=power5: -mpower4} \ %{mcpu=power5+: -mpower4} \ %{mcpu=power6: -mpower4 -maltivec} \ +%{mcpu=power6x: -mpower4 -maltivec} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rios: -mpwr} \ %{mcpu=rios1: -mpwr} \ --- gcc/config/rs6000/rs6000.md.jj 2006-09-27 10:40:01.804739533 -0500 +++ gcc/config/rs6000/rs6000.md 2006-09-27 10:37:09.000000000 -0500 @@ -103,7 +103,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6" +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,power6x" (const (symbol_ref "rs6000_cpu_attr"))) (automata_option "ndfa") --- gcc/config/rs6000/rs6000.opt.jj 2006-09-27 10:40:05.343725685 -0500 +++ gcc/config/rs6000/rs6000.opt 2006-09-27 10:37:15.000000000 -0500 @@ -66,7 +66,7 @@ Use PowerPC V2.02 floating point roundin mmfpgpr Target Report Mask(MFPGPR) -Use PowerPC V2.05 move floating point to/from GPR instructions +Use extended PowerPC V2.05 move floating point to/from GPR instructions maltivec Target Report Mask(ALTIVEC) --- gcc/doc/invoke.texi.jj 2006-09-27 10:40:14.000000000 -0500 +++ gcc/doc/invoke.texi 2006-09-27 10:37:23.000000000 -0500 @@ -10936,8 +10936,8 @@ The @option{-mfprnd} option allows GCC t integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The @option{-mfpgpr} option allows GCC to generate the FP move to/from -general purpose register instructions implemented on the POWER6 -processor and other processors that support the PowerPC V2.05 +general purpose register instructions implemented on the POWER6X +processor and other processors that support the extended PowerPC V2.05 architecture. The @option{-mpowerpc64} option allows GCC to generate the additional @@ -10981,7 +10981,7 @@ Supported values for @var{cpu_type} are @samp{860}, @samp{970}, @samp{8540}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, -@samp{common}, @samp{powerpc}, @samp{powerpc64}, +@samp{power6x}, @samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}. @option{-mcpu=common} selects a completely generic processor. Code
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