File nvidia-vaapi-driver-0.0.12.obscpio of Package libva-nvidia-driver
07070100000000000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000002300000000nvidia-vaapi-driver-0.0.12/.github07070100000001000081A4000000000000000000000001663926A700000076000000000000000000000000000000000000003200000000nvidia-vaapi-driver-0.0.12/.github/dependabot.ymlversion: 2
updates:
- package-ecosystem: "github-actions"
directory: "/"
schedule:
interval: "weekly"
07070100000002000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000002D00000000nvidia-vaapi-driver-0.0.12/.github/workflows07070100000003000081ED000000000000000000000001663926A7000002F1000000000000000000000000000000000000003E00000000nvidia-vaapi-driver-0.0.12/.github/workflows/install-clang.sh#!/bin/bash
set -euo pipefail
if (( $# != 1 )); then
echo Script requires one argument - the clang version to be installed
exit 1
fi
if ! which $CC >/dev/null 2>&1; then
case $DISTRO in
"ubuntu-22.04") distro_name=jammy;;
"ubuntu-20.04") distro_name=focal;;
*)
echo "Unknown distribution $DISTRO"
exit 1
esac
case $1 in
"14" | "15") llvm_version=$1;;
*)
echo "Unknown llvm version $1"
exit 1
esac
sources="deb [trusted=yes] http://apt.llvm.org/$distro_name/ llvm-toolchain-$distro_name-$llvm_version main"
echo "clang-$llvm_version missed in the image, installing from llvm"
echo "$sources" | sudo tee -a /etc/apt/sources.list
sudo apt-get update
sudo apt-get install -y --no-install-recommends clang-$llvm_version
fi
07070100000004000081A4000000000000000000000001663926A70000034F000000000000000000000000000000000000003800000000nvidia-vaapi-driver-0.0.12/.github/workflows/ubuntu.ymlname: ubuntu
on: [push, pull_request]
jobs:
ci:
strategy:
matrix:
compiler: [clang-15, gcc]
os: [ubuntu-22.04]
runs-on: ${{ matrix.os }}
env:
CC: ${{ matrix.compiler }}
DISTRO: ${{ matrix.os }}
steps:
- name: 'Checkout'
uses: actions/checkout@v4
- name: 'Install toolchain'
if: ${{ (matrix.compiler == 'clang-15') }}
run: .github/workflows/install-clang.sh 15
- name: 'Install prerequisites'
run: |
sudo apt-get update
sudo apt-get install -y \
libdrm-dev \
libva-dev \
libegl-dev \
meson
- name: 'Configure'
run: meson setup ./builddir --prefix=/usr -D werror=true
- name: 'Build'
run: meson compile -C ./builddir
- name: 'Install'
run: sudo meson install -C ./builddir
07070100000005000081A4000000000000000000000001663926A7000000D6000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/.gitignore*.o
samples/*.mp4
subprojects/*/
videos
va-api-nvidia.cflags
va-api-nvidia.config
va-api-nvidia.creator
va-api-nvidia.creator.user
va-api-nvidia.cxxflags
va-api-nvidia.files
va-api-nvidia.includes
meson.build.user
07070100000006000081A4000000000000000000000001663926A7000004A3000000000000000000000000000000000000002300000000nvidia-vaapi-driver-0.0.12/COPYINGPermission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
---
The above is the version of the MIT "Expat" License used by X.org:
http://cgit.freedesktop.org/xorg/xserver/tree/COPYING
07070100000007000081A4000000000000000000000001663926A7000025AB000000000000000000000000000000000000002500000000nvidia-vaapi-driver-0.0.12/README.md# nvidia-vaapi-driver
This is an VA-API implementation that uses NVDEC as a backend. This implementation is specifically designed to be used by Firefox for accelerated decode of web content, and may not operate correctly in other applications.
# Table of contents
- [nvidia-vaapi-driver](#nvidia-vaapi-driver)
- [Table of contents](#table-of-contents)
- [Codec Support](#codec-support)
- [Installation](#installation)
- [Packaging status](#packaging-status)
- [Building](#building)
- [Removal](#removal)
- [Configuration](#configuration)
- [Upstream regressions](#upstream-regressions)
- [Kernel parameters](#kernel-parameters)
- [Environment Variables](#environment-variables)
- [Firefox](#firefox)
- [Chrome](#chrome)
- [MPV](#mpv)
- [Direct Backend](#direct-backend)
- [Testing](#testing)
# Codec Support
Hardware decoding only, encoding is [not supported](/../../issues/116).
| Codec | Supported | Comments |
|---|---|---|
|AV1|:heavy_check_mark:|Firefox 98+ is required.|
|H.264|:heavy_check_mark:||
|HEVC|:heavy_check_mark:||
|VP8|:heavy_check_mark:||
|VP9|:heavy_check_mark:|Requires being compiled with `gstreamer-codecparsers-1.0`|
|MPEG-2|:heavy_check_mark:||
|VC-1|:heavy_check_mark:||
|MPEG-4|:x:|VA-API does not supply enough of the original bitstream to allow NVDEC to decode it.|
|JPEG|:x:|This is unlikely to ever work, the two APIs are too different.|
YUV444 is supported but requires:
* \>= Turing (20XX/16XX)
* HEVC
* Direct backend
To view which codecs your card is capable of decoding you can use the `vainfo` command with this driver installed, or visit the NVIDIA website [here](https://developer.nvidia.com/video-encode-and-decode-gpu-support-matrix-new#geforce).
# Installation
To install and use `nvidia-vaapi-driver`, follow the steps in installation and configuration. It is recommended to follow testing as well to verify hardware acceleration is working as intended.
**Requirements**
* NVIDIA driver series 470 or 500+
## Packaging status
<p align="top"><a href="https://repology.org/project/nvidia-vaapi-driver/versions"><img src="https://repology.org/badge/vertical-allrepos/nvidia-vaapi-driver.svg" alt="repology"><a href="https://repology.org/project/libva-nvidia-driver/versions"><img src="https://repology.org/badge/vertical-allrepos/libva-nvidia-driver.svg" alt="repology" align="top" width="%"></p>
[pkgs.org/nvidia-vaapi-driver](https://pkgs.org/search/?q=nvidia-vaapi-driver) [pkgs.org/libva-nvidia-driver](https://pkgs.org/search/?q=libva-nvidia-driver)
openSUSE: [1](https://software.opensuse.org/package/nvidia-vaapi-driver), [2](https://software.opensuse.org/package/libva-nvidia-driver).
Feel free to add your distributions package in an issue/PR, if it isn't on these websites.
## Building
You'll need `meson`, the `gstreamer-plugins-bad` library, and [`nv-codec-headers`](https://git.videolan.org/?p=ffmpeg/nv-codec-headers.git) installed.
| Package manager | Packages | Optional packages for additional codec support |
|-----------------|-------------------------------------------------|------------------------------------------------|
| pacman | meson gst-plugins-bad ffnvcodec-headers | |
| apt | meson gstreamer1.0-plugins-bad libffmpeg-nvenc-dev libva-dev libegl-dev | libgstreamer-plugins-bad1.0-dev |
| yum/dnf | meson libva-devel gstreamer1-plugins-bad-freeworld nv-codec-headers | gstreamer1-plugins-bad-free-devel |
Then run the following commands:
```sh
meson setup build
meson install -C build
```
## Removal
By default the driver installs itself as `/usr/lib64/dri/nvidia_drv_video.so` (this might be `/usr/lib/x86_64-linux-gnu/dri/nvidia_drv_video.so` on some distros). To uninstall the driver, simply remove this file. In addition, this file is usually symlinked to `/usr/lib64/dri/vdpau_drv_video.so` (or `/usr/lib/x86_64-linux-gnu/dri/vdpau_drv_video.so`) if the VDPAU to VA-API driver is installed, so this symlink will need to be restored for that driver to work normally again.
# Configuration
## Upstream regressions
The EGL backend is broken on driver versions 525 or later due to a regression. Users running these drivers should use the [direct backend](#direct-backend) instead.
For more information read the [upstream bug report](https://forums.developer.nvidia.com/t/cueglstreamproducerconnect-returns-error-801-on-525-53-driver/233610) or [issue #126](/../../issues/126).
## Kernel parameters
This library requires that the `nvidia_drm` kernel module is [configured with the parameter](https://wiki.archlinux.org/title/Kernel_parameters) `nvidia-drm.modeset=1`
## Environment Variables
Environment variables used to control the behavior of this library.
| Variable | Purpose |
|---|---|
| `NVD_LOG` | Used to control logging. `1` to log to stdout, anything else to append to the given file. |
| `NVD_MAX_INSTANCES` | Controls the maximum concurrent instances of the driver will be allowed per-process. This option is only really useful for older GPUs with not much VRAM, especially with Firefox on video heavy websites. |
| `NVD_BACKEND` | Controls which backend this library uses. Either `egl`, or `direct` (default). See [direct backend](#direct-backend) for more details. |
## Firefox
To use the driver with firefox you will need at least Firefox 96, `ffmpeg` compiled with vaapi support (`ffmpeg -hwaccels` output should include vaapi), and the following config options need to be set in the `about:config` page:
| Option | Value | Reason |
|---|---|---|
| media.ffmpeg.vaapi.enabled | true | Required, enables the use of VA-API. |
| media.rdd-ffmpeg.enabled | true | Required, default on FF97. Forces ffmpeg usage into the RDD process, rather than the content process. |
| media.av1.enabled | false | Optional, disables AV1. If your GPU doesn't support AV1, this will prevent sites using it and falling back to software decoding. |
| gfx.x11-egl.force-enabled | true | Required, this driver requires that Firefox use the EGL backend. It may be enabled by default. It is recommended to test it with the `MOZ_X11_EGL=1` environment variable before enabling it in the Firefox configuration. |
| widget.dmabuf.force-enabled | true | Required on NVIDIA 470 series drivers, and currently **REQUIRED** on 500+ drivers due to a [Firefox change](https://bugzilla.mozilla.org/show_bug.cgi?id=1788573). Note that Firefox isn't coded to allow DMA-BUF support without GBM support, so it may not function completely correctly when it's forced on. |
In addition the following environment variables need to be set. For permanent configuration `/etc/environment` may suffice.
| Variable | Value | Reason |
|---|---|---|
| MOZ_DISABLE_RDD_SANDBOX | 1 | Disables the sandbox for the RDD process that the decoder runs in. |
| LIBVA_DRIVER_NAME | nvidia | Required for libva 2.20+, forces libva to load this driver. |
| __EGL_VENDOR_LIBRARY_FILENAMES | /usr/share/glvnd/egl_vendor.d/10_nvidia.json | Required for the 470 driver series only. It overrides the list of drivers the glvnd library can use to prevent Firefox from using the MESA driver by mistake. |
When libva is used it will log out some information, which can be excessive when Firefox initalises it multiple times per page. This logging can be suppressed by adding the following line to the `/etc/libva.conf` file:
```
LIBVA_MESSAGING_LEVEL=1
```
If you're using the Snap version of Firefox, it will be unable to access the host version of the driver that is installed.
## Chrome
Chrome is currently unsupported, and will not function.
## MPV
Currently this only works with a build of MPV from git master.
There's no real reason to run it with mpv except for testing, as mpv already supports using nvdec directly. The `test.sh` script will run mpv with the file provided and various environment variables set to use the newly built driver
## Direct Backend
The direct backend is a experimental backend that accesses the NVIDIA kernel driver directly, rather than using EGL to share the buffers. This allows us
a greater degree of control over buffer allocation and freeing.
The direct backend has been tested on a variety of hardware from the Kepler to Lovelace generations, and seems to be working fine. If you find any compatibility issues, please leave a comment [here](/../../issues/126).
Given this backend accesses the NVIDIA driver directly, via NVIDIA's unstable API, this module is likely to break often with new versions of the kernel driver. If you encounter issues using this backend raise an issue and including logs generated by `NVD_LOG=1`.
This backend uses headers files from the NVIDIA [open-gpu-kernel-modules](https://github.com/NVIDIA/open-gpu-kernel-modules)
project. The `extract_headers.sh` script, along with the `headers.in` file list which files we need, and will copy them from a checked out version of the NVIDIA project to the `nvidia-include` directory. This is done to prevent everyone needing to checkout that project.
# Testing
To verify that the driver is being used to decode video, you can use nvidia-settings or nvidia-smi.
- nvidia-settings
By selecting the relevant GPU on the left of the nvidia-settings window, it will show `Video Engine Utilization` on the right. While playing a video this value should be non-zero.
- nvidia-smi
Running `nvidia-smi` while decoding a video should show a Firefox process with `C` in the `Type` column. In addition `nvidia-smi pmon` will show the usage of the decode engine per-process, and `nvidia-smi dmon` will show the usage per-GPU.
07070100000008000081ED000000000000000000000001663926A700000603000000000000000000000000000000000000002E00000000nvidia-vaapi-driver-0.0.12/extract_headers.sh#!/bin/bash
if [ "x$1" = "x" ]; then
echo "Usage: $(basename $0) <path of NVIDIA open-gpu-kernel-modules project>"
exit 1
fi
OUTPUT_DIR=nvidia-include
DIR=$1
NEWLINE=$'\n'
DIRS=""
INC_DIRS=""
INC_FILES="#ifndef NVIDIA_H_${NEWLINE}#define NVIDIA_H_${NEWLINE}"
while IFS= read -r line; do
#echo got line: $line
if [[ $line =~ ^d\ .+ ]]; then
DIRS="$DIRS$DIR/${line//d /}${NEWLINE}"
INC_DIRS="$INC_DIRS -I$DIR/${line//d /}"
elif [[ $line =~ ^f\ .+ ]]; then
INC_FILES="${INC_FILES}#include <${line//f /}>${NEWLINE}"
elif [[ $line =~ ^#.+ ]]; then
INC_FILES="${INC_FILES}${line}${NEWLINE}"
fi
done < headers.in
INC_FILES="${INC_FILES}#endif${NEWLINE}"
#echo got dirs: "$DIRS"
#echo got inc dirs: $INC_DIRS
#echo got inc files: "$INC_FILES"
mkdir -p ${OUTPUT_DIR}
echo "${INC_FILES}" > ${OUTPUT_DIR}/nvidia.h
INCLUDED_FILES=$(cpp $INC_DIRS -H ${OUTPUT_DIR}/nvidia.h 2>&1 1>/dev/null | grep -E '^\.' | grep -Eo "$DIR.*")
for f in $INCLUDED_FILES; do
for d in $DIRS; do
if [[ "$f" == "$d"* ]]; then
dest_file=${OUTPUT_DIR}/${f//$d/}
mkdir -p $(dirname ${dest_file})
echo Copying ${dest_file}
cp $f ${dest_file}
fi
done
done
#fixup nvidia-drm-ioctl.h as it includes a kernel header, and we'd like it to be able to choose
mv ${OUTPUT_DIR}/nvidia-drm-ioctl.h ${OUTPUT_DIR}/nvidia-drm-ioctl.h.bak
sed 's$#include <drm/drm.h>$#include <drm.h>$' < ${OUTPUT_DIR}/nvidia-drm-ioctl.h.bak > ${OUTPUT_DIR}/nvidia-drm-ioctl.h
07070100000009000081A4000000000000000000000001663926A700000209000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/headers.ind src/common/sdk/nvidia/inc/
d src/nvidia/arch/nvalloc/unix/include/
d kernel-open/nvidia-drm/
d kernel-open/common/inc/
d src/nvidia-modeset/kapi/interface/
d src/nvidia-modeset/interface/
f class/cl0040.h
f class/cl0080.h
f class/cl2080.h
f nvos.h
f nv_escape.h
f nv-ioctl.h
f nvidia-drm-ioctl.h
f ctrl/ctrl0000/ctrl0000gpu.h
f ctrl/ctrl0000/ctrl0000unix.h
f ctrl/ctrl0000/ctrl0000system.h
//f ctrl/ctrl0080/ctrl0080dma.h
//f ctrl/ctrl2080/ctrl2080mc.h
#define NVKMS_API_H
f nvkms-api-types.h
f nvkms-kapi-private.h
0707010000000A000081A4000000000000000000000001663926A70000090A000000000000000000000000000000000000002700000000nvidia-vaapi-driver-0.0.12/meson.buildproject(
'nvidia-vaapi-driver',
'c',
version: '0.1',
default_options: [
'prefix=/usr',
'c_std=c11',
'warning_level=2',
],
license: 'MIT',
meson_version: '>= 0.58.0',
)
cc = meson.get_compiler('c')
deps = [
cc.find_library('m'),
cc.find_library('dl', required : false),
dependency('egl'),
dependency('ffnvcodec', version: '>= 11.1.5.1'),
dependency('libdrm', version: '>=2.4.60').partial_dependency(compile_args: true),
dependency('threads'),
]
libva_deps = dependency('libva', version: '>= 1.8.0').partial_dependency(compile_args: true)
deps += [libva_deps]
gst_codecs_deps = dependency('gstreamer-codecparsers-1.0', required: false)
if cc.get_argument_syntax() == 'gcc'
add_project_arguments(
cc.get_supported_arguments([
'-Wno-missing-field-initializers',
'-Wno-unused-parameter',
'-Werror=format',
'-Werror=format-security',
'-Werror=incompatible-pointer-types',
'-Werror=init-self',
'-Werror=int-conversion',
'-Werror=missing-declarations',
'-Werror=missing-prototypes',
'-Werror=pointer-arith',
'-Werror=undef',
'-Werror=vla',
'-Wsuggest-attribute=format',
'-Wwrite-strings',
]),
language: ['c'],
)
endif
sources = [
'src/av1.c',
'src/backend-common.c',
'src/export-buf.c',
'src/direct/direct-export-buf.c',
'src/direct/nv-driver.c',
'src/h264.c',
'src/hevc.c',
'src/jpeg.c',
'src/mpeg2.c',
'src/mpeg4.c',
'src/vabackend.c',
'src/vc1.c',
'src/vp8.c',
'src/list.c',
]
if gst_codecs_deps.found()
sources += ['src/vp9.c']
deps += [gst_codecs_deps]
endif
nvidia_incdir = include_directories('nvidia-include')
nvidia_install_dir = libva_deps.get_variable(pkgconfig: 'driverdir')
shared_library(
'nvidia_drv_video',
name_prefix: '',
sources: sources,
dependencies: deps,
include_directories: nvidia_incdir,
install: true,
install_dir: nvidia_install_dir,
gnu_symbol_visibility: 'hidden',
)
meson.add_devenv(environment({
'NVD_LOG': '1',
'LIBVA_DRIVER_NAME': 'nvidia',
'LIBVA_DRIVERS_PATH': meson.project_build_root(),
}))
0707010000000B000081A4000000000000000000000001663926A700000000000000000000000000000000000000000000002D00000000nvidia-vaapi-driver-0.0.12/meson_options.txt0707010000000C000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000002A00000000nvidia-vaapi-driver-0.0.12/nvidia-include0707010000000D000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000003000000000nvidia-vaapi-driver-0.0.12/nvidia-include/class0707010000000E000081A4000000000000000000000001663926A700000956000000000000000000000000000000000000003900000000nvidia-vaapi-driver-0.0.12/nvidia-include/class/cl0040.h/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2001 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0040_h_
#define _cl0040_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#define NV01_MEMORY_LOCAL_USER (0x00000040)
/* NvNotification[] fields and values */
#define NV040_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0040_tag0 {
NvV32 Reserved00[0x7c0];
} Nv040Typedef, Nv01MemoryLocalUser;
#define NV040_TYPEDEF Nv01MemoryLocalUser
/* obsolete stuff */
#define NV01_MEMORY_USER (0x00000040)
#define NV1_MEMORY_USER (0x00000040)
#define Nv01MemoryUser Nv01MemoryLocalUser
#define nv01MemoryUser Nv01MemoryLocalUser
#define Nv1MemoryUser Nv01MemoryLocalUser
#define nv1MemoryUser Nv01MemoryLocalUser
#define nv01MemoryLocalUser Nv01MemoryLocalUser
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0040_h_ */
0707010000000F000081A4000000000000000000000001663926A700000A32000000000000000000000000000000000000003900000000nvidia-vaapi-driver-0.0.12/nvidia-include/class/cl0080.h/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl0080_h_
#define _cl0080_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvlimits.h"
#include "nvtypes.h"
#define NV01_DEVICE_0 (0x00000080)
/* NvNotification[] fields and values */
#define NV080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl0080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv080Typedef, Nv01Device0;
#define NV080_TYPEDEF Nv01Device0
/* NvAlloc parameteters */
#define NV0080_MAX_DEVICES NV_MAX_DEVICES
/**
* @brief Alloc param
*
* @param vaMode mode for virtual address space allocation
* Three modes:
* NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES
* NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE
* NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES
* Detailed description of these modes is in nvos.h
**/
typedef struct {
NvU32 deviceId;
NvHandle hClientShare;
NvHandle hTargetClient;
NvHandle hTargetDevice;
NvV32 flags;
NvU64 vaSpaceSize NV_ALIGN_BYTES(8);
NvU64 vaStartInternal NV_ALIGN_BYTES(8);
NvU64 vaLimitInternal NV_ALIGN_BYTES(8);
NvV32 vaMode;
} NV0080_ALLOC_PARAMETERS;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl0080_h_ */
07070100000010000081A4000000000000000000000001663926A700006B4B000000000000000000000000000000000000003900000000nvidia-vaapi-driver-0.0.12/nvidia-include/class/cl2080.h/*
* SPDX-FileCopyrightText: Copyright (c) 2002-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl2080_h_
#define _cl2080_h_
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "nvlimits.h"
#define NV20_SUBDEVICE_0 (0x00002080)
/* event values */
#define NV2080_NOTIFIERS_SW (0)
#define NV2080_NOTIFIERS_HOTPLUG (1)
#define NV2080_NOTIFIERS_POWER_CONNECTOR (2)
#define NV2080_NOTIFIERS_THERMAL_SW (3)
#define NV2080_NOTIFIERS_THERMAL_HW (4)
#define NV2080_NOTIFIERS_FULL_SCREEN_CHANGE (5)
#define NV2080_NOTIFIERS_EVENTBUFFER (6)
#define NV2080_NOTIFIERS_DP_IRQ (7)
#define NV2080_NOTIFIERS_GR_DEBUG_INTR (8)
#define NV2080_NOTIFIERS_PMU_EVENT (9)
#define NV2080_NOTIFIERS_PMU_COMMAND (10)
#define NV2080_NOTIFIERS_TIMER (11)
#define NV2080_NOTIFIERS_GRAPHICS (12)
#define NV2080_NOTIFIERS_PPP (13)
#define NV2080_NOTIFIERS_VLD (14) // also known as BSP
#define NV2080_NOTIFIERS_NVDEC0 NV2080_NOTIFIERS_VLD
#define NV2080_NOTIFIERS_NVDEC1 (15)
#define NV2080_NOTIFIERS_NVDEC2 (16)
#define NV2080_NOTIFIERS_NVDEC3 (17)
#define NV2080_NOTIFIERS_NVDEC4 (18)
#define NV2080_NOTIFIERS_RESERVED19 (19)
#define NV2080_NOTIFIERS_RESERVED20 (20)
#define NV2080_NOTIFIERS_RESERVED21 (21)
#define NV2080_NOTIFIERS_PDEC (22) // also known as VP
#define NV2080_NOTIFIERS_CE0 (23)
#define NV2080_NOTIFIERS_CE1 (24)
#define NV2080_NOTIFIERS_CE2 (25)
#define NV2080_NOTIFIERS_CE3 (26)
#define NV2080_NOTIFIERS_CE4 (27)
#define NV2080_NOTIFIERS_CE5 (28)
#define NV2080_NOTIFIERS_CE6 (29)
#define NV2080_NOTIFIERS_CE7 (30)
#define NV2080_NOTIFIERS_CE8 (31)
#define NV2080_NOTIFIERS_CE9 (32)
#define NV2080_NOTIFIERS_PSTATE_CHANGE (33)
#define NV2080_NOTIFIERS_HDCP_STATUS_CHANGE (34)
#define NV2080_NOTIFIERS_FIFO_EVENT_MTHD (35)
#define NV2080_NOTIFIERS_PRIV_RING_HANG (36)
#define NV2080_NOTIFIERS_RC_ERROR (37)
#define NV2080_NOTIFIERS_MSENC (38)
#define NV2080_NOTIFIERS_NVENC0 NV2080_NOTIFIERS_MSENC
#define NV2080_NOTIFIERS_NVENC1 (39)
#define NV2080_NOTIFIERS_NVENC2 (40)
#define NV2080_NOTIFIERS_UNUSED_0 (41) // Unused
#define NV2080_NOTIFIERS_ACPI_NOTIFY (42)
#define NV2080_NOTIFIERS_COOLER_DIAG_ZONE (43)
#define NV2080_NOTIFIERS_THERMAL_DIAG_ZONE (44)
#define NV2080_NOTIFIERS_AUDIO_HDCP_REQUEST (45)
#define NV2080_NOTIFIERS_WORKLOAD_MODULATION_CHANGE (46)
#define NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT (47)
#define NV2080_NOTIFIERS_GPIO_1_RISING_INTERRUPT (48)
#define NV2080_NOTIFIERS_GPIO_2_RISING_INTERRUPT (49)
#define NV2080_NOTIFIERS_GPIO_3_RISING_INTERRUPT (50)
#define NV2080_NOTIFIERS_GPIO_4_RISING_INTERRUPT (51)
#define NV2080_NOTIFIERS_GPIO_5_RISING_INTERRUPT (52)
#define NV2080_NOTIFIERS_GPIO_6_RISING_INTERRUPT (53)
#define NV2080_NOTIFIERS_GPIO_7_RISING_INTERRUPT (54)
#define NV2080_NOTIFIERS_GPIO_8_RISING_INTERRUPT (55)
#define NV2080_NOTIFIERS_GPIO_9_RISING_INTERRUPT (56)
#define NV2080_NOTIFIERS_GPIO_10_RISING_INTERRUPT (57)
#define NV2080_NOTIFIERS_GPIO_11_RISING_INTERRUPT (58)
#define NV2080_NOTIFIERS_GPIO_12_RISING_INTERRUPT (59)
#define NV2080_NOTIFIERS_GPIO_13_RISING_INTERRUPT (60)
#define NV2080_NOTIFIERS_GPIO_14_RISING_INTERRUPT (61)
#define NV2080_NOTIFIERS_GPIO_15_RISING_INTERRUPT (62)
#define NV2080_NOTIFIERS_GPIO_16_RISING_INTERRUPT (63)
#define NV2080_NOTIFIERS_GPIO_17_RISING_INTERRUPT (64)
#define NV2080_NOTIFIERS_GPIO_18_RISING_INTERRUPT (65)
#define NV2080_NOTIFIERS_GPIO_19_RISING_INTERRUPT (66)
#define NV2080_NOTIFIERS_GPIO_20_RISING_INTERRUPT (67)
#define NV2080_NOTIFIERS_GPIO_21_RISING_INTERRUPT (68)
#define NV2080_NOTIFIERS_GPIO_22_RISING_INTERRUPT (69)
#define NV2080_NOTIFIERS_GPIO_23_RISING_INTERRUPT (70)
#define NV2080_NOTIFIERS_GPIO_24_RISING_INTERRUPT (71)
#define NV2080_NOTIFIERS_GPIO_25_RISING_INTERRUPT (72)
#define NV2080_NOTIFIERS_GPIO_26_RISING_INTERRUPT (73)
#define NV2080_NOTIFIERS_GPIO_27_RISING_INTERRUPT (74)
#define NV2080_NOTIFIERS_GPIO_28_RISING_INTERRUPT (75)
#define NV2080_NOTIFIERS_GPIO_29_RISING_INTERRUPT (76)
#define NV2080_NOTIFIERS_GPIO_30_RISING_INTERRUPT (77)
#define NV2080_NOTIFIERS_GPIO_31_RISING_INTERRUPT (78)
#define NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT (79)
#define NV2080_NOTIFIERS_GPIO_1_FALLING_INTERRUPT (80)
#define NV2080_NOTIFIERS_GPIO_2_FALLING_INTERRUPT (81)
#define NV2080_NOTIFIERS_GPIO_3_FALLING_INTERRUPT (82)
#define NV2080_NOTIFIERS_GPIO_4_FALLING_INTERRUPT (83)
#define NV2080_NOTIFIERS_GPIO_5_FALLING_INTERRUPT (84)
#define NV2080_NOTIFIERS_GPIO_6_FALLING_INTERRUPT (85)
#define NV2080_NOTIFIERS_GPIO_7_FALLING_INTERRUPT (86)
#define NV2080_NOTIFIERS_GPIO_8_FALLING_INTERRUPT (87)
#define NV2080_NOTIFIERS_GPIO_9_FALLING_INTERRUPT (88)
#define NV2080_NOTIFIERS_GPIO_10_FALLING_INTERRUPT (89)
#define NV2080_NOTIFIERS_GPIO_11_FALLING_INTERRUPT (90)
#define NV2080_NOTIFIERS_GPIO_12_FALLING_INTERRUPT (91)
#define NV2080_NOTIFIERS_GPIO_13_FALLING_INTERRUPT (92)
#define NV2080_NOTIFIERS_GPIO_14_FALLING_INTERRUPT (93)
#define NV2080_NOTIFIERS_GPIO_15_FALLING_INTERRUPT (94)
#define NV2080_NOTIFIERS_GPIO_16_FALLING_INTERRUPT (95)
#define NV2080_NOTIFIERS_GPIO_17_FALLING_INTERRUPT (96)
#define NV2080_NOTIFIERS_GPIO_18_FALLING_INTERRUPT (97)
#define NV2080_NOTIFIERS_GPIO_19_FALLING_INTERRUPT (98)
#define NV2080_NOTIFIERS_GPIO_20_FALLING_INTERRUPT (99)
#define NV2080_NOTIFIERS_GPIO_21_FALLING_INTERRUPT (100)
#define NV2080_NOTIFIERS_GPIO_22_FALLING_INTERRUPT (101)
#define NV2080_NOTIFIERS_GPIO_23_FALLING_INTERRUPT (102)
#define NV2080_NOTIFIERS_GPIO_24_FALLING_INTERRUPT (103)
#define NV2080_NOTIFIERS_GPIO_25_FALLING_INTERRUPT (104)
#define NV2080_NOTIFIERS_GPIO_26_FALLING_INTERRUPT (105)
#define NV2080_NOTIFIERS_GPIO_27_FALLING_INTERRUPT (106)
#define NV2080_NOTIFIERS_GPIO_28_FALLING_INTERRUPT (107)
#define NV2080_NOTIFIERS_GPIO_29_FALLING_INTERRUPT (108)
#define NV2080_NOTIFIERS_GPIO_30_FALLING_INTERRUPT (109)
#define NV2080_NOTIFIERS_GPIO_31_FALLING_INTERRUPT (110)
#define NV2080_NOTIFIERS_ECC_SBE (111)
#define NV2080_NOTIFIERS_ECC_DBE (112)
#define NV2080_NOTIFIERS_STEREO_EMITTER_DETECTION (113)
#define NV2080_NOTIFIERS_GC5_GPU_READY (114)
#define NV2080_NOTIFIERS_SEC2 (115)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_INC (116)
#define NV2080_NOTIFIERS_GC6_REFCOUNT_DEC (117)
#define NV2080_NOTIFIERS_POWER_EVENT (118)
#define NV2080_NOTIFIERS_CLOCKS_CHANGE (119)
#define NV2080_NOTIFIERS_HOTPLUG_PROCESSING_COMPLETE (120)
#define NV2080_NOTIFIERS_PHYSICAL_PAGE_FAULT (121)
#define NV2080_NOTIFIERS_RESERVED_122 (122)
#define NV2080_NOTIFIERS_NVLINK_ERROR_FATAL (123)
#define NV2080_NOTIFIERS_PRIV_REG_ACCESS_FAULT (124)
#define NV2080_NOTIFIERS_NVLINK_ERROR_RECOVERY_REQUIRED (125)
#define NV2080_NOTIFIERS_NVJPG (126)
#define NV2080_NOTIFIERS_NVJPEG0 NV2080_NOTIFIERS_NVJPG
#define NV2080_NOTIFIERS_RESERVED127 (127)
#define NV2080_NOTIFIERS_RESERVED128 (128)
#define NV2080_NOTIFIERS_RESERVED129 (129)
#define NV2080_NOTIFIERS_RESERVED130 (130)
#define NV2080_NOTIFIERS_RESERVED131 (131)
#define NV2080_NOTIFIERS_RESERVED132 (132)
#define NV2080_NOTIFIERS_RESERVED133 (133)
#define NV2080_NOTIFIERS_RUNLIST_AND_ENG_IDLE (134)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE (135)
#define NV2080_NOTIFIERS_RUNLIST_ACQUIRE_AND_ENG_IDLE (136)
#define NV2080_NOTIFIERS_RUNLIST_IDLE (137)
#define NV2080_NOTIFIERS_TSG_PREEMPT_COMPLETE (138)
#define NV2080_NOTIFIERS_RUNLIST_PREEMPT_COMPLETE (139)
#define NV2080_NOTIFIERS_CTXSW_TIMEOUT (140)
#define NV2080_NOTIFIERS_INFOROM_ECC_OBJECT_UPDATED (141)
#define NV2080_NOTIFIERS_NVTELEMETRY_REPORT_EVENT (142)
#define NV2080_NOTIFIERS_DSTATE_XUSB_PPC (143)
#define NV2080_NOTIFIERS_FECS_CTX_SWITCH (144)
#define NV2080_NOTIFIERS_XUSB_PPC_CONNECTED (145)
#define NV2080_NOTIFIERS_GR0 NV2080_NOTIFIERS_GRAPHICS
#define NV2080_NOTIFIERS_GR1 (146)
#define NV2080_NOTIFIERS_GR2 (147)
#define NV2080_NOTIFIERS_GR3 (148)
#define NV2080_NOTIFIERS_GR4 (149)
#define NV2080_NOTIFIERS_GR5 (150)
#define NV2080_NOTIFIERS_GR6 (151)
#define NV2080_NOTIFIERS_GR7 (152)
#define NV2080_NOTIFIERS_OFA (153)
#define NV2080_NOTIFIERS_DSTATE_HDA (154)
#define NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL (155)
#define NV2080_NOTIFIERS_POISON_ERROR_FATAL (156)
#define NV2080_NOTIFIERS_UCODE_RESET (157)
#define NV2080_NOTIFIERS_PLATFORM_POWER_MODE_CHANGE (158)
#define NV2080_NOTIFIERS_SMC_CONFIG_UPDATE (159)
#define NV2080_NOTIFIERS_INFOROM_RRL_OBJECT_UPDATED (160)
#define NV2080_NOTIFIERS_INFOROM_PBL_OBJECT_UPDATED (161)
#define NV2080_NOTIFIERS_LPWR_DIFR_PREFETCH_REQUEST (162)
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_POSSIBLE_ERROR (164)
#define NV2080_NOTIFIERS_MAXCOUNT (165)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x-1)))
#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7)))
// Indexed CE notifier reference
#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9))
// Indexed MSENC notifier reference
#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVENC(x) (((x) >= NV2080_NOTIFIERS_NVENC0) && ((x) <= NV2080_NOTIFIERS_NVENC2))
// Indexed NVDEC notifier reference
#define NV2080_NOTIFIERS_NVDEC(x) (NV2080_NOTIFIERS_NVDEC0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVDEC(x) (((x) >= NV2080_NOTIFIERS_NVDEC0) && ((x) <= NV2080_NOTIFIERS_NVDEC4))
// Indexed NVJPEG notifier reference
#define NV2080_NOTIFIERS_NVJPEG(x) (NV2080_NOTIFIERS_NVJPEG0 + (x))
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG0))
#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT+(pin))
#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT+(pin))
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_IN_PROGRESS (0x8000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_INVALID_STATE (0x2000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_ERROR_STATE_IN_USE (0x1000)
#define NV2080_SUBDEVICE_NOTIFICATION_STATUS_DONE_SUCCESS (0x0000)
/* exported engine defines */
#define NV2080_ENGINE_TYPE_NULL (0x00000000)
#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001)
#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS
#define NV2080_ENGINE_TYPE_GR1 (0x00000002)
#define NV2080_ENGINE_TYPE_GR2 (0x00000003)
#define NV2080_ENGINE_TYPE_GR3 (0x00000004)
#define NV2080_ENGINE_TYPE_GR4 (0x00000005)
#define NV2080_ENGINE_TYPE_GR5 (0x00000006)
#define NV2080_ENGINE_TYPE_GR6 (0x00000007)
#define NV2080_ENGINE_TYPE_GR7 (0x00000008)
#define NV2080_ENGINE_TYPE_COPY0 (0x00000009)
#define NV2080_ENGINE_TYPE_COPY1 (0x0000000a)
#define NV2080_ENGINE_TYPE_COPY2 (0x0000000b)
#define NV2080_ENGINE_TYPE_COPY3 (0x0000000c)
#define NV2080_ENGINE_TYPE_COPY4 (0x0000000d)
#define NV2080_ENGINE_TYPE_COPY5 (0x0000000e)
#define NV2080_ENGINE_TYPE_COPY6 (0x0000000f)
#define NV2080_ENGINE_TYPE_COPY7 (0x00000010)
#define NV2080_ENGINE_TYPE_COPY8 (0x00000011)
#define NV2080_ENGINE_TYPE_COPY9 (0x00000012)
#define NV2080_ENGINE_TYPE_BSP (0x00000013)
#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP
#define NV2080_ENGINE_TYPE_NVDEC1 (0x00000014)
#define NV2080_ENGINE_TYPE_NVDEC2 (0x00000015)
#define NV2080_ENGINE_TYPE_NVDEC3 (0x00000016)
#define NV2080_ENGINE_TYPE_NVDEC4 (0x00000017)
#define NV2080_ENGINE_TYPE_RESERVED18 (0x00000018)
#define NV2080_ENGINE_TYPE_RESERVED19 (0x00000019)
#define NV2080_ENGINE_TYPE_RESERVED1A (0x0000001a)
#define NV2080_ENGINE_TYPE_MSENC (0x0000001b)
#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */
#define NV2080_ENGINE_TYPE_NVENC1 (0x0000001c)
#define NV2080_ENGINE_TYPE_NVENC2 (0x0000001d)
#define NV2080_ENGINE_TYPE_VP (0x0000001e)
#define NV2080_ENGINE_TYPE_ME (0x0000001f)
#define NV2080_ENGINE_TYPE_PPP (0x00000020)
#define NV2080_ENGINE_TYPE_MPEG (0x00000021)
#define NV2080_ENGINE_TYPE_SW (0x00000022)
#define NV2080_ENGINE_TYPE_CIPHER (0x00000023)
#define NV2080_ENGINE_TYPE_TSEC NV2080_ENGINE_TYPE_CIPHER
#define NV2080_ENGINE_TYPE_VIC (0x00000024)
#define NV2080_ENGINE_TYPE_MP (0x00000025)
#define NV2080_ENGINE_TYPE_SEC2 (0x00000026)
#define NV2080_ENGINE_TYPE_HOST (0x00000027)
#define NV2080_ENGINE_TYPE_DPU (0x00000028)
#define NV2080_ENGINE_TYPE_PMU (0x00000029)
#define NV2080_ENGINE_TYPE_FBFLCN (0x0000002a)
#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b)
#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG
#define NV2080_ENGINE_TYPE_RESERVED2C (0x0000002c)
#define NV2080_ENGINE_TYPE_RESERVED2D (0x0000002d)
#define NV2080_ENGINE_TYPE_RESERVED2E (0x0000002e)
#define NV2080_ENGINE_TYPE_RESERVED2F (0x0000002f)
#define NV2080_ENGINE_TYPE_RESERVED30 (0x00000030)
#define NV2080_ENGINE_TYPE_RESERVED31 (0x00000031)
#define NV2080_ENGINE_TYPE_RESERVED32 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_LAST (0x00000034)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
#define NV2080_ENGINE_TYPE_COPY_SIZE 10
#define NV2080_ENGINE_TYPE_NVENC_SIZE 3
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 1
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 5
#define NV2080_ENGINE_TYPE_GR_SIZE 8
// Indexed engines
#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i))
#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) < NV2080_ENGINE_TYPE_COPY(NV2080_ENGINE_TYPE_COPY_SIZE)))
#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0)
#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE)))
#define NV2080_ENGINE_TYPE_NVENC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVENC0)
#define NV2080_ENGINE_TYPE_NVDEC(i) (NV2080_ENGINE_TYPE_NVDEC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVDEC(i) (((i) >= NV2080_ENGINE_TYPE_NVDEC0) && ((i) < NV2080_ENGINE_TYPE_NVDEC(NV2080_ENGINE_TYPE_NVDEC_SIZE)))
#define NV2080_ENGINE_TYPE_NVDEC_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVDEC0)
#define NV2080_ENGINE_TYPE_NVJPEG(i) (NV2080_ENGINE_TYPE_NVJPEG0+(i))
#define NV2080_ENGINE_TYPE_IS_NVJPEG(i) (((i) >= NV2080_ENGINE_TYPE_NVJPEG0) && ((i) < NV2080_ENGINE_TYPE_NVJPEG(NV2080_ENGINE_TYPE_NVJPEG_SIZE)))
#define NV2080_ENGINE_TYPE_NVJPEG_IDX(i) ((i) - NV2080_ENGINE_TYPE_NVJPEG0)
#define NV2080_ENGINE_TYPE_GR(i) (NV2080_ENGINE_TYPE_GR0 + (i))
#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0)
#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST)))
/* exported client defines */
#define NV2080_CLIENT_TYPE_TEX (0x00000001)
#define NV2080_CLIENT_TYPE_COLOR (0x00000002)
#define NV2080_CLIENT_TYPE_DEPTH (0x00000003)
#define NV2080_CLIENT_TYPE_DA (0x00000004)
#define NV2080_CLIENT_TYPE_FE (0x00000005)
#define NV2080_CLIENT_TYPE_SCC (0x00000006)
#define NV2080_CLIENT_TYPE_WID (0x00000007)
#define NV2080_CLIENT_TYPE_MSVLD (0x00000008)
#define NV2080_CLIENT_TYPE_MSPDEC (0x00000009)
#define NV2080_CLIENT_TYPE_MSPPP (0x0000000a)
#define NV2080_CLIENT_TYPE_VIC (0x0000000b)
#define NV2080_CLIENT_TYPE_ALLCLIENTS (0xffffffff)
/* GC5 Gpu Ready event defines */
#define NV2080_GC5_EXIT_COMPLETE (0x00000001)
#define NV2080_GC5_ENTRY_ABORTED (0x00000002)
/* Platform Power Mode event defines */
#define NV2080_PLATFORM_POWER_MODE_CHANGE_COMPLETION (0x00000000)
#define NV2080_PLATFORM_POWER_MODE_CHANGE_ACPI_NOTIFICATION (0x00000001)
/* NvNotification[] fields and values */
#define NV2080_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
/* pio method data structure */
typedef volatile struct _cl2080_tag0 {
NvV32 Reserved00[0x7c0];
} Nv2080Typedef, Nv20Subdevice0;
#define NV2080_TYPEDEF Nv20Subdevice0
/* NvAlloc parameteters */
#define NV2080_MAX_SUBDEVICES NV_MAX_SUBDEVICES
typedef struct {
NvU32 subDeviceId;
} NV2080_ALLOC_PARAMETERS;
/* HDCP Status change notification information */
typedef struct Nv2080HdcpStatusChangeNotificationRec {
NvU32 displayId;
NvU32 hdcpStatusChangeNotif;
} Nv2080HdcpStatusChangeNotification;
/* Pstate change notification information */
typedef struct Nv2080PStateChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvU32 NewPstate;
} Nv2080PStateChangeNotification;
/* Clocks change notification information */
typedef struct Nv2080ClocksChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
} Nv2080ClocksChangeNotification;
/* WorkLoad Modulation state change notification information*/
typedef struct Nv2080WorkloadModulationChangeNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvBool WorkloadModulationEnabled;
} Nv2080WorkloadModulationChangeNotification;
/* Hotplug notification information */
typedef struct {
NvU32 plugDisplayMask;
NvU32 unplugDisplayMask;
} Nv2080HotplugNotification;
/* Power state changing notification information */
typedef struct {
NvBool bSwitchToAC;
NvBool bGPUCapabilityChanged;
NvU32 displayMaskAffected;
} Nv2080PowerEventNotification;
/* DP IRQ notification information */
typedef struct Nv2080DpIrqNotificationRec {
NvU32 displayId;
} Nv2080DpIrqNotification;
/* XUSB/PPC D-State change notification information */
typedef struct Nv2080DstateXusbPpcNotificationRec {
NvU32 dstateXusb;
NvU32 dstatePpc;
} Nv2080DstateXusbPpcNotification;
/* XUSB/PPC Connection status notification information */
typedef struct Nv2080XusbPpcConnectStateNotificationRec {
NvBool bConnected;
} Nv2080XusbPpcConnectStateNotification;
/* ACPI event notification information */
typedef struct Nv2080ACPIEvent {
NvU32 event;
} Nv2080ACPIEvent;
/* Cooler Zone notification information */
typedef struct _NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_COOLER_DIAG_ZONE_NOTIFICATION_REC;
/* Thermal Zone notification information */
typedef struct _NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC {
NvU32 currentZone;
} NV2080_THERM_DIAG_ZONE_NOTIFICATION_REC;
/* HDCP ref count change notification information */
typedef struct Nv2080AudioHdcpRequestRec {
NvU32 displayId;
NvU32 requestedState;
} Nv2080AudioHdcpRequest;
/* Gpu ready event information */
typedef struct Nv2080GC5GpuReadyParams {
NvU32 event;
NvU32 sciIntr0;
NvU32 sciIntr1;
} Nv2080GC5GpuReadyParams;
/* Priv reg access fault notification information */
typedef struct {
NvU32 errAddr;
} Nv2080PrivRegAccessFaultNotification;
/* HDA D-State change notification information
* See @HDACODEC_DSTATE for definitions
*/
typedef struct Nv2080DstateHdaCodecNotificationRec {
NvU32 dstateHdaCodec;
} Nv2080DstateHdaCodecNotification;
/*
* Platform Power Mode event information
*/
typedef struct _NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS {
NvU8 platformPowerModeIndex;
NvU8 platformPowerModeMask;
NvU8 eventReason;
} NV2080_PLATFORM_POWER_MODE_CHANGE_STATUS;
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_INDEX 7:0
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_MASK 15:8
#define NV2080_PLATFORM_POWER_MODE_CHANGE_INFO_REASON 23:16
/*
* ENGINE_INFO_TYPE_NV2080 of the engine for which the QOS interrupt has been raised
*/
typedef struct {
NvU32 engineType;
} Nv2080QosIntrNotification;
typedef struct {
NvU64 physAddress NV_ALIGN_BYTES(8);
} Nv2080EccDbeNotification;
/*
* LPWR DIFR Prefetch Request - Size of L2 Cache
*/
typedef struct {
NvU32 l2CacheSize;
} Nv2080LpwrDifrPrefetchNotification;
#ifdef __cplusplus
}; /* extern "C" */
#endif
#endif /* _cl2080_h_ */
07070100000011000081A4000000000000000000000001663926A70000065D000000000000000000000000000000000000003900000000nvidia-vaapi-driver-0.0.12/nvidia-include/class/cl9010.h/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_CL9010_H
#define SDK_CL9010_H
#include "nvtypes.h"
#define NV9010_VBLANK_CALLBACK 0x9010
typedef void (*OSVBLANKCALLBACKPROC)(void * pParm1, void * pParm2);
typedef struct
{
OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time
NvV32 LogicalHead; // Logical Head
void *pParm1; // pParm1
void *pParm2; // pParm2
} NV_VBLANK_CALLBACK_ALLOCATION_PARAMETERS;
#endif // SDK_CL9010_H
07070100000012000081A4000000000000000000000001663926A700002DFE000000000000000000000000000000000000003500000000nvidia-vaapi-driver-0.0.12/nvidia-include/cpuopsys.h/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*! \brief
* Define compile time symbols for CPU type and operating system type.
* This file should only contain preprocessor commands so that
* there are no dependencies on other files.
*
* cpuopsys.h
*
* Copyright (c) 2001, Nvidia Corporation. All rights reserved.
*/
/*!
* Uniform names are defined for compile time options to distinguish
* CPU types and Operating systems.
* Distinctions between CPU and OpSys should be orthogonal.
*
* These uniform names have initially been defined by keying off the
* makefile/build names defined for builds in the OpenGL group.
* Getting the uniform names defined for other builds may require
* different qualifications.
*
* The file is placed here to allow for the possibility of all driver
* components using the same naming convention for conditional compilation.
*/
#ifndef CPUOPSYS_H
#define CPUOPSYS_H
/*****************************************************************************/
/* Define all OS/CPU-Chip related symbols */
/* ***** WINDOWS variations */
#if defined(_WIN32) || defined(_WIN16)
# define NV_WINDOWS
# if defined(_WIN32_WINNT)
# define NV_WINDOWS_NT
# elif defined(_WIN32_WCE)
# define NV_WINDOWS_CE
# else
# define NV_WINDOWS_9X
# endif
#endif /* _WIN32 || defined(_WIN16) */
/* ***** Unix variations */
#if defined(__linux__) && !defined(NV_LINUX) && !defined(NV_VMWARE)
# define NV_LINUX
#endif /* defined(__linux__) */
#if defined(__VMWARE__) && !defined(NV_VMWARE)
# define NV_VMWARE
#endif /* defined(__VMWARE__) */
/* SunOS + gcc */
#if defined(__sun__) && defined(__svr4__) && !defined(NV_SUNOS)
# define NV_SUNOS
#endif /* defined(__sun__) && defined(__svr4__) */
/* SunOS + Sun Compiler (named SunPro, Studio or Forte) */
#if defined(__SUNPRO_C) || defined(__SUNPRO_CC)
# define NV_SUNPRO_C
# define NV_SUNOS
#endif /* defined(_SUNPRO_C) || defined(__SUNPRO_CC) */
#if defined(__FreeBSD__) && !defined(NV_BSD)
# define NV_BSD
#endif /* defined(__FreeBSD__) */
/* XXXar don't define NV_UNIX on MacOSX or vxworks or QNX */
#if (defined(__unix__) || defined(__unix) || defined(__INTEGRITY) ) && !defined(nvmacosx) && !defined(vxworks) && !defined(NV_UNIX) && !defined(__QNX__) && !defined(__QNXNTO__)/* XXX until removed from Makefiles */
# define NV_UNIX
#endif /* defined(__unix__) */
#if (defined(__QNX__) || defined(__QNXNTO__)) && !defined(NV_QNX)
# define NV_QNX
#endif
#if (defined(__ANDROID__) || defined(ANDROID)) && !defined(NV_ANDROID)
# define NV_ANDROID
#endif
#if defined(DceCore) && !defined(NV_DCECORE)
# define NV_DCECORE
#endif
/* ***** Apple variations */
#if defined(macintosh) || defined(__APPLE__)
# define NV_MACINTOSH
# if defined(__MACH__)
# define NV_MACINTOSH_OSX
# else
# define NV_MACINTOSH_OS9
# endif
# if defined(__LP64__)
# define NV_MACINTOSH_64
# endif
#endif /* defined(macintosh) */
/* ***** VxWorks */
/* Tornado 2.21 is gcc 2.96 and #defines __vxworks. */
/* Tornado 2.02 is gcc 2.7.2 and doesn't define any OS symbol, so we rely on */
/* the build system #defining vxworks. */
#if defined(__vxworks) || defined(vxworks)
# define NV_VXWORKS
#endif
/* ***** Integrity OS */
#if defined(__INTEGRITY)
# if !defined(NV_INTEGRITY)
# define NV_INTEGRITY
# endif
#endif
/* ***** Processor type variations */
/* Note: The prefix NV_CPU_* is taken by Nvcm.h */
#if ((defined(_M_IX86) || defined(__i386__) || defined(__i386)) && !defined(NVCPU_X86)) /* XXX until removed from Makefiles */
/* _M_IX86 for windows, __i386__ for Linux (or any x86 using gcc) */
/* __i386 for Studio compiler on Solaris x86 */
# define NVCPU_X86 /* any IA32 machine (not x86-64) */
# define NVCPU_MIN_PAGE_SHIFT 12
#endif
#if defined(NV_LINUX) && defined(__ia64__)
# define NVCPU_IA64_LINUX /* any IA64 for Linux opsys */
#endif
#if defined(NVCPU_IA64_WINDOWS) || defined(NVCPU_IA64_LINUX) || defined(IA64)
# define NVCPU_IA64 /* any IA64 for any opsys */
#endif
#if (defined(NV_MACINTOSH) && !(defined(__i386__) || defined(__x86_64__))) || defined(__PPC__) || defined(__ppc)
# if defined(__powerpc64__) && defined(__LITTLE_ENDIAN__)
# ifndef NVCPU_PPC64LE
# define NVCPU_PPC64LE /* PPC 64-bit little endian */
# endif
# else
# ifndef NVCPU_PPC
# define NVCPU_PPC /* any non-PPC64LE PowerPC architecture */
# endif
# ifndef NV_BIG_ENDIAN
# define NV_BIG_ENDIAN
# endif
# endif
# define NVCPU_FAMILY_PPC
#endif
#if defined(__x86_64) || defined(AMD64) || defined(_M_AMD64)
# define NVCPU_X86_64 /* any x86-64 for any opsys */
#endif
#if defined(NVCPU_X86) || defined(NVCPU_X86_64)
# define NVCPU_FAMILY_X86
#endif
#if defined(__riscv) && (__riscv_xlen==64)
# define NVCPU_RISCV64
# if defined(__nvriscv)
# define NVCPU_NVRISCV64
# endif
#endif
#if defined(__arm__) || defined(_M_ARM)
/*
* 32-bit instruction set on, e.g., ARMv7 or AArch32 execution state
* on ARMv8
*/
# define NVCPU_ARM
# define NVCPU_MIN_PAGE_SHIFT 12
#endif
#if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64)
# define NVCPU_AARCH64 /* 64-bit A64 instruction set on ARMv8 */
# define NVCPU_MIN_PAGE_SHIFT 12
#endif
#if defined(NVCPU_ARM) || defined(NVCPU_AARCH64)
# define NVCPU_FAMILY_ARM
#endif
#if defined(__SH4__)
# ifndef NVCPU_SH4
# define NVCPU_SH4 /* Renesas (formerly Hitachi) SH4 */
# endif
# if defined NV_WINDOWS_CE
# define NVCPU_MIN_PAGE_SHIFT 12
# endif
#endif
/* For Xtensa processors */
#if defined(__XTENSA__)
# define NVCPU_XTENSA
# if defined(__XTENSA_EB__)
# define NV_BIG_ENDIAN
# endif
#endif
/*
* Other flavors of CPU type should be determined at run-time.
* For example, an x86 architecture with/without SSE.
* If it can compile, then there's no need for a compile time option.
* For some current GCC limitations, these may be fixed by using the Intel
* compiler for certain files in a Linux build.
*/
/* The minimum page size can be determined from the minimum page shift */
#if defined(NVCPU_MIN_PAGE_SHIFT)
#define NVCPU_MIN_PAGE_SIZE (1 << NVCPU_MIN_PAGE_SHIFT)
#endif
#if defined(NVCPU_IA64) || defined(NVCPU_X86_64) || \
defined(NV_MACINTOSH_64) || defined(NVCPU_AARCH64) || \
defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64)
# define NV_64_BITS /* all architectures where pointers are 64 bits */
#else
/* we assume 32 bits. I don't see a need for NV_16_BITS. */
#endif
/* For verification-only features not intended to be included in normal drivers */
#if (defined(NV_MODS) || defined(NV_GSP_MODS)) && defined(DEBUG) && !defined(DISABLE_VERIF_FEATURES)
#define NV_VERIF_FEATURES
#endif
/*
* New, safer family of #define's -- these ones use 0 vs. 1 rather than
* defined/!defined. This is advantageous because if you make a typo,
* say misspelled ENDIAN:
*
* #if NVCPU_IS_BIG_ENDAIN
*
* ...some compilers can give you a warning telling you that you screwed up.
* The compiler can also give you a warning if you forget to #include
* "cpuopsys.h" in your code before the point where you try to use these
* conditionals.
*
* Also, the names have been prefixed in more cases with "CPU" or "OS" for
* increased clarity. You can tell the names apart from the old ones because
* they all use "_IS_" in the name.
*
* Finally, these can be used in "if" statements and not just in #if's. For
* example:
*
* if (NVCPU_IS_BIG_ENDIAN) x = Swap32(x);
*
* Maybe some day in the far-off future these can replace the old #define's.
*/
#define NV_IS_MODS 0
#if defined(NV_GSP_MODS)
#define NV_IS_GSP_MODS 1
#else
#define NV_IS_GSP_MODS 0
#endif
#define NVOS_IS_WINDOWS 0
#if defined(NV_WINDOWS_CE)
#define NVOS_IS_WINDOWS_CE 1
#else
#define NVOS_IS_WINDOWS_CE 0
#endif
#if defined(NV_LINUX)
#define NVOS_IS_LINUX 1
#else
#define NVOS_IS_LINUX 0
#endif
#if defined(NV_UNIX)
#define NVOS_IS_UNIX 1
#else
#define NVOS_IS_UNIX 0
#endif
#if defined(NV_BSD)
#define NVOS_IS_FREEBSD 1
#else
#define NVOS_IS_FREEBSD 0
#endif
#if defined(NV_SUNOS)
#define NVOS_IS_SOLARIS 1
#else
#define NVOS_IS_SOLARIS 0
#endif
#define NVOS_IS_VMWARE 0
#if defined(NV_QNX)
#define NVOS_IS_QNX 1
#else
#define NVOS_IS_QNX 0
#endif
#if defined(NV_ANDROID)
#define NVOS_IS_ANDROID 1
#else
#define NVOS_IS_ANDROID 0
#endif
#if defined(NV_MACINTOSH)
#define NVOS_IS_MACINTOSH 1
#else
#define NVOS_IS_MACINTOSH 0
#endif
#if defined(NV_VXWORKS)
#define NVOS_IS_VXWORKS 1
#else
#define NVOS_IS_VXWORKS 0
#endif
#if defined(NV_LIBOS)
#define NVOS_IS_LIBOS 1
#else
#define NVOS_IS_LIBOS 0
#endif
#if defined(NV_INTEGRITY)
#define NVOS_IS_INTEGRITY 1
#else
#define NVOS_IS_INTEGRITY 0
#endif
#if defined(NVCPU_X86)
#define NVCPU_IS_X86 1
#else
#define NVCPU_IS_X86 0
#endif
#if defined(NVCPU_RISCV64)
#define NVCPU_IS_RISCV64 1
#else
#define NVCPU_IS_RISCV64 0
#endif
#if defined(NVCPU_NVRISCV64)
#define NVCPU_IS_NVRISCV64 1
#else
#define NVCPU_IS_NVRISCV64 0
#endif
#if defined(NVCPU_IA64)
#define NVCPU_IS_IA64 1
#else
#define NVCPU_IS_IA64 0
#endif
#if defined(NVCPU_X86_64)
#define NVCPU_IS_X86_64 1
#else
#define NVCPU_IS_X86_64 0
#endif
#if defined(NVCPU_FAMILY_X86)
#define NVCPU_IS_FAMILY_X86 1
#else
#define NVCPU_IS_FAMILY_X86 0
#endif
#if defined(NVCPU_PPC)
#define NVCPU_IS_PPC 1
#else
#define NVCPU_IS_PPC 0
#endif
#if defined(NVCPU_PPC64LE)
#define NVCPU_IS_PPC64LE 1
#else
#define NVCPU_IS_PPC64LE 0
#endif
#if defined(NVCPU_FAMILY_PPC)
#define NVCPU_IS_FAMILY_PPC 1
#else
#define NVCPU_IS_FAMILY_PPC 0
#endif
#if defined(NVCPU_ARM)
#define NVCPU_IS_ARM 1
#else
#define NVCPU_IS_ARM 0
#endif
#if defined(NVCPU_AARCH64)
#define NVCPU_IS_AARCH64 1
#else
#define NVCPU_IS_AARCH64 0
#endif
#if defined(NVCPU_FAMILY_ARM)
#define NVCPU_IS_FAMILY_ARM 1
#else
#define NVCPU_IS_FAMILY_ARM 0
#endif
#if defined(NVCPU_SH4)
#define NVCPU_IS_SH4 1
#else
#define NVCPU_IS_SH4 0
#endif
#if defined(NVCPU_XTENSA)
#define NVCPU_IS_XTENSA 1
#else
#define NVCPU_IS_XTENSA 0
#endif
#if defined(NV_BIG_ENDIAN)
#define NVCPU_IS_BIG_ENDIAN 1
#else
#define NVCPU_IS_BIG_ENDIAN 0
#endif
#if defined(NV_64_BITS)
#define NVCPU_IS_64_BITS 1
#else
#define NVCPU_IS_64_BITS 0
#endif
#if defined(NVCPU_FAMILY_ARM)
#define NVCPU_IS_PCIE_CACHE_COHERENT 0
#else
#define NVCPU_IS_PCIE_CACHE_COHERENT 1
#endif
#if defined(NV_DCECORE)
#define NVOS_IS_DCECORE 1
#else
#define NVOS_IS_DCECORE 0
#endif
/*****************************************************************************/
#endif /* CPUOPSYS_H */
07070100000013000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000002F00000000nvidia-vaapi-driver-0.0.12/nvidia-include/ctrl07070100000014000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000003800000000nvidia-vaapi-driver-0.0.12/nvidia-include/ctrl/ctrl000007070100000015000081A4000000000000000000000001663926A700000A63000000000000000000000000000000000000004700000000nvidia-vaapi-driver-0.0.12/nvidia-include/ctrl/ctrl0000/ctrl0000base.h/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000base.finn
//
#include "ctrl/ctrlxxxx.h"
/* NV01_ROOT (client) control commands and parameters */
#define NV0000_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x0000,NV0000_CTRL_##cat,idx)
/* Client command categories (6bits) */
#define NV0000_CTRL_RESERVED (0x00)
#define NV0000_CTRL_SYSTEM (0x01)
#define NV0000_CTRL_GPU (0x02)
#define NV0000_CTRL_GSYNC (0x03)
#define NV0000_CTRL_DIAG (0x04)
#define NV0000_CTRL_EVENT (0x05)
#define NV0000_CTRL_NVD (0x06)
#define NV0000_CTRL_SWINSTR (0x07)
#define NV0000_CTRL_GSPC (0x08)
#define NV0000_CTRL_PROC (0x09)
#define NV0000_CTRL_SYNC_GPU_BOOST (0x0A)
#define NV0000_CTRL_GPUACCT (0x0B)
#define NV0000_CTRL_VGPU (0x0C)
#define NV0000_CTRL_CLIENT (0x0D)
// per-OS categories start at highest category and work backwards
#define NV0000_CTRL_OS_WINDOWS (0x3F)
#define NV0000_CTRL_OS_MACOS (0x3E)
#define NV0000_CTRL_OS_UNIX (0x3D)
/*
* NV0000_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_NULL (0x0) /* finn: Evaluated from "(FINN_NV01_ROOT_RESERVED_INTERFACE_ID << 8) | 0x0" */
/* _ctrl0000_base_h_ */
07070100000016000081A4000000000000000000000001663926A7000081B2000000000000000000000000000000000000004600000000nvidia-vaapi-driver-0.0.12/nvidia-include/ctrl/ctrl0000/ctrl0000gpu.h/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000gpu.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrlxxxx.h"
#include "nvlimits.h"
/* NV01_ROOT (client) GPU control commands and parameters */
/*
* NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
*
* This command returns a table of attached gpuId values.
* The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size.
*
* gpuIds[]
* This parameter returns the table of attached GPU IDs.
* The GPU ID is an opaque platform-dependent value that can be used
* with the NV0000_CTRL_CMD_GPU_GET_ID_INFO command to retrieve
* additional information about the GPU. The valid entries in gpuIds[]
* are contiguous, with a value of NV0000_CTRL_GPU_INVALID_ID indicating
* the invalid entries.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS (0x201) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_ATTACHED_GPUS 32
#define NV0000_CTRL_GPU_INVALID_ID (0xffffffff)
#define NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
} NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS;
/*
* Deprecated. Please use NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 instead.
*/
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO (0x202) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_SZNAME 128
#define NV0000_CTRL_NO_NUMA_NODE (-1)
#define NV0000_CTRL_GPU_GET_ID_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_GPU_GET_ID_INFO_PARAMS {
NvU32 gpuId;
NvU32 gpuFlags;
NvU32 deviceInstance;
NvU32 subDeviceInstance;
NV_DECLARE_ALIGNED(NvP64 szName, 8);
NvU32 sliStatus;
NvU32 boardId;
NvU32 gpuInstance;
NvS32 numaId;
} NV0000_CTRL_GPU_GET_ID_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2
* This command returns GPU instance information for the specified GPU.
*
* [in] gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* [out] gpuFlags
* This parameter returns various flags values for the specified GPU.
* Valid flag values include:
* NV0000_CTRL_GPU_ID_INFO_IN_USE
* When true this flag indicates there are client references
* to the GPU in the form of device class instantiations (see
* NV01_DEVICE or NV03_DEVICE descriptions for details).
* NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE
* When true this flag indicates the GPU is linked into an
* active SLI device.
* NV0000_CTRL_GPU_ID_INFO_MOBILE
* When true this flag indicates the GPU is a mobile GPU.
* NV0000_CTRL_GPU_ID_BOOT_MASTER
* When true this flag indicates the GPU is the boot master GPU.
* NV0000_CTRL_GPU_ID_INFO_SOC
* When true this flag indicates the GPU is part of a
* System-on-Chip (SOC).
* NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED
* When ATS is enabled on the system.
* [out] deviceInstance
* This parameter returns the broadcast device instance number associated
* with the specified GPU. This value can be used to instantiate
* a broadcast reference to the GPU using the NV01_DEVICE classes.
* [out] subDeviceInstance
* This parameter returns the unicast subdevice instance number
* associated with the specified GPU. This value can be used to
* instantiate a unicast reference to the GPU using the NV20_SUBDEVICE
* classes.
* [out] sliStatus
* This parameters returns the SLI status for the specified GPU.
* Legal values for this member are described by NV0000_CTRL_SLI_STATUS.
* [out] boardId
* This parameter returns the board ID value with which the
* specified GPU is associated. Multiple GPUs can share the
* same board ID in multi-GPU configurations.
* [out] gpuInstance
* This parameter returns the GPU instance number for the specified GPU.
* GPU instance numbers are assigned in bus-probe order beginning with
* zero and are limited to one less the number of GPUs in the system.
* [out] numaId
* This parameter returns the ID of NUMA node for the specified GPU.
* In case there is no NUMA node, NV0000_CTRL_NO_NUMA_NODE is returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 (0x205) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS {
NvU32 gpuId;
NvU32 gpuFlags;
NvU32 deviceInstance;
NvU32 subDeviceInstance;
NvU32 sliStatus;
NvU32 boardId;
NvU32 gpuInstance;
NvS32 numaId;
} NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS;
/* valid flags values */
#define NV0000_CTRL_GPU_ID_INFO_IN_USE 0:0
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_IN_USE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE 1:1
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_LINKED_INTO_SLI_DEVICE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE 2:2
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_MOBILE_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER 3:3
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_BOOT_MASTER_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_SOC 5:5
#define NV0000_CTRL_GPU_ID_INFO_SOC_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_SOC_TRUE (0x00000001)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED 6:6
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_FALSE (0x00000000)
#define NV0000_CTRL_GPU_ID_INFO_ATS_ENABLED_TRUE (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_GET_INIT_STATUS
*
* This command returns the initialization status for the specified GPU, and
* will return NV_ERR_INVALID_STATE if called prior to GPU
* initialization.
*
* gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* status
* This parameter returns the status code identifying the initialization
* state of the GPU. If this parameter has the value NV_OK,
* then no errors were detected during GPU initialization. Otherwise, this
* parameter specifies the top-level error that was detected during GPU
* initialization. Note that a value of NV_OK only means that
* no errors were detected during the actual GPU initialization, and other
* errors may have occurred that prevent the GPU from being attached or
* accessible via the NV01_DEVICE or NV20_SUBDEVICE classes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_GPU_GET_INIT_STATUS (0x203) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS {
NvU32 gpuId;
NvU32 status;
} NV0000_CTRL_GPU_GET_INIT_STATUS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS
*
* This command returns a mask of valid device IDs. These device IDs
* can be used to instantiate the NV01_DEVICE_0 class (see NV01_DEVICE_0
* for more information).
*
* deviceIds
* This parameter returns the mask of valid device IDs. Each enabled bit
* in the mask corresponds to a valid device instance. Valid device
* instances can be used to initialize the NV0080_ALLOC_PARAMETERS
* structure when using NvRmAlloc to instantiate device handles. The
* number of device IDs will not exceed NV_MAX_DEVICES in number.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS (0x204) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS {
NvU32 deviceIds;
} NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_PROBED_IDS
*
* This command returns a table of probed gpuId values.
* The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size.
*
* gpuIds[]
* This parameter returns the table of probed GPU IDs.
* The GPU ID is an opaque platform-dependent value that can
* be used with the NV0000_CTRL_CMD_GPU_ATTACH_IDS and
* NV0000_CTRL_CMD_GPU_DETACH_ID commands to attach and detach
* the GPU.
* The valid entries in gpuIds[] are contiguous, with a value
* of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries.
* excludedGpuIds[]
* This parameter returns the table of excluded GPU IDs.
* An excluded GPU ID is an opaque platform-dependent value that
* can be used with NV0000_CTRL_CMD_GPU_GET_PCI_INFO and
* NV0000_CTRL_CMD_GPU_GET_UUID_INFO.
* The valid entries in excludedGpuIds[] are contiguous, with a value
* of NV0000_CTRL_GPU_INVALID_ID indicating the invalid entries.
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_GPU_GET_PROBED_IDS (0x214) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_MAX_PROBED_GPUS NV_MAX_DEVICES
#define NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS_MESSAGE_ID (0x14U)
typedef struct NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
NvU32 excludedGpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
} NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_PCI_INFO
*
* This command takes a gpuId and returns PCI bus information about
* the device. If the OS does not support returning PCI bus
* information, this call will return NV_ERR_NOT_SUPPORTED
*
* gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
*
* domain
* This parameter returns the PCI domain of the GPU.
*
* bus
* This parameter returns the PCI bus of the GPU.
*
* slot
* This parameter returns the PCI slot of the GPU.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_GET_PCI_INFO (0x21b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS_MESSAGE_ID (0x1BU)
typedef struct NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS {
NvU32 gpuId;
NvU32 domain;
NvU16 bus;
NvU16 slot;
} NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_ATTACH_IDS
*
* This command attaches the GPUs with the gpuIds matching those in
* the table provided by the client.
* The table is NV0000_CTRL_GPU_MAX_PROBED_GPUS entries in size.
*
* gpuIds[]
* This parameter holds the table of gpuIds to attach. At least
* one gpuId must be specified; clients may use the special
* gpuId value NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS to indicate
* that all probed GPUs are to be attached.
* The entries in gpuIds[] must be contiguous, with a value of
* NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid
* entry.
* If one or more of the gpuId values do not specify a GPU found
* in the system, the NV_ERR_INVALID_ARGUMENT error
* status is returned.
*
* failedId
* If NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is specified and
* a GPU cannot be attached, the NV0000_CTRL_CMD_GPU_ATTACH_IDS
* command returns an error code and saves the failing GPU's
* gpuId in this field.
*
* If a table of gpuIds is provided, these gpuIds will be validated
* against the RM's table of probed gpuIds and attached in turn,
* if valid; if NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS is used, all
* probed gpuIds will be attached, in the order the associated GPUs
* were probed in by the RM.
*
* If a gpuId fails to attach, this gpuId is stored in the failedId
* field. Any GPUs attached by the command prior the failure are
* detached.
*
* If multiple clients use NV0000_CTRL_CMD_GPU_ATTACH_IDS to attach
* a gpuId, the RM ensures that the gpuId won't be detached until
* all clients have issued a call to NV0000_CTRL_CMD_GPU_DETACH_IDS
* to detach the gpuId (or have terminated).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_IRQ_EDGE_TRIGGERED
* NV_ERR_IRQ_NOT_FIRING
*/
#define NV0000_CTRL_CMD_GPU_ATTACH_IDS (0x215) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_ATTACH_ALL_PROBED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_ATTACH_IDS_PARAMS_MESSAGE_ID (0x15U)
typedef struct NV0000_CTRL_GPU_ATTACH_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_PROBED_GPUS];
NvU32 failedId;
} NV0000_CTRL_GPU_ATTACH_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_DETACH_IDS
*
* This command detaches the GPUs with the gpuIds matching those in
* the table provided by the client.
* The table is NV0000_CTRL_GPU_MAX_ATTACHED_GPUS entries in size.
*
* gpuIds[]
* This parameter holds the table of gpuIds to detach. At least
* one gpuId must be specified; clients may use the special
* gpuId NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS to indicate that
* all attached GPUs are to be detached.
* The entries in gpuIds[] must be contiguous, with a value of
* NV0000_CTRL_GPU_INVALID_ID to indicate the first invalid
* entry.
* If one or more of the gpuId values do not specify a GPU found
* in the system, the NV_ERR_INVALID_ARGUMENT error
* status is returned.
*
* If a table of gpuIds is provided, these gpuIds will be validated
* against the RM's list of attached gpuIds; each valid gpuId is
* detached immediately if it's no longer in use (i.e. if there are
* no client references to the associated GPU in the form of
* device class instantiations (see the NV01_DEVICE or NV03_DEVICE
* descriptions for details)) and if no other client still requires
* the associated GPU to be attached.
*
* If a given gpuId can't be detached immediately, it will instead
* be detached when the last client reference is freed or when
* the last client that issued NV0000_CTRL_CMD_GPU_ATTACH_IDS for
* this gpuId either issues NV0000_CTRL_CMD_GPU_DETACH_IDS or exits
* without detaching the gpuId explicitly.
*
* Clients may use the NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS command
* to obtain a table of the attached gpuIds.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_DETACH_IDS (0x216) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DETACH_ALL_ATTACHED_IDS (0x0000ffff)
#define NV0000_CTRL_GPU_DETACH_IDS_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV0000_CTRL_GPU_DETACH_IDS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_GPU_MAX_ATTACHED_GPUS];
} NV0000_CTRL_GPU_DETACH_IDS_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_SVM_SIZE
*
* This command is used to get the SVM size.
*
* gpuId
* This parameter uniquely identifies the GPU whose associated
* SVM size is to be returned. The value of this field must
* match one of those in the table returned by
* NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS
*
* SvmSize
* SVM size is returned in this.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_STATE
*
*/
#define NV0000_CTRL_CMD_GPU_GET_SVM_SIZE (0x240) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS_MESSAGE_ID (0x40U)
typedef struct NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS {
NvU32 gpuId;
NvU32 svmSize;
} NV0000_CTRL_GPU_GET_SVM_SIZE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_UUID_INFO
*
* This command returns requested information pertaining to the GPU
* specified by the GPU UUID passed in.
*
* Generally only GPUs that have been attached are visible to this call. Therefore
* queries on unattached GPUs will fail with NV_ERR_OBJECT_NOT_FOUND. However,
* a query for a SHA1 UUID may succeed for an unattached GPU in cases where the GID
* is cached, such as an excluded GPU.
*
* gpuGuid (INPUT)
* The GPU UUID of the gpu whose parameters are to be returned. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* flags (INPUT)
* The _FORMAT* flags designate ascii string format or a binary format.
*
* The _TYPE* flags designate either SHA-1-based (32-hex-character) or
* SHA-256-based (64-hex-character).
*
* gpuId (OUTPUT)
* The GPU ID of the GPU identified by gpuGuid. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* deviceInstance (OUTPUT)
* The device instance of the GPU identified by gpuGuid. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* subdeviceInstance (OUTPUT)
* The subdevice instance of the GPU identified by gpuGuid. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO (0x274) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID" */
/* maximum possible number of bytes of GID information */
#define NV0000_GPU_MAX_GID_LENGTH (0x00000100)
#define NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS_MESSAGE_ID (0x74U)
typedef struct NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS {
NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH];
NvU32 flags;
NvU32 gpuId;
NvU32 deviceInstance;
NvU32 subdeviceInstance;
} NV0000_CTRL_GPU_GET_UUID_INFO_PARAMS;
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_FORMAT_BINARY (0x00000002)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_INFO_FLAGS_TYPE_SHA256 (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID
*
* This command returns the GPU UUID for the provided GPU ID.
* Note that only GPUs that have been attached are visible to this call.
* Therefore queries on unattached GPUs will fail
* with NV_ERR_OBJECT_NOT_FOUND.
*
* gpuId (INPUT)
* The GPU ID whose parameters are to be returned. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* flags (INPUT)
*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII
* This value is used to request the GPU UUID in ASCII format.
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY
* This value is used to request the GPU UUID in binary format.
*
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1
* This value is used to request that the GPU UUID value
* be SHA1-based (32-hex-character).
* NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256
* This value is used to request that the GPU UUID value
* be SHA256-based (64-hex-character).
*
* gpuUuid[NV0000_GPU_MAX_GID_LENGTH] (OUTPUT)
* The GPU UUID of the GPU identified by GPU ID. Refer to
* NV0000_CTRL_CMD_GPU_GET_ID_INFO for more information.
*
* uuidStrLen (OUTPUT)
* The length of the UUID returned which is related to the format that
* was requested using flags.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID (0x275) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS_MESSAGE_ID (0x75U)
typedef struct NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS {
NvU32 gpuId;
NvU32 flags;
NvU8 gpuUuid[NV0000_GPU_MAX_GID_LENGTH];
NvU32 uuidStrLen;
} NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS;
/* valid format values */
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT 1:0
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_ASCII (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY (0x00000002)
/*valid type values*/
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE 2:2
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1 (0x00000000)
#define NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA256 (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE
*
* This command is used to enter or exit the so called "drain" state.
* When this state is enabled, the existing clients continue executing
* as usual, however no new client connections are allowed.
* This is done in order to "drain" the system of the running clients
* in preparation to selectively powering down the GPU.
* No GPU can enter a bleed state if that GPU is in an SLI group.
* In that case, NV_ERR_IN_USE is returned.
* Requires administrator privileges.
*
* It is expected, that the "drain" state will be eventually deprecated
* and replaced with another mechanism to quiesce a GPU (Bug 1718113).
*
* gpuId (INPUT)
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* newState (INPUT)
* This input parameter is used to enter or exit the "drain"
* software state of the GPU specified by the gpuId parameter.
* Possible values are:
* NV0000_CTRL_GPU_DRAIN_STATE_ENABLED
* NV0000_CTRL_GPU_DRAIN_STATE_DISABLED
* flags (INPUT)
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE
* if set, upon reaching quiescence, a request will be made to
* the OS to "forget" the PCI device associated with the
* GPU specified by the gpuId parameter, in case such a request
* is supported by the OS. Otherwise, NV_ERR_NOT_SUPPORTED
* will be returned.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
* NV_ERR_IN_USE
*/
#define NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE (0x278) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
/* Possible values of newState */
#define NV0000_CTRL_GPU_DRAIN_STATE_DISABLED (0x00000000)
#define NV0000_CTRL_GPU_DRAIN_STATE_ENABLED (0x00000001)
/* Defined bits for the "flags" argument */
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE (0x00000001)
#define NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE (0x00000002)
#define NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x78U)
typedef struct NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS {
NvU32 gpuId;
NvU32 newState;
NvU32 flags;
} NV0000_CTRL_GPU_MODIFY_DRAIN_STATE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE
*
* gpuId (INPUT)
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NVOS_STATUS_ERROR_INVALID_ARGUMENT is returned.
* drainState (OUTPUT)
* This parameter returns a value indicating if the "drain"
* state is currently enabled or not for the specified GPU. See the
* description of NV0000_CTRL_CMD_GPU_MODIFY_DRAIN_STATE.
* Possible values are:
* NV0000_CTRL_GPU_DRAIN_STATE_ENABLED
* NV0000_CTRL_GPU_DRAIN_STATE_DISABLED
* flags (OUTPUT)
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE
* if set, upon reaching quiesence, the GPU device will be
* removed automatically from the kernel space, similar
* to what writing "1" to the sysfs "remove" node does.
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_LINK_DISABLE
* after removing the GPU, also disable the parent bridge's
* PCIe link. This flag can only be set in conjunction with
* NV0000_CTRL_GPU_DRAIN_STATE_FLAG_REMOVE_DEVICE, and then
* only when the GPU is already idle (not attached).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE (0x279) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS_MESSAGE_ID (0x79U)
typedef struct NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS {
NvU32 gpuId;
NvU32 drainState;
NvU32 flags;
} NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_DISCOVER
*
* This request asks the OS to scan the PCI tree or a sub-tree for GPUs,
* that are not yet known to the OS, and to make them available for use.
* If all of domain:bus:slot.function are zeros, the entire tree is scanned,
* otherwise the parameters identify the bridge device, that roots the
* subtree to be scanned.
* Requires administrator privileges.
*
* domain (INPUT)
* PCI domain of the bridge
* bus (INPUT)
* PCI bus of the bridge
* slot (INPUT)
* PCI slot of the bridge
* function (INPUT)
* PCI function of the bridge
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_DEVICE
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_OPERATING_SYSTEM
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_GPU_DISCOVER (0x27a) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | 0x7A" */
typedef struct NV0000_CTRL_GPU_DISCOVER_PARAMS {
NvU32 domain;
NvU8 bus;
NvU8 slot;
NvU8 function;
} NV0000_CTRL_GPU_DISCOVER_PARAMS;
/*
* NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE
*
* This command is used to get the content of the MemOp (CUDA Memory Operation)
* enablement mask, which can be overridden by using the MemOpOverride RegKey.
*
* The enableMask member must be treated as a bitmask, where each bit controls
* the enablement of a feature.
*
* So far, the only feature which is defined controls to whole MemOp APIs.
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE (0x27b) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS_MESSAGE_ID (0x7BU)
typedef struct NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS {
NvU32 enableMask;
} NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS;
#define NV0000_CTRL_GPU_FLAGS_MEMOP_ENABLE (0x00000001)
/*
* NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT
*
* This privileged command is used to disable initialization for the NVLinks
* provided in the mask.
*
* The mask must be applied before the GPU is attached. DISABLE_NVLINK_INIT
* is an NOP for non-NVLink GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_DEVICE
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_STATE
* NV_ERR_IN_USE
*
*/
#define NV0000_CTRL_CMD_GPU_DISABLE_NVLINK_INIT (0x281) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS {
NvU32 gpuId;
NvU32 mask;
NvBool bSkipHwNvlinkDisable;
} NV0000_CTRL_GPU_DISABLE_NVLINK_INIT_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA 0x00000175
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN 6
#define NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT 5
/*
* NV0000_CTRL_CMD_GPU_LEGACY_CONFIG
*
* Path to use legacy RM GetConfig/Set API. This API is being phased out.
*/
#define NV0000_CTRL_CMD_GPU_LEGACY_CONFIG (0x282) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS {
NvHandle hContext; /* [in] - Handle of object to perform operation on (Device, Subdevice, etc) */
NvU32 opType; /* [in] - Type of API */
NvV32 index; /* [in] - command type */
NvU32 dataType; /* [out] - data union type */
union {
struct {
NvV32 value;
} configGet;
struct {
NvU32 newValue;
NvU32 oldValue;
} configSet;
struct {
NvU8 paramData[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PARAM_DATA];
NvU32 paramSize;
} configEx;
struct {
NvU32 propertyId;
NvU32 propertyIn[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_IN];
NvU32 propertyOut[NV0000_CTRL_GPU_LEGACY_CONFIG_MAX_PROPERTIES_OUT];
} reservedProperty;
} data;
} NV0000_CTRL_GPU_LEGACY_CONFIG_PARAMS;
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET (0x00000000)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET (0x00000001)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_GET_EX (0x00000002)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_SET_EX (0x00000003)
#define NV0000_CTRL_GPU_LEGACY_CONFIG_OP_TYPE_RESERVED (0x00000004)
/*
* NV0000_CTRL_CMD_IDLE_CHANNELS
*/
#define NV0000_CTRL_CMD_IDLE_CHANNELS (0x283) /* finn: Evaluated from "(FINN_NV01_ROOT_GPU_INTERFACE_ID << 8) | NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS {
NvHandle hDevice;
NvHandle hChannel;
NvV32 numChannels;
/* C form: NvP64 phClients NV_ALIGN_BYTES(8); */
NV_DECLARE_ALIGNED(NvP64 phClients, 8);
/* C form: NvP64 phDevices NV_ALIGN_BYTES(8); */
NV_DECLARE_ALIGNED(NvP64 phDevices, 8);
/* C form: NvP64 phChannels NV_ALIGN_BYTES(8); */
NV_DECLARE_ALIGNED(NvP64 phChannels, 8);
NvV32 flags;
NvV32 timeout;
} NV0000_CTRL_GPU_IDLE_CHANNELS_PARAMS;
/* _ctrl0000gpu_h_ */
07070100000017000081A4000000000000000000000001663926A70000E20D000000000000000000000000000000000000004900000000nvidia-vaapi-driver-0.0.12/nvidia-include/ctrl/ctrl0000/ctrl0000system.h/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000system.finn
//
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl0000/ctrl0000base.h"
/* NV01_ROOT (client) system control commands and parameters */
/*
* NV0000_CTRL_CMD_SYSTEM_GET_FEATURES
*
* This command returns a mask of supported features for the SYSTEM category
* of the 0000 class.
*
* Valid features include:
*
* NV0000_CTRL_GET_FEATURES_SLI
* When this bit is set, SLI is supported.
* NV0000_CTRL_GET_FEATURES_UEFI
* When this bit is set, it is a UEFI system.
* NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT
* When this bit is set, EFI has initialized core channel
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_FEATURES (0x1f0) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS_MESSAGE_ID (0xF0U)
typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
NvU32 featuresMask;
} NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS;
/* Valid feature values */
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI 1:1
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UEFI_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001)
/*
* NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION
*
* This command returns the current driver information.
* The first time this is called the size of strings is
* set with the greater of NV_BUILD_BRANCH_VERSION and
* NV_DISPLAY_DRIVER_TITLE. The client then allocates memory
* of size sizeOfStrings for pVersionBuffer and pTitleBuffer
* and calls the command again to receive driver info.
*
* sizeOfStrings
* This field returns the size in bytes of the pVersionBuffer and
* pTitleBuffer strings.
* pDriverVersionBuffer
* This field returns the version (NV_VERSION_STRING).
* pVersionBuffer
* This field returns the version (NV_BUILD_BRANCH_VERSION).
* pTitleBuffer
* This field returns the title (NV_DISPLAY_DRIVER_TITLE).
* changelistNumber
* This field returns the changelist value (NV_BUILD_CHANGELIST_NUM).
* officialChangelistNumber
* This field returns the last official changelist value
* (NV_LAST_OFFICIAL_CHANGELIST_NUM).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U)
typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS {
NvU32 sizeOfStrings;
NV_DECLARE_ALIGNED(NvP64 pDriverVersionBuffer, 8);
NV_DECLARE_ALIGNED(NvP64 pVersionBuffer, 8);
NV_DECLARE_ALIGNED(NvP64 pTitleBuffer, 8);
NvU32 changelistNumber;
NvU32 officialChangelistNumber;
} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO
*
* This command returns system CPU information.
*
* type
* This field returns the processor type.
* Legal processor types include:
* Intel processors:
* P55 : P55C - MMX
* P6 : PPro
* P2 : PentiumII
* P2XC : Xeon & Celeron
* CELA : Celeron-A
* P3 : Pentium-III
* P3_INTL2 : Pentium-III w/integrated L2 (fullspeed, on die, 256K)
* P4 : Pentium 4
* CORE2 : Core2 Duo Conroe
* AMD processors
* K62 : K6-2 w/ 3DNow
* IDT/Centaur processors
* C6 : WinChip C6
* C62 : WinChip 2 w/ 3DNow
* Cyrix processors
* GX : MediaGX
* M1 : 6x86
* M2 : M2
* MGX : MediaGX w/ MMX
* Transmeta processors
* TM_CRUSOE : Transmeta Crusoe(tm)
* PowerPC processors
* PPC603 : PowerPC 603
* PPC604 : PowerPC 604
* PPC750 : PowerPC 750
*
* capabilities
* This field returns the capabilities of the processor.
* Legal processor capabilities include:
* MMX : supports MMX
* SSE : supports SSE
* 3DNOW : supports 3DNow
* SSE2 : supports SSE2
* SFENCE : supports SFENCE
* WRITE_COMBINING : supports write-combining
* ALTIVEC : supports ALTIVEC
* PUT_NEEDS_IO : requires OUT inst w/PUT updates
* NEEDS_WC_WORKAROUND : requires workaround for P4 write-combining bug
* 3DNOW_EXT : supports 3DNow Extensions
* MMX_EXT : supports MMX Extensions
* CMOV : supports CMOV
* CLFLUSH : supports CLFLUSH
* SSE3 : supports SSE3
* NEEDS_WAR_124888 : requires write to GPU while spinning on
* : GPU value
* HT : support hyper-threading
* clock
* This field returns the processor speed in MHz.
* L1DataCacheSize
* This field returns the level 1 data (or unified) cache size
* in kilobytes.
* L2DataCacheSize
* This field returns the level 2 data (or unified) cache size
* in kilobytes.
* dataCacheLineSize
* This field returns the bytes per line in the level 1 data cache.
* numLogicalCpus
* This field returns the number of logical processors. On Intel x86
* systems that support it, this value will incorporate the current state
* of HyperThreading.
* numPhysicalCpus
* This field returns the number of physical processors.
* name
* This field returns the CPU name in ASCII string format.
* family
* Vendor defined Family and Extended Family combined
* model
* Vendor defined Model and Extended Model combined
* stepping
* Silicon stepping
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO (0x102) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS {
NvU32 type; /* processor type */
NvU32 capabilities; /* processor caps */
NvU32 clock; /* processor speed (MHz) */
NvU32 L1DataCacheSize; /* L1 dcache size (KB) */
NvU32 L2DataCacheSize; /* L2 dcache size (KB) */
NvU32 dataCacheLineSize; /* L1 dcache bytes/line */
NvU32 numLogicalCpus; /* logial processor cnt */
NvU32 numPhysicalCpus; /* physical processor cnt*/
NvU8 name[52]; /* embedded cpu name */
NvU32 family; /* Vendor defined Family and Extended Family combined */
NvU32 model; /* Vendor defined Model and Extended Model combined */
NvU8 stepping; /* Silicon stepping */
NvU32 coresOnDie; /* cpu cores per die */
} NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS;
/* processor type values */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_UNKNOWN (0x00000000)
/* Intel types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P5 (0x00000001)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P55 (0x00000002)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P6 (0x00000003)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2 (0x00000004)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P2XC (0x00000005)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELA (0x00000006)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3 (0x00000007)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P3_INTL2 (0x00000008)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_P4 (0x00000009)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2 (0x00000010)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_CELN_M16H (0x00000011)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_CORE2_EXTRM (0x00000012)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ATOM (0x00000013)
/* AMD types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K5 (0x00000030)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K6 (0x00000031)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K62 (0x00000032)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K63 (0x00000033)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K7 (0x00000034)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K8 (0x00000035)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K10 (0x00000036)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_K11 (0x00000037)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_RYZEN (0x00000038)
/* IDT/Centaur types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_C6 (0x00000060)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_C62 (0x00000061)
/* Cyrix types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_GX (0x00000070)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_M1 (0x00000071)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_M2 (0x00000072)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_MGX (0x00000073)
/* Transmeta types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_TM_CRUSOE (0x00000080)
/* IBM types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC603 (0x00000090)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC604 (0x00000091)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_PPC750 (0x00000092)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_POWERN (0x00000093)
/* Unknown ARM architecture CPU type */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_UNKNOWN (0xA0000000)
/* ARM Ltd types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A9 (0xA0000009)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARM_A15 (0xA000000F)
/* NVIDIA types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_1_0 (0xA0001000)
#define NV0000_CTRL_SYSTEM_CPU_TYPE_NV_DENVER_2_0 (0xA0002000)
/* Generic types */
#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000)
/* processor capabilities */
#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001)
#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE (0x00000002)
#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW (0x00000004)
#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 (0x00000008)
#define NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE (0x00000010)
#define NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING (0x00000020)
#define NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC (0x00000040)
#define NV0000_CTRL_SYSTEM_CPU_CAP_PUT_NEEDS_IO (0x00000080)
#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WC_WORKAROUND (0x00000100)
#define NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT (0x00000200)
#define NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT (0x00000400)
#define NV0000_CTRL_SYSTEM_CPU_CAP_CMOV (0x00000800)
#define NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH (0x00001000)
#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_190854 (0x00002000) /* deprecated */
#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 (0x00004000)
#define NV0000_CTRL_SYSTEM_CPU_CAP_NEEDS_WAR_124888 (0x00008000)
#define NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE (0x00010000)
#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 (0x00020000)
#define NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 (0x00040000)
#define NV0000_CTRL_SYSTEM_CPU_CAP_AVX (0x00080000)
#define NV0000_CTRL_SYSTEM_CPU_CAP_ERMS (0x00100000)
/* feature mask (as opposed to bugs, requirements, etc.) */
#define NV0000_CTRL_SYSTEM_CPU_CAP_FEATURE_MASK (0x1f5e7f) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_CPU_CAP_MMX | NV0000_CTRL_SYSTEM_CPU_CAP_SSE | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW | NV0000_CTRL_SYSTEM_CPU_CAP_SSE2 | NV0000_CTRL_SYSTEM_CPU_CAP_SFENCE | NV0000_CTRL_SYSTEM_CPU_CAP_WRITE_COMBINING | NV0000_CTRL_SYSTEM_CPU_CAP_ALTIVEC | NV0000_CTRL_SYSTEM_CPU_CAP_3DNOW_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_MMX_EXT | NV0000_CTRL_SYSTEM_CPU_CAP_CMOV | NV0000_CTRL_SYSTEM_CPU_CAP_CLFLUSH | NV0000_CTRL_SYSTEM_CPU_CAP_SSE3 | NV0000_CTRL_SYSTEM_CPU_CAP_HT_CAPABLE | NV0000_CTRL_SYSTEM_CPU_CAP_SSE41 | NV0000_CTRL_SYSTEM_CPU_CAP_SSE42 | NV0000_CTRL_SYSTEM_CPU_CAP_AVX | NV0000_CTRL_SYSTEM_CPU_CAP_ERMS)" */
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CAPS
*
* This command returns the set of system capabilities in the
* form of an array of unsigned bytes. System capabilities include
* supported features and required workarounds for the system,
* each represented by a byte offset into the table and a bit
* position within that byte.
*
* capsTblSize
* This parameter specifies the size in bytes of the caps table.
* This value should be set to NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE.
* capsTbl
* This parameter specifies a pointer to the client's caps table buffer
* into which the system caps bits will be transferred by the RM.
* The caps table is an array of unsigned bytes.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CAPS (0x103) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x3" */
typedef struct NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS {
NvU32 capsTblSize;
NV_DECLARE_ALIGNED(NvP64 capsTbl, 8);
} NV0000_CTRL_SYSTEM_GET_CAPS_PARAMS;
/* extract cap bit setting from tbl */
#define NV0000_CTRL_SYSTEM_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0000_CTRL_SYSTEM_CAPS_POWER_SLI_SUPPORTED 0:0x01
/* size in bytes of system caps table */
#define NV0000_CTRL_SYSTEM_CAPS_TBL_SIZE 1
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO
*
* This command returns system chipset information.
*
* vendorId
* This parameter returns the vendor identification for the chipset.
* A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset
* cannot be identified.
* deviceId
* This parameter returns the device identification for the chipset.
* A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the chipset
* cannot be identified.
* subSysVendorId
* This parameter returns the subsystem vendor identification for the
* chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the
* chipset cannot be identified.
* subSysDeviceId
* This parameter returns the subsystem device identification for the
* chipset. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates the
* chipset cannot be identified.
* HBvendorId
* This parameter returns the vendor identification for the chipset's
* host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates
* the chipset's host bridge cannot be identified.
* HBdeviceId
* This parameter returns the device identification for the chipset's
* host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID indicates
* the chipset's host bridge cannot be identified.
* HBsubSysVendorId
* This parameter returns the subsystem vendor identification for the
* chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID
* indicates the chipset's host bridge cannot be identified.
* HBsubSysDeviceId
* This parameter returns the subsystem device identification for the
* chipset's host bridge. A value of NV0000_SYSTEM_CHIPSET_INVALID_ID
* indicates the chipset's host bridge cannot be identified.
* sliBondId
* This parameter returns the SLI bond identification for the chipset.
* vendorNameString
* This parameter returns the vendor name string.
* chipsetNameString
* This parameter returns the vendor name string.
* sliBondNameString
* This parameter returns the SLI bond name string.
* flag
* This parameter specifies NV0000_CTRL_SYSTEM_CHIPSET_FLAG_XXX flags:
* _HAS_RESIZABLE_BAR_ISSUE_YES: Chipset where the use of resizable BAR1
* should be disabled - bug 3440153
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CHIPSET_INFO (0x104) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID" */
/* maximum name string length */
#define NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH (0x0000020)
/* invalid id */
#define NV0000_SYSTEM_CHIPSET_INVALID_ID (0xffff)
#define NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS {
NvU16 vendorId;
NvU16 deviceId;
NvU16 subSysVendorId;
NvU16 subSysDeviceId;
NvU16 HBvendorId;
NvU16 HBdeviceId;
NvU16 HBsubSysVendorId;
NvU16 HBsubSysDeviceId;
NvU32 sliBondId;
NvU8 vendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
NvU8 subSysVendorNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
NvU8 chipsetNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
NvU8 sliBondNameString[NV0000_SYSTEM_MAX_CHIPSET_STRING_LENGTH];
NvU32 flags;
} NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS;
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE 0:0
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_NO (0x00000000)
#define NV0000_CTRL_SYSTEM_CHIPSET_FLAG_HAS_RESIZABLE_BAR_ISSUE_YES (0x00000001)
/*
* NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE
*
* This command is used to set the system memory size in pages.
*
* memorySize
* This parameter specifies the system memory size in pages. All values
* are considered legal.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_SET_MEMORY_SIZE (0x107) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS {
NvU32 memorySize;
} NV0000_CTRL_SYSTEM_SET_MEMORY_SIZE_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST
*
* This command is used to retrieve the set of system-level classes
* supported by the platform.
*
* numClasses
* This parameter returns the number of valid entries in the returned
* classes[] list. This parameter will not exceed
* Nv0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE.
* classes
* This parameter returns the list of supported classes
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CLASSLIST (0x108) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID" */
/* maximum number of classes returned in classes[] array */
#define NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE (32)
#define NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS {
NvU32 numClasses;
NvU32 classes[NV0000_CTRL_SYSTEM_MAX_CLASSLIST_SIZE];
} NV0000_CTRL_SYSTEM_GET_CLASSLIST_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT
*
* This command is used to send triggered mobile related system events
* to the RM.
*
* eventType
* This parameter indicates the triggered event type. This parameter
* should specify a valid NV0000_CTRL_SYSTEM_EVENT_TYPE value.
* eventData
* This parameter specifies the type-dependent event data associated
* with EventType. This parameter should specify a valid
* NV0000_CTRL_SYSTEM_EVENT_DATA value.
* bEventDataForced
* This parameter specifies what we have to do, Whether trust current
* Lid/Dock state or not. This parameter should specify a valid
* NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED value.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
* Sync this up (#defines) with one in nvapi.spec!
* (NV_ACPI_EVENT_TYPE & NV_ACPI_EVENT_DATA)
*/
#define NV0000_CTRL_CMD_SYSTEM_NOTIFY_EVENT (0x110) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS {
NvU32 eventType;
NvU32 eventData;
NvBool bEventDataForced;
} NV0000_CTRL_SYSTEM_NOTIFY_EVENT_PARAMS;
/* valid eventType values */
#define NV0000_CTRL_SYSTEM_EVENT_TYPE_LID_STATE (0x00000000)
#define NV0000_CTRL_SYSTEM_EVENT_TYPE_POWER_SOURCE (0x00000001)
#define NV0000_CTRL_SYSTEM_EVENT_TYPE_DOCK_STATE (0x00000002)
#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_LID (0x00000003)
#define NV0000_CTRL_SYSTEM_EVENT_TYPE_TRUST_DOCK (0x00000004)
/* valid eventData values */
#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_OPEN (0x00000000)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_LID_CLOSED (0x00000001)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_BATTERY (0x00000000)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_POWER_AC (0x00000001)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_UNDOCKED (0x00000000)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_DOCKED (0x00000001)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DSM (0x00000000)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_DCS (0x00000001)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_NVIF (0x00000002)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_ACPI (0x00000003)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL (0x00000004)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_COUNT (0x5) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_LID_POLL + 1)" */
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DSM (0x00000000)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_DCS (0x00000001)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_NVIF (0x00000002)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_ACPI (0x00000003)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL (0x00000004)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_COUNT (0x5) /* finn: Evaluated from "(NV0000_CTRL_SYSTEM_EVENT_DATA_TRUST_DOCK_POLL + 1)" */
/* valid bEventDataForced values */
#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_EVENT_DATA_FORCED_TRUE (0x00000001)
/*
* NV000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE
*
* This command is used to query the platform type.
*
* systemType
* This parameter returns the type of the system.
* Legal values for this parameter include:
* NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP
* The system is a desktop platform.
* NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC
* The system is a mobile (non-Toshiba) platform.
* NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP
* The system is a mobile Toshiba platform.
* NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC
* The system is a system-on-a-chip (SOC) platform.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE (0x111) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS_MESSAGE_ID (0x11U)
typedef struct NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS {
NvU32 systemType;
} NV0000_CTRL_CMD_SYSTEM_GET_PLATFORM_TYPE_PARAMS;
/* valid systemType values */
#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_DESKTOP (0x000000)
#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_GENERIC (0x000001)
#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_MOBILE_TOSHIBA (0x000002)
#define NV0000_CTRL_SYSTEM_GET_PLATFORM_TYPE_SOC (0x000003)
/*
* NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL
*
* This command controls the current RmMsg filters.
*
* It is only supported if RmMsg is enabled (e.g. debug builds).
*
* cmd
* GET - Gets the current RmMsg filter string.
* SET - Sets the current RmMsg filter string.
*
* count
* The length of the RmMsg filter string.
*
* data
* The RmMsg filter string.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_DEBUG_RMMSG_CTRL (0x121) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE 512
#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_GET (0x00000000)
#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_CMD_SET (0x00000001)
#define NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS {
NvU32 cmd;
NvU32 count;
NvU8 data[NV0000_CTRL_SYSTEM_DEBUG_RMMSG_SIZE];
} NV0000_CTRL_SYSTEM_DEBUG_RMMSG_CTRL_PARAMS;
/*
* NV0000_CTRL_SYSTEM_HWBC_INFO
*
* This structure contains information about the HWBC (BR04) specified by
* hwbcId.
*
* hwbcId
* This field specifies the HWBC ID.
* firmwareVersion
* This field returns the version of the firmware on the HWBC (BR04), if
* present. This is a packed binary number of the form 0x12345678, which
* corresponds to a firmware version of 12.34.56.78.
* subordinateBus
* This field returns the subordinate bus number of the HWBC (BR04).
* secondaryBus
* This field returns the secondary bus number of the HWBC (BR04).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
typedef struct NV0000_CTRL_SYSTEM_HWBC_INFO {
NvU32 hwbcId;
NvU32 firmwareVersion;
NvU32 subordinateBus;
NvU32 secondaryBus;
} NV0000_CTRL_SYSTEM_HWBC_INFO;
#define NV0000_CTRL_SYSTEM_HWBC_INVALID_ID (0xFFFFFFFF)
/*
* NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO
*
* This command returns information about all Hardware Broadcast (HWBC)
* devices present in the system that are BR04s. To get the complete
* list of HWBCs in the system, all GPUs present in the system must be
* initialized. See the description of NV0000_CTRL_CMD_GPU_ATTACH_IDS to
* accomplish this.
*
* hwbcInfo
* This field is an array of NV0000_CTRL_SYSTEM_HWBC_INFO structures into
* which HWBC information is placed. There is one entry for each HWBC
* present in the system. Valid entries are contiguous, invalid entries
* have the hwbcId equal to NV0000_CTRL_SYSTEM_HWBC_INVALID_ID. If no HWBC
* is present in the system, all the entries would be marked invalid, but
* the return value would still be SUCCESS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_HWBC_INFO (0x124) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_MAX_HWBCS (0x00000080)
#define NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS {
NV0000_CTRL_SYSTEM_HWBC_INFO hwbcInfo[NV0000_CTRL_SYSTEM_MAX_HWBCS];
} NV0000_CTRL_SYSTEM_GET_HWBC_INFO_PARAMS;
/*
* Deprecated. Please use NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 instead.
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS (0x127) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID" */
/*
* NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED must remain equal to the square of
* NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS due to Check RM parsing issues.
* NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS is the maximum size of GPU groups
* allowed for batched P2P caps queries provided by the RM control
* NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX.
*/
#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS 32
#define NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED 1024
#define NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS 8
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER 0xffffffff
/* P2P capabilities status index values */
#define NV0000_CTRL_P2P_CAPS_INDEX_READ 0
#define NV0000_CTRL_P2P_CAPS_INDEX_WRITE 1
#define NV0000_CTRL_P2P_CAPS_INDEX_NVLINK 2
#define NV0000_CTRL_P2P_CAPS_INDEX_ATOMICS 3
#define NV0000_CTRL_P2P_CAPS_INDEX_PROP 4
#define NV0000_CTRL_P2P_CAPS_INDEX_LOOPBACK 5
#define NV0000_CTRL_P2P_CAPS_INDEX_PCI 6
#define NV0000_CTRL_P2P_CAPS_INDEX_C2C 7
#define NV0000_CTRL_P2P_CAPS_INDEX_PCI_BAR1 8
#define NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE 9
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS_MESSAGE_ID (0x27U)
typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS {
NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
NvU32 gpuCount;
NvU32 p2pCaps;
NvU32 p2pOptimalReadCEs;
NvU32 p2pOptimalWriteCEs;
NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
NV_DECLARE_ALIGNED(NvP64 busPeerIds, 8);
} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS;
/* valid p2pCaps values */
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED 0:0
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED 1:1
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED 2:2
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED 3:3
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED 4:4
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED 5:5
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED 6:6
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED 7:7
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED 8:8
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED 9:9
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED 10:10
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED 12:12
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED_TRUE (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED 13:13
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_FALSE (0x00000000)
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_BAR1_SUPPORTED_TRUE (0x00000001)
/* P2P status codes */
#define NV0000_P2P_CAPS_STATUS_OK (0x00)
#define NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED (0x01)
#define NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED (0x02)
#define NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED (0x03)
#define NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY (0x04)
#define NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED (0x05)
/*
* NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2
*
* This command returns peer to peer capabilities present between GPUs.
* Valid requests must present a list of GPU Ids.
*
* [in] gpuIds
* This member contains the array of GPU IDs for which we query the P2P
* capabilities. Valid entries are contiguous, beginning with the first
* entry in the list.
* [in] gpuCount
* This member contains the number of GPU IDs stored in the gpuIds[] array.
* [out] p2pCaps
* This member returns the peer to peer capabilities discovered between the
* GPUs. Valid p2pCaps values include:
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED
* When this bit is set, peer to peer writes between subdevices owned
* by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED
* When this bit is set, peer to peer reads between subdevices owned
* by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED
* When this bit is set, peer to peer PROP between subdevices owned
* by this device are supported. This is enabled by default
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED
* When this bit is set, PCI is supported for all P2P between subdevices
* owned by this device.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED
* When this bit is set, NVLINK is supported for all P2P between subdevices
* owned by this device.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED
* When this bit is set, peer to peer atomics between subdevices owned
* by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED
* When this bit is set, peer to peer loopback is supported for subdevices
* owned by this device.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED
* When this bit is set, indirect peer to peer writes between subdevices
* owned by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED
* When this bit is set, indirect peer to peer reads between subdevices
* owned by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED
* When this bit is set, indirect peer to peer atomics between
* subdevices owned by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED
* When this bit is set, indirect NVLINK is supported for subdevices
* owned by this device.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_C2C_SUPPORTED
* When this bit is set, C2C P2P is supported between the GPUs
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_BAR1_SUPPORTED
* When this bit is set, BAR1 P2P is supported between the GPUs
* mentioned in @ref gpuIds
* [out] p2pOptimalReadCEs
* For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink
* [out] p2pOptimalWriteCEs
* For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink
* [out] p2pCapsStatus
* This member returns status of all supported p2p capabilities. Valid
* status values include:
* NV0000_P2P_CAPS_STATUS_OK
* P2P capability is supported.
* NV0000_P2P_CAPS_STATUS_CHIPSET_NOT_SUPPORTED
* Chipset doesn't support p2p capability.
* NV0000_P2P_CAPS_STATUS_GPU_NOT_SUPPORTED
* GPU doesn't support p2p capability.
* NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED
* IOH topology isn't supported. For e.g. root ports are on different
* IOH.
* NV0000_P2P_CAPS_STATUS_DISABLED_BY_REGKEY
* P2P Capability is disabled by a regkey.
* NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED
* P2P Capability is not supported.
* NV0000_P2P_CAPS_STATUS_NVLINK_SETUP_FAILED
* Indicates that NvLink P2P link setup failed.
* [out] busPeerIds
* Peer ID matrix. It is a one-dimentional array.
* busPeerIds[X * gpuCount + Y] maps from index X to index Y in
* the gpuIds[] table. For invalid or non-existent peer busPeerIds[]
* has the value NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INVALID_PEER.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 (0x12b) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS_MESSAGE_ID (0x2BU)
typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS {
NvU32 gpuIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
NvU32 gpuCount;
NvU32 p2pCaps;
NvU32 p2pOptimalReadCEs;
NvU32 p2pOptimalWriteCEs;
NvU8 p2pCapsStatus[NV0000_CTRL_P2P_CAPS_INDEX_TABLE_SIZE];
NvU32 busPeerIds[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS_SQUARED];
} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX
*
* This command returns peer to peer capabilities present between all pairs of
* GPU IDs {(a, b) : a in gpuIdGrpA and b in gpuIdGrpB}. This can be used to
* collect all P2P capabilities in the system - see the SRT:
* NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX_TEST
* for a demonstration.
*
* The call will query for all pairs between set A and set B, and returns
* results in both link directions. The results are two-dimensional arrays where
* the first dimension is the index within the set-A array of one GPU ID under
* consideration, and the second dimension is the index within the set-B array
* of the other GPU ID under consideration.
*
* That is, the result arrays are *ALWAYS* to be indexed first with the set-A
* index, then with the set-B index. The B-to-A direction of results are put in
* the b2aOptimal(Read|Write)CEs. This makes it unnecessary to call the query
* twice, since the usual use case requires both directions.
*
* If a set is being compared against itself (by setting grpBCount to 0), then
* the result matrices are symmetric - it doesn't matter which index is first.
* However, the choice of indices is effectively a choice of which ID is "B" and
* which is "A" for the "a2b" and "b2a" directional results.
*
* [in] grpACount
* This member contains the number of GPU IDs stored in the gpuIdGrpA[]
* array. Must be >= 0.
* [in] grpBCount
* This member contains the number of GPU IDs stored in the gpuIdGrpB[]
* array. Can be == 0 to specify a check of group A against itself.
* [in] gpuIdGrpA
* This member contains the array of GPU IDs in "group A", each of which
* will have its P2P capabilities returned with respect to each GPU ID in
* "group B". Valid entries are contiguous, beginning with the first entry
* in the list.
* [in] gpuIdGrpB
* This member contains the array of GPU IDs in "group B", each of which
* will have its P2P capabilities returned with respect to each GPU ID in
* "group A". Valid entries are contiguous, beginning with the first entry
* in the list. May be equal to gpuIdGrpA, but best performance requires
* that the caller specifies grpBCount = 0 in this case, and ignores this.
* [out] p2pCaps
* This member returns the peer to peer capabilities discovered between the
* pairs of input GPUs between the groups, indexed by [A_index][B_index].
* Valid p2pCaps values include:
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_WRITES_SUPPORTED
* When this bit is set, peer to peer writes between subdevices owned
* by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_READS_SUPPORTED
* When this bit is set, peer to peer reads between subdevices owned
* by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PROP_SUPPORTED
* When this bit is set, peer to peer PROP between subdevices owned
* by this device are supported. This is enabled by default
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PCI_SUPPORTED
* When this bit is set, PCI is supported for all P2P between subdevices
* owned by this device.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_NVLINK_SUPPORTED
* When this bit is set, NVLINK is supported for all P2P between subdevices
* owned by this device.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_ATOMICS_SUPPORTED
* When this bit is set, peer to peer atomics between subdevices owned
* by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_LOOPBACK_SUPPORTED
* When this bit is set, peer to peer loopback is supported for subdevices
* owned by this device.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_WRITES_SUPPORTED
* When this bit is set, indirect peer to peer writes between subdevices
* owned by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_READS_SUPPORTED
* When this bit is set, indirect peer to peer reads between subdevices
* owned by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_ATOMICS_SUPPORTED
* When this bit is set, indirect peer to peer atomics between
* subdevices owned by this device are supported.
* NV0000_CTRL_SYSTEM_GET_P2P_CAPS_INDIRECT_NVLINK_SUPPORTED
* When this bit is set, indirect NVLINK is supported for subdevices
* owned by this device.
* [out] a2bOptimalReadCes
* For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink
* in the A-to-B direction.
* [out] a2bOptimalWriteCes
* For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink
* in the A-to-B direction.
* [out] b2aOptimalReadCes
* For a pair of GPUs, return mask of CEs to use for p2p reads over Nvlink
* in the B-to-A direction.
* [out] b2aOptimalWriteCes
* For a pair of GPUs, return mask of CEs to use for p2p writes over Nvlink
* in the B-to-A direction.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX (0x13a) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID" */
typedef NvU32 NV0000_CTRL_P2P_CAPS_MATRIX_ROW[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
#define NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS_MESSAGE_ID (0x3AU)
typedef struct NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS {
NvU32 grpACount;
NvU32 grpBCount;
NvU32 gpuIdGrpA[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
NvU32 gpuIdGrpB[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
NV0000_CTRL_P2P_CAPS_MATRIX_ROW p2pCaps[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
NV0000_CTRL_P2P_CAPS_MATRIX_ROW a2bOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalReadCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
NV0000_CTRL_P2P_CAPS_MATRIX_ROW b2aOptimalWriteCes[NV0000_CTRL_SYSTEM_MAX_P2P_GROUP_GPUS];
} NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS;
#define GPS_MAX_COUNTERS_PER_BLOCK 32
typedef struct NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS {
NvU32 objHndl;
NvU32 blockId;
NvU32 nextExpectedSampleTimems;
NvU32 countersReq;
NvU32 countersReturned;
NvU32 counterBlock[GPS_MAX_COUNTERS_PER_BLOCK];
} NV0000_CTRL_SYSTEM_GPS_GET_PERF_SENSOR_COUNTERS_PARAMS;
#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_PERF_SENSORS (0x12c) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2C" */
#define NV0000_CTRL_CMD_SYSTEM_GPS_GET_EXTENDED_PERF_SENSORS (0x12e) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | 0x2E" */
/*
* NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO
*
* This command returns the current host driver, host OS and
* plugin information. It is only valid when VGX is setup.
* szHostDriverVersionBuffer
* This field returns the host driver version (NV_VERSION_STRING).
* szHostVersionBuffer
* This field returns the host driver version (NV_BUILD_BRANCH_VERSION).
* szHostTitleBuffer
* This field returns the host driver title (NV_DISPLAY_DRIVER_TITLE).
* szPluginTitleBuffer
* This field returns the plugin build title (NV_DISPLAY_DRIVER_TITLE).
* szHostUnameBuffer
* This field returns the call of 'uname' on the host OS.
* iHostChangelistNumber
* This field returns the changelist value of the host driver (NV_BUILD_CHANGELIST_NUM).
* iPluginChangelistNumber
* This field returns the changelist value of the plugin (NV_BUILD_CHANGELIST_NUM).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE 256
#define NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO (0x133) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_MESSAGE_ID (0x33U)
typedef struct NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS {
char szHostDriverVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
char szHostVersionBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
char szHostTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
char szPluginTitleBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
char szHostUnameBuffer[NV0000_CTRL_CMD_SYSTEM_GET_VGX_SYSTEM_INFO_BUFFER_SIZE];
NvU32 iHostChangelistNumber;
NvU32 iPluginChangelistNumber;
} NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS
*
* This command returns the power status of the GPUs in the system, successfully attached or not because of
* insufficient power. It is supported on Kepler and up only.
* gpuCount
* This field returns the count into the following arrays.
* busNumber
* This field returns the busNumber of a GPU.
* gpuExternalPowerStatus
* This field returns the corresponding external power status:
* NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED
* NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_GPUS_POWER_STATUS (0x134) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS_MESSAGE_ID (0x34U)
typedef struct NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS {
NvU8 gpuCount;
NvU8 gpuBus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
NvU8 gpuExternalPowerStatus[NV0000_CTRL_SYSTEM_MAX_ATTACHED_GPUS];
} NV0000_CTRL_SYSTEM_GET_GPUS_POWER_STATUS_PARAMS;
/* Valid gpuExternalPowerStatus values */
#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_CONNECTED 0
#define NV0000_CTRL_SYSTEM_GPU_EXTERNAL_POWER_STATUS_NOT_CONNECTED 1
/*
* NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS
*
* This command returns the caller's API access privileges using
* this client handle.
*
* privStatus
* This parameter returns a mask of possible access privileges:
* NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_USER_FLAG
* The caller is running with elevated privileges
* NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_ROOT_HANDLE_FLAG
* Client is of NV01_ROOT class.
* NV0000_CTRL_SYSTEM_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG
* Client has PRIV bit set.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_PRIVILEGED_STATUS (0x135) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS_MESSAGE_ID (0x35U)
typedef struct NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS {
NvU8 privStatusFlags;
} NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PARAMS;
/* Valid privStatus values */
#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_USER_FLAG (0x00000001)
#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_KERNEL_HANDLE_FLAG (0x00000002)
#define NV0000_CTRL_SYSTEM_GET_PRIVILEGED_STATUS_PRIV_HANDLE_FLAG (0x00000004)
/*
* NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS
*
* The fabric manager (FM) notifies RM that fabric (system) is ready for peer to
* peer (P2P) use or still initializing the fabric. This command allows clients
* to query fabric status to allow P2P operations.
*
* Note, on systems where FM isn't used, RM just returns _SKIP.
*
* fabricStatus
* This parameter returns current fabric status:
* NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP
* NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED
* NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS
* NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INSUFFICIENT_PERMISSIONS
* NV_ERR_INVALID_PARAM_STRUCT
*/
typedef enum NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS {
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_SKIP = 1,
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_UNINITIALIZED = 2,
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_IN_PROGRESS = 3,
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS_INITIALIZED = 4,
} NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS;
#define NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS (0x136) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS_MESSAGE_ID (0x36U)
typedef struct NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS {
NV0000_CTRL_GET_SYSTEM_FABRIC_STATUS fabricStatus;
} NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS;
/*
* NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID
*
* This command is used to get a unique identifier for the instance of RM.
* The returned value will only change when the driver is reloaded. A previous
* value will never be reused on a given machine.
*
* rm_instance_id;
* The instance ID of the current RM instance
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_RM_INSTANCE_ID (0x139) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID" */
/*
* NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS
*/
#define NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS_MESSAGE_ID (0x39U)
typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS {
NV_DECLARE_ALIGNED(NvU64 rm_instance_id, 8);
} NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT
*
* This API is used to sync the external fabric management status with
* GSP-RM
*
* bExternalFabricMgmt
* Whether fabric is externally managed
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT (0x13c) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS_MESSAGE_ID (0x3CU)
typedef struct NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS {
NvBool bExternalFabricMgmt;
} NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS;
/*
* NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO
*
* This API is used to get information about the RM client
* database.
*
* clientCount [OUT]
* This field indicates the number of clients currently allocated.
*
* resourceCount [OUT]
* This field indicates the number of resources currently allocated
* across all clients.
*
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_CLIENT_DATABASE_INFO (0x13d) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS_MESSAGE_ID (0x3DU)
typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS {
NvU32 clientCount;
NV_DECLARE_ALIGNED(NvU64 resourceCount, 8);
} NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2
*
* This command returns the current driver information in
* statically sized character arrays.
*
* driverVersionBuffer
* This field returns the version (NV_VERSION_STRING).
* versionBuffer
* This field returns the version (NV_BUILD_BRANCH_VERSION).
* titleBuffer
* This field returns the title (NV_DISPLAY_DRIVER_TITLE).
* changelistNumber
* This field returns the changelist value (NV_BUILD_CHANGELIST_NUM).
* officialChangelistNumber
* This field returns the last official changelist value
* (NV_LAST_OFFICIAL_CHANGELIST_NUM).
*
* Possible status values returned are:
* NV_OK
*/
#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE 256
#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION_V2 (0x13e) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS_MESSAGE_ID (0x3EU)
typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS {
char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
NvU32 changelistNumber;
NvU32 officialChangelistNumber;
} NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS;
/* _ctrl0000system_h_ */
07070100000018000081A4000000000000000000000001663926A7000044A1000000000000000000000000000000000000004700000000nvidia-vaapi-driver-0.0.12/nvidia-include/ctrl/ctrl0000/ctrl0000unix.h/*
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl0000/ctrl0000unix.finn
//
#include "ctrl/ctrl0000/ctrl0000base.h"
#include "ctrl/ctrlxxxx.h"
/* NV01_ROOT (client) Linux control commands and parameters */
/*
* NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE
*
* This command may be used to force a cache flush for a range of virtual addresses in
* memory. Can be used for either user or kernel addresses.
*
* offset, length
* These parameters specify the offset within the memory block
* and the number of bytes to flush/invalidate
* cacheOps
* This parameter flags whether to flush, invalidate or do both.
* Possible values are:
* NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH
* NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE
* NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE
* hDevice
* This parameter is the handle to the device
* hObject
* This parameter is the handle to the memory structure being operated on.
* internalOnly
* Intended for internal use unless client is running in MODS UNIX environment,
* in which case this parameter specify the virtual address of the memory block
* to flush.
*
* Possible status values are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_COMMAND
* NV_ERR_INVALID_LIMIT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_OS_UNIX_FLUSH_USER_CACHE (0x3d02) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS {
NV_DECLARE_ALIGNED(NvU64 offset, 8);
NV_DECLARE_ALIGNED(NvU64 length, 8);
NvU32 cacheOps;
NvHandle hDevice;
NvHandle hObject;
NV_DECLARE_ALIGNED(NvU64 internalOnly, 8);
} NV0000_CTRL_OS_UNIX_FLUSH_USER_CACHE_PARAMS;
#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH (0x00000001)
#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_INVALIDATE (0x00000002)
#define NV0000_CTRL_OS_UNIX_FLAGS_USER_CACHE_FLUSH_INVALIDATE (0x00000003)
/*
* NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR
*
* This command is used to get the control file descriptor.
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV0000_CTRL_CMD_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR (0x3d04) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x4" */
typedef struct NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS {
NvS32 fd;
} NV0000_CTRL_OS_UNIX_GET_CONTROL_FILE_DESCRIPTOR_PARAMS;
typedef enum NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE {
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_NONE = 0,
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM = 1,
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE;
typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT {
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE type;
union {
struct {
NvHandle hDevice;
NvHandle hParent;
NvHandle hObject;
} rmObject;
} data;
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT;
/*
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD
*
* This command may be used to export NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE
* object to file descriptor.
*
* Note that the 'fd' parameter is an input parameter at the kernel level, but
* an output parameter for usermode RMAPI clients -- the RMAPI library will
* open a new FD automatically if a usermode RMAPI client exports an object.
*
* Kernel-mode RM clients can export an object to an FD in two steps:
* 1. User client calls this RMControl with the flag 'EMPTY_FD_TRUE' to create
* an empty FD to receive the object, then passes that FD to the kernel-mode
* RM client.
* 2. Kernel-mode RM client fills in the rest of the
* NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS as usual and calls RM to
* associate its desired RM object with the empty FD from its usermode
* client.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_PARAMETER
*/
#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (0x3d05) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS {
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */
NvS32 fd; /* IN/OUT */
NvU32 flags; /* IN */
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS;
/*
* If EMPTY_FD is TRUE, the 'fd' will be created but no object will be
* associated with it. The hDevice parameter is still required, to determine
* the correct device node on which to create the file descriptor.
* (An empty FD can then be passed to a kernel-mode driver to associate it with
* an actual object.)
*/
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD 0:0
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_FALSE (0x00000000)
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_FLAGS_EMPTY_FD_TRUE (0x00000001)
/*
* NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD
*
* This command may be used to import back
* NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE object from file descriptor.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_PARAMETER
*/
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD (0x3d06) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS_MESSAGE_ID (0x6U)
typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS {
NvS32 fd; /* IN */
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT object; /* IN */
} NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS;
/*
* NV0000_CTRL_CMD_OS_GET_GPU_INFO
*
* This command will query the OS specific info for the specified GPU.
*
* gpuId
* This parameter should specify a valid GPU ID value. If there
* is no GPU present with the specified ID, a status of
* NV_ERR_INVALID_ARGUMENT is returned.
* minorNum
* This parameter returns minor number of device node.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV0000_CTRL_CMD_OS_GET_GPU_INFO (0x3d07) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x7" */
typedef struct NV0000_CTRL_OS_GET_GPU_INFO_PARAMS {
NvU32 gpuId; /* IN */
NvU32 minorNum; /* OUT */
} NV0000_CTRL_OS_GET_GPU_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO
*
* This command will query the deviceInstance for the specified FD
* which is referencing an exported object.
*
* fd
* File descriptor parameter is referencing an exported object on a Unix system.
*
* deviceInstatnce
* This parameter returns a deviceInstance on which the object is located.
*
* maxObjects
* This parameter returns the maximum number of object handles that may be
* contained in the file descriptor.
*
* metadata
* This parameter returns the user metadata passed into the
* _EXPORT_OBJECTS_TO_FD control call.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO (0x3d08) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID" */
#define NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE 64
#define NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS {
NvS32 fd; /* IN */
NvU32 deviceInstance; /* OUT */
NvU16 maxObjects; /* OUT */
NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* OUT */
} NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST
*
* This command will re-fetch probed GPUs information and update RMAPI library's
* internal detected GPU context information accordingly. Without this, GPUs
* attached to RM after RMAPI client initialization will not be accessible and
* all RMAPI library calls will fail on them.
* Currently this is used by NVSwitch Fabric Manager in conjunction with NVSwitch
* Shared Virtualization feature where GPUs are hot-plugged to OS/RM (by Hypervisor)
* and Fabric Manager is signaled externally by the Hypervisor to initialize those GPUs.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_OPERATING_SYSTEM
*/
#define NV0000_CTRL_CMD_OS_UNIX_REFRESH_RMAPI_DEVICE_LIST (0x3d09) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | 0x9" */
/*
* This control call has been deprecated. It will be deleted soon.
* Use NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD (singular) or
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (plural) instead.
*/
#define NV0000_CTRL_CMD_OS_UNIX_CREATE_EXPORT_OBJECT_FD (0x3d0a) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE
#define NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS {
NvHandle hDevice; /* IN */
NvU16 maxObjects; /* IN */
NvU8 metadata[NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */
NvS32 fd; /* IN/OUT */
} NV0000_CTRL_OS_UNIX_CREATE_EXPORT_OBJECT_FD_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD
*
* Exports RM handles to an fd that was provided, also creates an FD if
* requested.
*
* The objects in the 'handles' array are exported into the fd
* as the range [index, index + numObjects).
*
* If index + numObjects is greater than the maxObjects value used
* to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned.
*
* If 'numObjects and 'index' overlap with a prior call, the newer call's RM object
* handles will overwrite the previously exported handles from the previous call.
* This overlapping behavior can also be used to unexport a handle by setting
* the appropriate object in 'objects' to 0.
*
* fd
* A file descriptor. If -1, a new FD will be created.
*
* hDevice
* The owning device of the objects to be exported (must be the same for
* all objects).
*
* maxObjects
* The total number of objects that the client wishes to export to the FD.
* This parameter will be honored only when the FD is getting created.
*
* metadata
* A buffer for clients to write some metadata to and pass to the importing
* client. This parameter will be honored only when the FD is getting
* created.
*
* objects
* Array of RM object handles to export to the fd.
*
* numObjects
* The number of handles the user wishes to export in this call.
*
* index
* The index into the export fd at which to start exporting the handles in
* 'objects' (for use in iterative calls).
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OUT_OF_RANGE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
*/
#define NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD (0x3d0b) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS 512
#define NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS_MESSAGE_ID (0xBU)
typedef struct NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS {
NvS32 fd; /* IN/OUT */
NvHandle hDevice; /* IN */
NvU16 maxObjects; /* IN */
NvU8 metadata[NV0000_OS_UNIX_EXPORT_OBJECT_FD_BUFFER_SIZE]; /* IN */
NvHandle objects[NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */
NvU16 numObjects; /* IN */
NvU16 index; /* IN */
} NV0000_CTRL_OS_UNIX_EXPORT_OBJECTS_TO_FD_PARAMS;
/*
* NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD
*
* This command can be used to import back RM handles
* that were exported to an fd using the
* NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECTS_TO_FD control call.
*
* If index + numObjects is greater than the maxObjects value used
* to create the file descriptor, NV_ERR_INVALID_PARAMETER is returned
* and no objects are imported.
*
* For each valid handle in the 'objects' array parameter at index 'i',
* the corresponding object handle at index ('i' + 'index') contained by
* the fd will be imported. If the object at index ('i' + 'index') has
* not been exported into the fd, no object will be imported.
*
* If any of handles contained in the 'objects' array parameter are invalid
* and the corresponding export object handle is valid,
* NV_ERR_INVALID_PARAMETER will be returned and no handles will be imported.
*
* fd
* The export fd on which to import handles out of.
*
* hParent
* The parent RM handle of which all of the exported objects will
* be duped under.
*
* objects
* An array of RM handles. The exported objects will be duped under
* these handles during the import process.
*
* objectTypes
* An array of RM handle types. The type _NONE will be returned if
* the object was not imported. Other possible object types are
* mentioned below.
*
* numObjects
* The number of valid object handles in the 'objects' array. This should
* be set to the number of objects that the client wishes to import.
*
* index
* The index into the fd in which to start importing from. For
* use in iterative calls.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OUT_OF_RANGE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_PARAMETER
*/
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECTS_FROM_FD (0x3d0c) /* finn: Evaluated from "(FINN_NV01_ROOT_OS_UNIX_INTERFACE_ID << 8) | NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID" */
//
// TODO Bump this back up to 512 after the FLA revamp is complete
//
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS 128
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_NONE 0
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_VIDMEM 1
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_SYSMEM 2
#define NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_TYPE_FABRIC 3
#define NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS {
NvS32 fd; /* IN */
NvHandle hParent; /* IN */
NvHandle objects[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* IN */
NvU8 objectTypes[NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_TO_FD_MAX_OBJECTS]; /* OUT */
NvU16 numObjects; /* IN */
NvU16 index; /* IN */
} NV0000_CTRL_OS_UNIX_IMPORT_OBJECTS_FROM_FD_PARAMS;
/* _ctrl0000unix_h_ */
07070100000019000081A4000000000000000000000001663926A70000097B000000000000000000000000000000000000003A00000000nvidia-vaapi-driver-0.0.12/nvidia-include/ctrl/ctrlxxxx.h/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2008,2013,2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlxxxx.finn
//
#include "nvtypes.h"
/* definitions shared by all CTRL interfaces */
/* Basic command format:
* cmd_class [31:16],
* cmd_reserved [15:15],
* cmd_reserved [14:14],
* cmd_category [13:8],
* cmd_index [7:0]
*/
#define NVXXXX_CTRL_CMD_CLASS 31:16
#define NVXXXX_CTRL_CMD_CATEGORY 13:8
#define NVXXXX_CTRL_CMD_INDEX 7:0
/* don't use DRF_NUM - not always available */
# define NVXXXX_CTRL_CMD(cls,cat,idx) \
(((cls) << 16) | ((0) << 15) | ((0) << 14) \
| ((cat) << 8) | ((idx) & 0xFF))
/*
* NVXXXX_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
* This command is valid for all classes.
*
* Possible status values returned are:
* NV_OK
*/
#define NVXXXX_CTRL_CMD_NULL (0x00000000)
#define NVxxxx_CTRL_LEGACY_PRIVILEGED (0xC0)
#define NVxxxx_CTRL_LEGACY_NON_PRIVILEGED (0x80)
0707010000001A000081A4000000000000000000000001663926A7000007F5000000000000000000000000000000000000003D00000000nvidia-vaapi-driver-0.0.12/nvidia-include/nv-ioctl-numbers.h/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_IOCTL_NUMBERS_H
#define NV_IOCTL_NUMBERS_H
/* NOTE: using an ioctl() number > 55 will overflow! */
#define NV_IOCTL_MAGIC 'F'
#define NV_IOCTL_BASE 200
#define NV_ESC_CARD_INFO (NV_IOCTL_BASE + 0)
#define NV_ESC_REGISTER_FD (NV_IOCTL_BASE + 1)
#define NV_ESC_ALLOC_OS_EVENT (NV_IOCTL_BASE + 6)
#define NV_ESC_FREE_OS_EVENT (NV_IOCTL_BASE + 7)
#define NV_ESC_STATUS_CODE (NV_IOCTL_BASE + 9)
#define NV_ESC_CHECK_VERSION_STR (NV_IOCTL_BASE + 10)
#define NV_ESC_IOCTL_XFER_CMD (NV_IOCTL_BASE + 11)
#define NV_ESC_ATTACH_GPUS_TO_FD (NV_IOCTL_BASE + 12)
#define NV_ESC_QUERY_DEVICE_INTR (NV_IOCTL_BASE + 13)
#define NV_ESC_SYS_PARAMS (NV_IOCTL_BASE + 14)
#define NV_ESC_EXPORT_TO_DMABUF_FD (NV_IOCTL_BASE + 17)
#endif
0707010000001B000081A4000000000000000000000001663926A70000119A000000000000000000000000000000000000003500000000nvidia-vaapi-driver-0.0.12/nvidia-include/nv-ioctl.h/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_IOCTL_H
#define NV_IOCTL_H
#include <nv-ioctl-numbers.h>
#include <nvtypes.h>
typedef struct {
NvU32 domain; /* PCI domain number */
NvU8 bus; /* PCI bus number */
NvU8 slot; /* PCI slot number */
NvU8 function; /* PCI function number */
NvU16 vendor_id; /* PCI vendor ID */
NvU16 device_id; /* PCI device ID */
} nv_pci_info_t;
/*
* ioctl()'s with parameter structures too large for the
* _IOC cmd layout use the nv_ioctl_xfer_t structure
* and the NV_ESC_IOCTL_XFER_CMD ioctl() to pass the actual
* size and user argument pointer into the RM, which
* will then copy it to/from kernel space in separate steps.
*/
typedef struct nv_ioctl_xfer
{
NvU32 cmd;
NvU32 size;
NvP64 ptr NV_ALIGN_BYTES(8);
} nv_ioctl_xfer_t;
typedef struct nv_ioctl_card_info
{
NvBool valid;
nv_pci_info_t pci_info; /* PCI config information */
NvU32 gpu_id;
NvU16 interrupt_line;
NvU64 reg_address NV_ALIGN_BYTES(8);
NvU64 reg_size NV_ALIGN_BYTES(8);
NvU64 fb_address NV_ALIGN_BYTES(8);
NvU64 fb_size NV_ALIGN_BYTES(8);
NvU32 minor_number;
NvU8 dev_name[10]; /* device names such as vmgfx[0-32] for vmkernel */
} nv_ioctl_card_info_t;
/* alloc event */
typedef struct nv_ioctl_alloc_os_event
{
NvHandle hClient;
NvHandle hDevice;
NvU32 fd;
NvU32 Status;
} nv_ioctl_alloc_os_event_t;
/* free event */
typedef struct nv_ioctl_free_os_event
{
NvHandle hClient;
NvHandle hDevice;
NvU32 fd;
NvU32 Status;
} nv_ioctl_free_os_event_t;
/* status code */
typedef struct nv_ioctl_status_code
{
NvU32 domain;
NvU8 bus;
NvU8 slot;
NvU32 status;
} nv_ioctl_status_code_t;
/* check version string */
#define NV_RM_API_VERSION_STRING_LENGTH 64
typedef struct nv_ioctl_rm_api_version
{
NvU32 cmd;
NvU32 reply;
char versionString[NV_RM_API_VERSION_STRING_LENGTH];
} nv_ioctl_rm_api_version_t;
#define NV_RM_API_VERSION_CMD_STRICT 0
#define NV_RM_API_VERSION_CMD_RELAXED '1'
#define NV_RM_API_VERSION_CMD_OVERRIDE '2'
#define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0
#define NV_RM_API_VERSION_REPLY_RECOGNIZED 1
typedef struct nv_ioctl_query_device_intr
{
NvU32 intrStatus NV_ALIGN_BYTES(4);
NvU32 status;
} nv_ioctl_query_device_intr;
/* system parameters that the kernel driver may use for configuration */
typedef struct nv_ioctl_sys_params
{
NvU64 memblock_size NV_ALIGN_BYTES(8);
} nv_ioctl_sys_params_t;
typedef struct nv_ioctl_register_fd
{
int ctl_fd;
} nv_ioctl_register_fd_t;
#define NV_DMABUF_EXPORT_MAX_HANDLES 128
typedef struct nv_ioctl_export_to_dma_buf_fd
{
int fd;
NvHandle hClient;
NvU32 totalObjects;
NvU32 numObjects;
NvU32 index;
NvU64 totalSize NV_ALIGN_BYTES(8);
NvHandle handles[NV_DMABUF_EXPORT_MAX_HANDLES];
NvU64 offsets[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
NvU64 sizes[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
NvU32 status;
} nv_ioctl_export_to_dma_buf_fd_t;
#endif
0707010000001C000081A4000000000000000000000001663926A700000AE9000000000000000000000000000000000000003600000000nvidia-vaapi-driver-0.0.12/nvidia-include/nv_escape.h/*
* SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_ESCAPE_H_INCLUDED
#define NV_ESCAPE_H_INCLUDED
#define NV_ESC_RM_ALLOC_MEMORY 0x27
#define NV_ESC_RM_ALLOC_OBJECT 0x28
#define NV_ESC_RM_FREE 0x29
#define NV_ESC_RM_CONTROL 0x2A
#define NV_ESC_RM_ALLOC 0x2B
#define NV_ESC_RM_CONFIG_GET 0x32
#define NV_ESC_RM_CONFIG_SET 0x33
#define NV_ESC_RM_DUP_OBJECT 0x34
#define NV_ESC_RM_SHARE 0x35
#define NV_ESC_RM_CONFIG_GET_EX 0x37
#define NV_ESC_RM_CONFIG_SET_EX 0x38
#define NV_ESC_RM_I2C_ACCESS 0x39
#define NV_ESC_RM_IDLE_CHANNELS 0x41
#define NV_ESC_RM_VID_HEAP_CONTROL 0x4A
#define NV_ESC_RM_ACCESS_REGISTRY 0x4D
#define NV_ESC_RM_MAP_MEMORY 0x4E
#define NV_ESC_RM_UNMAP_MEMORY 0x4F
#define NV_ESC_RM_GET_EVENT_DATA 0x52
#define NV_ESC_RM_ALLOC_CONTEXT_DMA2 0x54
#define NV_ESC_RM_ADD_VBLANK_CALLBACK 0x56
#define NV_ESC_RM_MAP_MEMORY_DMA 0x57
#define NV_ESC_RM_UNMAP_MEMORY_DMA 0x58
#define NV_ESC_RM_BIND_CONTEXT_DMA 0x59
#define NV_ESC_RM_EXPORT_OBJECT_TO_FD 0x5C
#define NV_ESC_RM_IMPORT_OBJECT_FROM_FD 0x5D
#define NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO 0x5E
#endif // NV_ESCAPE_H_INCLUDED
0707010000001D000081A4000000000000000000000001663926A700001F11000000000000000000000000000000000000003700000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvgputypes.h/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/***************************************************************************\
|* *|
|* NV GPU Types *|
|* *|
|* This header contains definitions describing NVIDIA's GPU hardware state. *|
|* *|
\***************************************************************************/
#ifndef NVGPUTYPES_INCLUDED
#define NVGPUTYPES_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/***************************************************************************\
|* NvNotification *|
\***************************************************************************/
/***** NvNotification Structure *****/
/*
* NV objects return information about method completion to clients via an
* array of notification structures in main memory.
*
* The client sets the status field to NV???_NOTIFICATION_STATUS_IN_PROGRESS.
* NV fills in the NvNotification[] data structure in the following order:
* timeStamp, otherInfo32, otherInfo16, and then status.
*/
/* memory data structures */
typedef volatile struct NvNotificationRec {
struct { /* 0000- */
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvV32 info32; /* info returned depends on method 0008-000b*/
NvV16 info16; /* info returned depends on method 000c-000d*/
NvV16 status; /* user sets bit 15, NV sets status 000e-000f*/
} NvNotification;
/***************************************************************************\
|* NvGpuSemaphore *|
\***************************************************************************/
/***** NvGpuSemaphore Structure *****/
/*
* NvGpuSemaphore objects are used by the GPU to synchronize multiple
* command-streams.
*
* Please refer to class documentation for details regarding the content of
* the data[] field.
*/
/* memory data structures */
typedef volatile struct NvGpuSemaphoreRec {
NvV32 data[2]; /* Payload/Report data 0000-0007*/
struct { /* 0008- */
NvV32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 8- f*/
} timeStamp; /* -000f*/
} NvGpuSemaphore;
/***************************************************************************\
|* NvGetReport *|
\***************************************************************************/
/*
* NV objects, starting with Kelvin, return information such as pixel counts to
* the user via the NV*_GET_REPORT method.
*
* The client fills in the "zero" field to any nonzero value and waits until it
* becomes zero. NV fills in the timeStamp, value, and zero fields.
*/
typedef volatile struct NVGetReportRec {
struct { /* 0000- */
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvU32 value; /* info returned depends on method 0008-000b*/
NvU32 zero; /* always written to zero 000c-000f*/
} NvGetReport;
/***************************************************************************\
|* NvRcNotification *|
\***************************************************************************/
/*
* NV robust channel notification information is reported to clients via
* standard NV01_EVENT objects bound to instance of the NV*_CHANNEL_DMA and
* NV*_CHANNEL_GPFIFO objects.
*/
typedef struct NvRcNotificationRec {
struct {
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
} timeStamp; /* -0007*/
NvU32 exceptLevel; /* exception level 000c-000f*/
NvU32 exceptType; /* exception type 0010-0013*/
} NvRcNotification;
/***************************************************************************\
|* NvSyncPointFence *|
\***************************************************************************/
/***** NvSyncPointFence Structure *****/
/*
* NvSyncPointFence objects represent a syncpoint event. The syncPointID
* identifies the syncpoint register and the value is the value that the
* register will contain right after the event occurs.
*
* If syncPointID contains NV_INVALID_SYNCPOINT_ID then this is an invalid
* event. This is often used to indicate an event in the past (i.e. no need to
* wait).
*
* For more info on syncpoints refer to Mobile channel and syncpoint
* documentation.
*/
typedef struct NvSyncPointFenceRec {
NvU32 syncPointID;
NvU32 value;
} NvSyncPointFence;
#define NV_INVALID_SYNCPOINT_ID ((NvU32)-1)
/***************************************************************************\
|* *|
|* 64 bit type definitions for use in interface structures. *|
|* *|
\***************************************************************************/
#if !defined(XAPIGEN) /* NvOffset is XAPIGEN builtin type, so skip typedef */
typedef NvU64 NvOffset; /* GPU address */
#endif
#define NvOffset_HI32(n) ((NvU32)(((NvU64)(n)) >> 32))
#define NvOffset_LO32(n) ((NvU32)((NvU64)(n)))
/*
* There are two types of GPU-UUIDs available:
*
* (1) a SHA-256 based 32 byte ID, formatted as a 64 character
* hexadecimal string as "GPU-%16x-%08x-%08x-%08x-%024x"; this is
* deprecated.
*
* (2) a SHA-1 based 16 byte ID, formatted as a 32 character
* hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the
* canonical format of a UUID); this is the default.
*/
#define NV_GPU_UUID_SHA1_LEN (16)
#define NV_GPU_UUID_SHA256_LEN (32)
#define NV_GPU_UUID_LEN NV_GPU_UUID_SHA1_LEN
#ifdef __cplusplus
};
#endif
#endif /* NVGPUTYPES_INCLUDED */
0707010000001E000081A4000000000000000000000001663926A70000281D000000000000000000000000000000000000003D00000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvidia-drm-ioctl.h/*
* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _UAPI_NVIDIA_DRM_IOCTL_H_
#define _UAPI_NVIDIA_DRM_IOCTL_H_
#include <drm.h>
/*
* We should do our best to keep these values constant. Any change to these will
* be backwards incompatible with client applications that might be using them
*/
#define DRM_NVIDIA_GET_CRTC_CRC32 0x00
#define DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY 0x01
#define DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY 0x02
#define DRM_NVIDIA_GET_DEV_INFO 0x03
#define DRM_NVIDIA_FENCE_SUPPORTED 0x04
#define DRM_NVIDIA_FENCE_CONTEXT_CREATE 0x05
#define DRM_NVIDIA_GEM_FENCE_ATTACH 0x06
#define DRM_NVIDIA_GET_CLIENT_CAPABILITY 0x08
#define DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY 0x09
#define DRM_NVIDIA_GEM_MAP_OFFSET 0x0a
#define DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY 0x0b
#define DRM_NVIDIA_GET_CRTC_CRC32_V2 0x0c
#define DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY 0x0d
#define DRM_NVIDIA_GEM_IDENTIFY_OBJECT 0x0e
#define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY), \
struct drm_nvidia_gem_import_nvkms_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY), \
struct drm_nvidia_gem_import_userspace_memory_params)
#define DRM_IOCTL_NVIDIA_GET_DEV_INFO \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DEV_INFO), \
struct drm_nvidia_get_dev_info_params)
#define DRM_IOCTL_NVIDIA_GET_DEV_INFO_545 \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DEV_INFO), \
struct drm_nvidia_get_dev_info_params_545)
/*
* XXX Solaris compiler has issues with DRM_IO. None of this is supported on
* Solaris anyway, so just skip it.
*
* 'warning: suggest parentheses around arithmetic in operand of |'
*/
#if defined(NV_LINUX)
#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED \
DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED)
#else
#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED 0
#endif
#define DRM_IOCTL_NVIDIA_FENCE_CONTEXT_CREATE \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_CONTEXT_CREATE), \
struct drm_nvidia_fence_context_create_params)
#define DRM_IOCTL_NVIDIA_GEM_FENCE_ATTACH \
DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_FENCE_ATTACH), \
struct drm_nvidia_gem_fence_attach_params)
#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \
struct drm_nvidia_get_client_capability_params)
#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \
struct drm_nvidia_get_crtc_crc32_params)
#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \
struct drm_nvidia_get_crtc_crc32_v2_params)
#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \
struct drm_nvidia_gem_export_nvkms_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \
struct drm_nvidia_gem_map_offset_params)
#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \
struct drm_nvidia_gem_alloc_nvkms_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \
struct drm_nvidia_gem_export_dmabuf_memory_params)
#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \
DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \
struct drm_nvidia_gem_identify_object_params)
struct drm_nvidia_gem_import_nvkms_memory_params {
uint64_t mem_size; /* IN */
uint64_t nvkms_params_ptr; /* IN */
uint64_t nvkms_params_size; /* IN */
uint32_t handle; /* OUT */
uint32_t __pad;
};
struct drm_nvidia_gem_import_userspace_memory_params {
uint64_t size; /* IN Size of memory in bytes */
uint64_t address; /* IN Virtual address of userspace memory */
uint32_t handle; /* OUT Handle to gem object */
};
struct drm_nvidia_get_dev_info_params {
uint32_t gpu_id; /* OUT */
uint32_t primary_index; /* OUT; the "card%d" value */
/* See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these */
uint32_t generic_page_kind; /* OUT */
uint32_t page_kind_generation; /* OUT */
uint32_t sector_layout; /* OUT */
};
struct drm_nvidia_get_dev_info_params_545 {
uint32_t gpu_id; /* OUT */
uint32_t primary_index; /* OUT; the "card%d" value */
uint32_t supports_alloc; /* OUT */
/* The generic_page_kind, page_kind_generation, and sector_layout
* fields are only valid if supports_alloc is true.
* See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these. */
uint32_t generic_page_kind; /* OUT */
uint32_t page_kind_generation; /* OUT */
uint32_t sector_layout; /* OUT */
uint32_t supports_sync_fd; /* OUT */
uint32_t supports_semsurf; /* OUT */
};
struct drm_nvidia_fence_context_create_params {
uint32_t handle; /* OUT GEM handle to fence context */
uint32_t index; /* IN Index of semaphore to use for fencing */
uint64_t size; /* IN Size of semaphore surface in bytes */
/* Params for importing userspace semaphore surface */
uint64_t import_mem_nvkms_params_ptr; /* IN */
uint64_t import_mem_nvkms_params_size; /* IN */
/* Params for creating software signaling event */
uint64_t event_nvkms_params_ptr; /* IN */
uint64_t event_nvkms_params_size; /* IN */
};
struct drm_nvidia_gem_fence_attach_params {
uint32_t handle; /* IN GEM handle to attach fence to */
uint32_t fence_context_handle; /* IN GEM handle to fence context on which fence is run on */
uint32_t sem_thresh; /* IN Semaphore value to reach before signal */
};
struct drm_nvidia_get_client_capability_params {
uint64_t capability; /* IN Client capability enum */
uint64_t value; /* OUT Client capability value */
};
/* Struct that stores Crc value and if it is supported by hardware */
struct drm_nvidia_crtc_crc32 {
uint32_t value; /* Read value, undefined if supported is false */
uint8_t supported; /* Supported boolean, true if readable by hardware */
};
struct drm_nvidia_crtc_crc32_v2_out {
struct drm_nvidia_crtc_crc32 compositorCrc32; /* OUT compositor hardware CRC32 value */
struct drm_nvidia_crtc_crc32 rasterGeneratorCrc32; /* OUT raster generator CRC32 value */
struct drm_nvidia_crtc_crc32 outputCrc32; /* OUT SF/SOR CRC32 value */
};
struct drm_nvidia_get_crtc_crc32_v2_params {
uint32_t crtc_id; /* IN CRTC identifier */
struct drm_nvidia_crtc_crc32_v2_out crc32; /* OUT Crc32 output structure */
};
struct drm_nvidia_get_crtc_crc32_params {
uint32_t crtc_id; /* IN CRTC identifier */
uint32_t crc32; /* OUT CRC32 value */
};
struct drm_nvidia_gem_export_nvkms_memory_params {
uint32_t handle; /* IN */
uint32_t __pad;
uint64_t nvkms_params_ptr; /* IN */
uint64_t nvkms_params_size; /* IN */
};
struct drm_nvidia_gem_map_offset_params {
uint32_t handle; /* IN Handle to gem object */
uint32_t __pad;
uint64_t offset; /* OUT Fake offset */
};
struct drm_nvidia_gem_alloc_nvkms_memory_params {
uint32_t handle; /* OUT */
uint8_t block_linear; /* IN */
uint8_t compressible; /* IN/OUT */
uint16_t __pad;
uint64_t memory_size; /* IN */
};
struct drm_nvidia_gem_export_dmabuf_memory_params {
uint32_t handle; /* IN GEM Handle*/
uint32_t __pad;
uint64_t nvkms_params_ptr; /* IN */
uint64_t nvkms_params_size; /* IN */
};
typedef enum {
NV_GEM_OBJECT_NVKMS,
NV_GEM_OBJECT_DMABUF,
NV_GEM_OBJECT_USERMEMORY,
NV_GEM_OBJECT_UNKNOWN = 0x7fffffff /* Force size of 32-bits. */
} drm_nvidia_gem_object_type;
struct drm_nvidia_gem_identify_object_params {
uint32_t handle; /* IN GEM handle*/
drm_nvidia_gem_object_type object_type; /* OUT GEM object type */
};
#endif /* _UAPI_NVIDIA_DRM_IOCTL_H_ */
0707010000001F000081A4000000000000000000000001663926A7000001A1000000000000000000000000000000000000003300000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvidia.h#ifndef NVIDIA_H_
#define NVIDIA_H_
#include <class/cl0040.h>
#include <class/cl0080.h>
#include <class/cl2080.h>
#include <nvos.h>
#include <nv_escape.h>
#include <nv-ioctl.h>
#include <nvidia-drm-ioctl.h>
#include <ctrl/ctrl0000/ctrl0000gpu.h>
#include <ctrl/ctrl0000/ctrl0000unix.h>
#include <ctrl/ctrl0000/ctrl0000system.h>
#define NVKMS_API_H
#include <nvkms-api-types.h>
#include <nvkms-kapi-private.h>
#endif
07070100000020000081A4000000000000000000000001663926A700004616000000000000000000000000000000000000003C00000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvkms-api-types.h/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#if !defined(NVKMS_API_TYPES_H)
#define NVKMS_API_TYPES_H
#include <nvtypes.h>
#include <nvmisc.h>
#include <nvlimits.h>
#define NVKMS_MAX_SUBDEVICES NV_MAX_SUBDEVICES
#define NVKMS_LEFT 0
#define NVKMS_RIGHT 1
#define NVKMS_MAX_EYES 2
#define NVKMS_MAIN_LAYER 0
#define NVKMS_OVERLAY_LAYER 1
#define NVKMS_MAX_LAYERS_PER_HEAD 8
#define NVKMS_MAX_PLANES_PER_SURFACE 3
#define NVKMS_DP_ADDRESS_STRING_LENGTH 64
#define NVKMS_DEVICE_ID_TEGRA 0x0000ffff
typedef NvU32 NvKmsDeviceHandle;
typedef NvU32 NvKmsDispHandle;
typedef NvU32 NvKmsConnectorHandle;
typedef NvU32 NvKmsSurfaceHandle;
typedef NvU32 NvKmsFrameLockHandle;
typedef NvU32 NvKmsDeferredRequestFifoHandle;
typedef NvU32 NvKmsSwapGroupHandle;
typedef NvU32 NvKmsVblankSyncObjectHandle;
struct NvKmsSize {
NvU16 width;
NvU16 height;
};
struct NvKmsPoint {
NvU16 x;
NvU16 y;
};
struct NvKmsSignedPoint {
NvS16 x;
NvS16 y;
};
struct NvKmsRect {
NvU16 x;
NvU16 y;
NvU16 width;
NvU16 height;
};
/*
* A 3x3 row-major matrix.
*
* The elements are 32-bit single-precision IEEE floating point values. The
* floating point bit pattern should be stored in NvU32s to be passed into the
* kernel.
*/
struct NvKmsMatrix {
NvU32 m[3][3];
};
typedef enum {
NVKMS_CONNECTOR_TYPE_DP = 0,
NVKMS_CONNECTOR_TYPE_VGA = 1,
NVKMS_CONNECTOR_TYPE_DVI_I = 2,
NVKMS_CONNECTOR_TYPE_DVI_D = 3,
NVKMS_CONNECTOR_TYPE_ADC = 4,
NVKMS_CONNECTOR_TYPE_LVDS = 5,
NVKMS_CONNECTOR_TYPE_HDMI = 6,
NVKMS_CONNECTOR_TYPE_USBC = 7,
NVKMS_CONNECTOR_TYPE_DSI = 8,
NVKMS_CONNECTOR_TYPE_DP_SERIALIZER = 9,
NVKMS_CONNECTOR_TYPE_UNKNOWN = 10,
NVKMS_CONNECTOR_TYPE_MAX = NVKMS_CONNECTOR_TYPE_UNKNOWN,
} NvKmsConnectorType;
static inline
const char *NvKmsConnectorTypeString(const NvKmsConnectorType connectorType)
{
switch (connectorType) {
case NVKMS_CONNECTOR_TYPE_DP: return "DP";
case NVKMS_CONNECTOR_TYPE_VGA: return "VGA";
case NVKMS_CONNECTOR_TYPE_DVI_I: return "DVI-I";
case NVKMS_CONNECTOR_TYPE_DVI_D: return "DVI-D";
case NVKMS_CONNECTOR_TYPE_ADC: return "ADC";
case NVKMS_CONNECTOR_TYPE_LVDS: return "LVDS";
case NVKMS_CONNECTOR_TYPE_HDMI: return "HDMI";
case NVKMS_CONNECTOR_TYPE_USBC: return "USB-C";
case NVKMS_CONNECTOR_TYPE_DSI: return "DSI";
case NVKMS_CONNECTOR_TYPE_DP_SERIALIZER: return "DP-SERIALIZER";
default: break;
}
return "Unknown";
}
typedef enum {
NVKMS_CONNECTOR_SIGNAL_FORMAT_VGA = 0,
NVKMS_CONNECTOR_SIGNAL_FORMAT_LVDS = 1,
NVKMS_CONNECTOR_SIGNAL_FORMAT_TMDS = 2,
NVKMS_CONNECTOR_SIGNAL_FORMAT_DP = 3,
NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI = 4,
NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN = 5,
NVKMS_CONNECTOR_SIGNAL_FORMAT_MAX =
NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN,
} NvKmsConnectorSignalFormat;
/*!
* Description of Notifiers and Semaphores (Non-isochronous (NISO) surfaces).
*
* When flipping, the client can optionally specify a notifier and/or
* a semaphore to use with the flip. The surfaces used for these
* should be registered with NVKMS to get an NvKmsSurfaceHandle.
*
* NvKmsNIsoSurface::offsetInWords indicates the starting location, in
* 32-bit words, within the surface where EVO should write the
* notifier or semaphore. Note that only the first 4096 bytes of a
* surface can be used by semaphores or notifiers; offsetInWords must
* allow for the semaphore or notifier to be written within the first
* 4096 bytes of the surface. I.e., this must be satisfied:
*
* ((offsetInWords * 4) + elementSizeInBytes) <= 4096
*
* Where elementSizeInBytes is:
*
* if NISO_FORMAT_FOUR_WORD*, elementSizeInBytes = 16
* if NISO_FORMAT_LEGACY,
* if overlay && notifier, elementSizeInBytes = 16
* else, elementSizeInBytes = 4
*
* Note that different GPUs support different semaphore and notifier formats.
* Check NvKmsAllocDeviceReply::validNIsoFormatMask to determine which are
* valid for the given device.
*
* Note also that FOUR_WORD and FOUR_WORD_NVDISPLAY are the same size, but
* FOUR_WORD uses a format compatible with display class 907[ce], and
* FOUR_WORD_NVDISPLAY uses a format compatible with c37e (actually defined by
* the NV_DISP_NOTIFIER definition in clc37d.h).
*/
enum NvKmsNIsoFormat {
NVKMS_NISO_FORMAT_LEGACY,
NVKMS_NISO_FORMAT_FOUR_WORD,
NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY,
};
enum NvKmsEventType {
NVKMS_EVENT_TYPE_DPY_CHANGED,
NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED,
NVKMS_EVENT_TYPE_DYNAMIC_DPY_DISCONNECTED,
NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED,
NVKMS_EVENT_TYPE_FRAMELOCK_ATTRIBUTE_CHANGED,
NVKMS_EVENT_TYPE_FLIP_OCCURRED,
};
typedef enum {
NV_EVO_SCALER_1TAP = 0,
NV_EVO_SCALER_2TAPS = 1,
NV_EVO_SCALER_3TAPS = 2,
NV_EVO_SCALER_5TAPS = 3,
NV_EVO_SCALER_8TAPS = 4,
NV_EVO_SCALER_TAPS_MIN = NV_EVO_SCALER_1TAP,
NV_EVO_SCALER_TAPS_MAX = NV_EVO_SCALER_8TAPS,
} NVEvoScalerTaps;
/* This structure describes the scaling bounds for a given layer. */
struct NvKmsScalingUsageBounds {
/*
* Maximum vertical downscale factor (scaled by 1024)
*
* For example, if the downscale factor is 1.5, then maxVDownscaleFactor
* would be 1.5 x 1024 = 1536.
*/
NvU16 maxVDownscaleFactor;
/*
* Maximum horizontal downscale factor (scaled by 1024)
*
* See the example above for maxVDownscaleFactor.
*/
NvU16 maxHDownscaleFactor;
/* Maximum vertical taps allowed */
NVEvoScalerTaps vTaps;
/* Whether vertical upscaling is allowed */
NvBool vUpscalingAllowed;
};
struct NvKmsUsageBounds {
struct {
NvBool usable;
struct NvKmsScalingUsageBounds scaling;
NvU64 supportedSurfaceMemoryFormats NV_ALIGN_BYTES(8);
} layer[NVKMS_MAX_LAYERS_PER_HEAD];
};
/*
* A 3x4 row-major colorspace conversion matrix.
*
* The output color C' is the CSC matrix M times the column vector
* [ R, G, B, 1 ].
*
* Each entry in the matrix is a signed 2's-complement fixed-point number with
* 3 integer bits and 16 fractional bits.
*/
struct NvKmsCscMatrix {
NvS32 m[3][4];
};
#define NVKMS_IDENTITY_CSC_MATRIX \
(struct NvKmsCscMatrix){{ \
{ 0x10000, 0, 0, 0 }, \
{ 0, 0x10000, 0, 0 }, \
{ 0, 0, 0x10000, 0 } \
}}
/*!
* A color key match bit used in the blend equations and one can select the src
* or dst Color Key when blending. Assert key bit means match, de-assert key
* bit means nomatch.
*
* The src Color Key means using the key bit from the current layer, the dst
* Color Key means using key bit from the previous layer composition stage. The
* src or dst key bit will be inherited by blended pixel for the preparation of
* next blending, as dst Color Key.
*
* src: Forward the color key match bit from the current layer pixel to next layer
* composition stage.
*
* dst: Forward the color key match bit from the previous composition stage
* pixel to next layer composition stage.
*
* disable: Forward “1” to the next layer composition stage as the color key.
*/
enum NvKmsCompositionColorKeySelect {
NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE = 0,
NVKMS_COMPOSITION_COLOR_KEY_SELECT_SRC,
NVKMS_COMPOSITION_COLOR_KEY_SELECT_DST,
};
#define NVKMS_COMPOSITION_NUMBER_OF_COLOR_KEY_SELECTS 3
/*!
* Composition modes used for surfaces in general.
* The various types of composition are:
*
* Opaque: source pixels are opaque regardless of alpha,
* and will occlude the destination pixel.
*
* Alpha blending: aka opacity, which could be specified
* for a surface in its entirety, or on a per-pixel basis.
*
* Non-premultiplied: alpha value applies to source pixel,
* and also counter-weighs the destination pixel.
* Premultiplied: alpha already applied to source pixel,
* so it only counter-weighs the destination pixel.
*
* Color keying: use a color key structure to decide
* the criteria for matching and compositing.
* (See NVColorKey below.)
*/
enum NvKmsCompositionBlendingMode {
/*!
* Modes that use no other parameters.
*/
NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE,
/*!
* Mode that ignores both per-pixel alpha provided
* by client and the surfaceAlpha, makes source pixel
* totally transparent.
*/
NVKMS_COMPOSITION_BLENDING_MODE_TRANSPARENT,
/*!
* Modes that use per-pixel alpha provided by client,
* and the surfaceAlpha must be set to 0.
*/
NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA,
NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA,
/*!
* These use both the surface-wide and per-pixel alpha values.
* surfaceAlpha is treated as numerator ranging from 0 to 255
* of a fraction whose denominator is 255.
*/
NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA,
NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA,
};
static inline NvBool
NvKmsIsCompositionModeUseAlpha(enum NvKmsCompositionBlendingMode mode)
{
return mode == NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA ||
mode == NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA ||
mode == NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA ||
mode == NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA;
}
/*!
* Abstract description of a color key.
*
* a, r, g, and b are component values in the same width as the framebuffer
* values being scanned out.
*
* match[ARGB] defines whether that component is considered when matching the
* color key -- TRUE means that the value of the corresponding component must
* match the given value for the given pixel to be considered a 'key match';
* FALSE means that the value of that component is not a key match criterion.
*/
typedef struct {
NvU16 a, r, g, b;
NvBool matchA, matchR, matchG, matchB;
} NVColorKey;
/*!
* Describes the composition parameters for the single layer.
*/
struct NvKmsCompositionParams {
enum NvKmsCompositionColorKeySelect colorKeySelect;
NVColorKey colorKey;
/*
* It is possible to assign different blending mode for match pixels and
* nomatch pixels. blendingMode[0] is used to blend a pixel with the color key
* match bit "0", and blendingMode[1] is used to blend a pixel with the color
* key match bit "1".
*
* But because of the hardware restrictions match and nomatch pixels can
* not use blending mode PREMULT_ALPHA, NON_PREMULT_ALPHA,
* PREMULT_SURFACE_ALPHA, and NON_PREMULT_SURFACE_ALPHA at once.
*/
enum NvKmsCompositionBlendingMode blendingMode[2];
NvU8 surfaceAlpha; /* Applies to all pixels of entire surface */
/*
* Defines the composition order. A smaller value moves the layer closer to
* the top (away from the background). No need to pick consecutive values,
* requirements are that the value should be different for each of the
* layers owned by the head and the value for the main layer should be
* the greatest one.
*
* Cursor always remains at the top of all other layers, this parameter
* has no effect on cursor. NVKMS assigns default depth to each of the
* supported layers, by default depth of the layer is calculated as
* (NVKMS_MAX_LAYERS_PER_HEAD - index of the layer). If depth is set to
* '0' then default depth value will get used.
*/
NvU8 depth;
};
/*!
* Describes the composition capabilities supported by the hardware for
* cursor or layer. It describes supported the color key selects and for each
* of the supported color key selects it describes supported blending modes
* for match and nomatch pixles.
*/
struct NvKmsCompositionCapabilities {
struct {
/*
* A bitmask of the supported blending modes for match and nomatch
* pixels. It should be the bitwise 'or' of one or more
* NVBIT(NVKMS_COMPOSITION_BLENDING_MODE_*) values.
*/
NvU32 supportedBlendModes[2];
} colorKeySelect[NVKMS_COMPOSITION_NUMBER_OF_COLOR_KEY_SELECTS];
/*
* A bitmask of the supported color key selects.
*
* It should be the bitwise 'or' of one or more
* NVBIT(NVKMS_COMPOSITION_COLOR_KEY_SELECT_*)
* values.
*/
NvU32 supportedColorKeySelects;
};
struct NvKmsLayerCapabilities {
/*!
* Whether Layer supports the window mode. If window mode is supported,
* then clients can set the layer's dimensions so that they're smaller than
* the viewport, and can also change the output position of the layer to a
* non-(0, 0) position.
*
* NOTE: Dimension changes are currently unsupported for the main layer,
* and output position changes for the main layer are currently only
* supported via IOCTL_SET_LAYER_POSITION but not via flips. Support for
* these is coming soon, via changes to flip code.
*/
NvBool supportsWindowMode :1;
/*!
* Whether layer supports HDR pipe.
*/
NvBool supportsHDR :1;
/*!
* Describes the supported Color Key selects and blending modes for
* match and nomatch layer pixels.
*/
struct NvKmsCompositionCapabilities composition;
/*!
* Which NvKmsSurfaceMemoryFormat enum values are supported by the NVKMS
* device on the given scanout surface layer.
*
* Iff a particular enum NvKmsSurfaceMemoryFormat 'value' is supported,
* then (1 << value) will be set in the appropriate bitmask.
*
* Note that these bitmasks just report the static SW/HW capabilities,
* and are a superset of the formats that IMP may allow. Clients are
* still expected to honor the NvKmsUsageBounds for each head.
*/
NvU64 supportedSurfaceMemoryFormats NV_ALIGN_BYTES(8);
};
/*!
* Surface layouts.
*
* BlockLinear is the NVIDIA GPU native tiling format, arranging pixels into
* blocks or tiles for better locality during common GPU operations.
*
* Pitch is the naive "linear" surface layout with pixels laid out sequentially
* in memory line-by-line, optionally with some padding at the end of each line
* for alignment purposes.
*/
enum NvKmsSurfaceMemoryLayout {
NvKmsSurfaceMemoryLayoutBlockLinear = 0,
NvKmsSurfaceMemoryLayoutPitch = 1,
};
static inline const char *NvKmsSurfaceMemoryLayoutToString(
enum NvKmsSurfaceMemoryLayout layout)
{
switch (layout) {
default:
return "Unknown";
case NvKmsSurfaceMemoryLayoutBlockLinear:
return "BlockLinear";
case NvKmsSurfaceMemoryLayoutPitch:
return "Pitch";
}
}
typedef enum {
MUX_STATE_GET = 0,
MUX_STATE_INTEGRATED = 1,
MUX_STATE_DISCRETE = 2,
MUX_STATE_UNKNOWN = 3,
} NvMuxState;
enum NvKmsRotation {
NVKMS_ROTATION_0 = 0,
NVKMS_ROTATION_90 = 1,
NVKMS_ROTATION_180 = 2,
NVKMS_ROTATION_270 = 3,
NVKMS_ROTATION_MIN = NVKMS_ROTATION_0,
NVKMS_ROTATION_MAX = NVKMS_ROTATION_270,
};
struct NvKmsRRParams {
enum NvKmsRotation rotation;
NvBool reflectionX;
NvBool reflectionY;
};
/*!
* Convert each possible NvKmsRRParams to a unique integer [0..15],
* so that we can describe possible NvKmsRRParams with an NvU16 bitmask.
*
* E.g.
* rotation = 0, reflectionX = F, reflectionY = F == 0|0|0 == 0
* ...
* rotation = 270, reflectionX = T, reflectionY = T == 3|4|8 == 15
*/
static inline NvU8 NvKmsRRParamsToCapBit(const struct NvKmsRRParams *rrParams)
{
NvU8 bitPosition = (NvU8)rrParams->rotation;
if (rrParams->reflectionX) {
bitPosition |= NVBIT(2);
}
if (rrParams->reflectionY) {
bitPosition |= NVBIT(3);
}
return bitPosition;
}
/*
* NVKMS_MEMORY_ISO is used to tag surface memory that will be accessed via
* display's isochronous interface. Examples of this type of memory are pixel
* data and LUT entries.
*
* NVKMS_MEMORY_NISO is used to tag surface memory that will be accessed via
* display's non-isochronous interface. Examples of this type of memory are
* semaphores and notifiers.
*/
typedef enum {
NVKMS_MEMORY_ISO = 0,
NVKMS_MEMORY_NISO = 1,
} NvKmsMemoryIsoType;
typedef struct {
NvBool coherent;
NvBool noncoherent;
} NvKmsDispIOCoherencyModes;
#endif /* NVKMS_API_TYPES_H */
07070100000021000081A4000000000000000000000001663926A700020A1B000000000000000000000000000000000000003600000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvkms-api.h/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#if !defined(NVKMS_API_H)
#define NVKMS_API_H
/*
* NVKMS API
*
*
* All file operations described in this header file go through a
* single device file that has system-wide scope. The individual
* ioctl request data structures specify the objects to which the
* request is targeted.
*
*
* OBJECTS
*
* The NVKMS API is organized into several objects:
*
* - A device, which corresponds to an RM device. This can either be
* a single GPU, or multiple GPUs linked into SLI. Each GPU is
* called a "subdevice". The subdevices used by an NVKMS device are
* reported in NvKmsAllocDeviceReply::subDeviceMask.
*
* A device is specified by a deviceHandle, returned by
* NVKMS_IOCTL_ALLOC_DEVICE.
*
* - A disp, which represents an individually programmable display
* engine of a GPU. In SLI Mosaic, there is one disp per physical
* GPU. In all other configurations there is one disp for the
* entire device. A disp is specified by a (deviceHandle,
* dispHandle) duple. A dispHandle is only unique within a single
* device: multiple devices may have disps with the same dispHandle
* value.
*
* A disp contains one or more subdevices, as reported by
* NvKmsQueryDispReply::subDeviceMask. A disp will only have
* multiple subdevices in cases where the device only has a single
* disp. Any subdevice specified in
* NvKmsQueryDispReply::subDeviceMask will also be in
* NvKmsAllocDeviceReply::subDeviceMask.
*
* - A connector, which represents an electrical connection to the
* GPU. E.g., a physical DVI-I connector has two NVKMS connector
* objects (a VGA NVKMS connector and a TMDS NVKMS connector).
* However, a physical DisplayPort connector has one NVKMS connector
* object, even if there is a tree of DisplayPort1.2 Multistream
* monitors connected to it.
*
* Connectors are associated with a specific disp. A connector is
* specified by a (deviceHandle, dispHandle, connectorHandle)
* triplet. A connectorHandle is only unique within a single disp:
* multiple disps may have connectors with the same connectorHandle
* value.
*
* - A dpy, which represents a connection of a display device to the
* system. Multiple dpys can map to the same connector in the case
* of DisplayPort1.2 MultiStream. A dpy is specified by a
* (deviceHandle, dispHandle, dpyId) triplet. A dpyId is only
* unique within a single disp: multiple disps may have dpys with
* the same dpyId value.
*
* - A surface, which represents memory to be scanned out. Surfaces
* should be allocated by resman, and then registered and
* unregistered with NVKMS. The NvKmsSurfaceHandle value of 0 is
* reserved to mean no surface.
*
* NVKMS clients should treat the device, disp, connector, and surface
* handles as opaque values. They are specific to the file descriptor
* through which a client allocated and queried them. Dpys should
* also be treated as opaque, though they can be passed between
* clients.
*
* NVKMS clients initialize NVKMS by allocating an NVKMS device. The
* device can either be a single GPU, or an SLI group. It is expected
* that the client has already attached/linked the GPUs through
* resman and created a resman device.
*
* NVKMS device allocation returns a device handle, the disp handles,
* and capabilities of the device.
*
*
* MODE VALIDATION
*
* When a client requests to set a mode via NVKMS_IOCTL_SET_MODE,
* NVKMS will validate the mode at that point in time, honoring the
* NvKmsModeValidationParams specified as part of the request.
*
* Clients can use NVKMS_IOCTL_VALIDATE_MODE to test if a mode is valid.
*
* Clients can use NVKMS_IOCTL_VALIDATE_MODE_INDEX to get the list of
* modes that NVKMS currently considers valid for the dpy (modes from
* the EDID, etc).
*
* IMPLEMENTATION NOTE: the same mode validation common code will be
* used in each of NVKMS_IOCTL_SET_MODE, NVKMS_IOCTL_VALIDATE_MODE,
* and NVKMS_IOCTL_VALIDATE_MODE_INDEX, but NVKMS won't generally maintain
* a "mode pool" with an exhaustive list of the allowable modes for a
* dpy.
*
*
* DYNAMIC DPY HANDLING
*
* Dynamic dpys (namely, DisplayPort multistream dpys) share the NVDpyId
* namespace with non-dynamic dpys on the same disp. However, dynamic dpys will
* not be listed in NvKmsQueryDispReply::validDpys. Instead, dynamic dpys are
* added and removed from the system dynamically.
*
* When a dynamic dpy is first connected, NVKMS will allocate a new NVDpyId for
* it and generate an NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED event. When the
* dynamic dpy is disconnected, NVKMS will generate an
* NVKMS_EVENT_TYPE_DYNAMIC_DPY_DISCONNECTED event. Whether the corresponding
* NVDpyId is immediately freed and made available for subsequent dynamic dpys
* depends on client behavior.
*
* Clients may require that a dynamic NVDpyId persist even after the dynamic dpy
* is disconnected. Clients who require this can use
* NVKMS_IOCTL_DECLARE_DYNAMIC_DPY_INTEREST. NVKMS will retain the NVDpyId
* until the dynamic dpy is disconnected and there are no clients who have
* declared "interest" on the particular dynamic dpy. While the NVDpyId
* persists, it will be used for any monitor that is connected at the same
* dynamic dpy address (i.e., port address, in the case of DP MST).
*
*
* FILE DESCRIPTOR HANDLING
*
* With the exception of NVDpyIds, all handles should be assumed to be
* specific to the current file descriptor on which the ioctls are
* performed.
*
* Multiple devices can be allocated on the same file descriptor.
* E.g., to drive the display of multiple GPUs.
*
* If a file descriptor is closed prematurely, either explicitly by
* the client or implicitly by the operating system because the client
* process was terminated, NVKMS will perform an
* NVKMS_IOCTL_FREE_DEVICE for any devices currently allocated by the
* client on the closed file descriptor.
*
* NVKMS file descriptors are normally used as the first argument of
* ioctl(2). However, NVKMS file descriptors are also used for
* granting surfaces (see NVKMS_IOCTL_GRANT_SURFACE) or permissions
* (see NVKMS_IOCTL_GRANT_PERMISSIONS). Any given NVKMS file
* descriptor can only be used for one of these uses.
*
* QUESTIONS:
*
* - Is there any reason for errors to be returned through a status field
* in the Param structures, rather than the ioctl(2) return value?
*
* - Is it too asymmetric that NVKMS_IOCTL_SET_MODE can set a
* mode across heads/disps, but other requests (e.g.,
* NVKMS_IOCTL_SET_CURSOR_IMAGE) operate on a single head?
*
*
* IOCTL PARAMETER ORGANIZATION
*
* For table-driven processing of ioctls, it is useful for all ioctl
* parameters to follow the same convention:
*
* struct NvKmsFooRequest {
* (...)
* };
*
* struct NvKmsFooReply {
* (...)
* };
*
* struct NvKmsFooParams {
* struct NvKmsFooRequest request; //! in
* struct NvKmsFooReply reply; //! out
* };
*
* I.e., all ioctl parameter structures NvKmsFooParams should have
* "request" and "reply" fields, with types "struct NvKmsFooRequest"
* and "struct NvKmsFooReply". C doesn't technically support empty
* structures, so the convention is to place a "padding" NvU32 in
* request or reply structures that would otherwise be empty.
*/
#include "nvtypes.h"
#include "nvlimits.h"
#include "nv_dpy_id.h"
#include "nv_mode_timings.h"
#include "nvkms-api-types.h"
#include "nvgputypes.h" /* NvGpuSemaphore */
#include "nvkms-format.h"
/*
* The NVKMS ioctl commands. See the ioctl parameter declarations
* later in this header file for an explanation of each ioctl command.
*/
enum NvKmsIoctlCommand {
NVKMS_IOCTL_ALLOC_DEVICE,
NVKMS_IOCTL_FREE_DEVICE,
NVKMS_IOCTL_QUERY_DISP,
NVKMS_IOCTL_QUERY_CONNECTOR_STATIC_DATA,
NVKMS_IOCTL_QUERY_CONNECTOR_DYNAMIC_DATA,
NVKMS_IOCTL_QUERY_DPY_STATIC_DATA,
NVKMS_IOCTL_QUERY_DPY_DYNAMIC_DATA,
NVKMS_IOCTL_VALIDATE_MODE_INDEX,
NVKMS_IOCTL_VALIDATE_MODE,
NVKMS_IOCTL_SET_MODE,
NVKMS_IOCTL_SET_CURSOR_IMAGE,
NVKMS_IOCTL_MOVE_CURSOR,
NVKMS_IOCTL_SET_LUT,
NVKMS_IOCTL_IDLE_BASE_CHANNEL,
NVKMS_IOCTL_FLIP,
NVKMS_IOCTL_DECLARE_DYNAMIC_DPY_INTEREST,
NVKMS_IOCTL_REGISTER_SURFACE,
NVKMS_IOCTL_UNREGISTER_SURFACE,
NVKMS_IOCTL_GRANT_SURFACE,
NVKMS_IOCTL_ACQUIRE_SURFACE,
NVKMS_IOCTL_RELEASE_SURFACE,
NVKMS_IOCTL_SET_DPY_ATTRIBUTE,
NVKMS_IOCTL_GET_DPY_ATTRIBUTE,
NVKMS_IOCTL_GET_DPY_ATTRIBUTE_VALID_VALUES,
NVKMS_IOCTL_SET_DISP_ATTRIBUTE,
NVKMS_IOCTL_GET_DISP_ATTRIBUTE,
NVKMS_IOCTL_GET_DISP_ATTRIBUTE_VALID_VALUES,
NVKMS_IOCTL_QUERY_FRAMELOCK,
NVKMS_IOCTL_SET_FRAMELOCK_ATTRIBUTE,
NVKMS_IOCTL_GET_FRAMELOCK_ATTRIBUTE,
NVKMS_IOCTL_GET_FRAMELOCK_ATTRIBUTE_VALID_VALUES,
NVKMS_IOCTL_GET_NEXT_EVENT,
NVKMS_IOCTL_DECLARE_EVENT_INTEREST,
NVKMS_IOCTL_CLEAR_UNICAST_EVENT,
NVKMS_IOCTL_GET_3DVISION_DONGLE_PARAM_BYTES,
NVKMS_IOCTL_SET_3DVISION_AEGIS_PARAMS,
NVKMS_IOCTL_SET_LAYER_POSITION,
NVKMS_IOCTL_GRAB_OWNERSHIP,
NVKMS_IOCTL_RELEASE_OWNERSHIP,
NVKMS_IOCTL_GRANT_PERMISSIONS,
NVKMS_IOCTL_ACQUIRE_PERMISSIONS,
NVKMS_IOCTL_REVOKE_PERMISSIONS,
NVKMS_IOCTL_QUERY_DPY_CRC32,
NVKMS_IOCTL_REGISTER_DEFERRED_REQUEST_FIFO,
NVKMS_IOCTL_UNREGISTER_DEFERRED_REQUEST_FIFO,
NVKMS_IOCTL_ALLOC_SWAP_GROUP,
NVKMS_IOCTL_FREE_SWAP_GROUP,
NVKMS_IOCTL_JOIN_SWAP_GROUP,
NVKMS_IOCTL_LEAVE_SWAP_GROUP,
NVKMS_IOCTL_SET_SWAP_GROUP_CLIP_LIST,
NVKMS_IOCTL_GRANT_SWAP_GROUP,
NVKMS_IOCTL_ACQUIRE_SWAP_GROUP,
NVKMS_IOCTL_RELEASE_SWAP_GROUP,
NVKMS_IOCTL_SWITCH_MUX,
NVKMS_IOCTL_GET_MUX_STATE,
NVKMS_IOCTL_EXPORT_VRR_SEMAPHORE_SURFACE,
NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT,
NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT,
};
#define NVKMS_NVIDIA_DRIVER_VERSION_STRING_LENGTH 32
#define NVKMS_MAX_CONNECTORS_PER_DISP 16
#define NVKMS_MAX_HEADS_PER_DISP 4
#define NVKMS_MAX_GPUS_PER_FRAMELOCK 4
#define NVKMS_MAX_DEVICE_REGISTRY_KEYS 16
#define NVKMS_MAX_DEVICE_REGISTRY_KEYNAME_LEN 32
#define NVKMS_MAX_VBLANK_SYNC_OBJECTS_PER_HEAD 6
/*
* There can be at most one SwapGroup per-head, per-disp (and,
* in the extreme, there is one disp per-GPU).
*/
#define NVKMS_MAX_SWAPGROUPS (NVKMS_MAX_HEADS_PER_DISP * NV_MAX_DEVICES)
#define NVKMS_MAX_VALID_SYNC_RANGES 8
#define NVKMS_DPY_NAME_SIZE 128
#define NVKMS_GUID_SIZE 16
#define NVKMS_3DVISION_DONGLE_PARAM_BYTES 20
#define NVKMS_GPU_STRING_SIZE 80
#define NVKMS_LOG2_LUT_ARRAY_SIZE 10
#define NVKMS_LUT_ARRAY_SIZE (1 << NVKMS_LOG2_LUT_ARRAY_SIZE)
#define NVKMS_VRR_SEMAPHORE_SURFACE_SIZE 1024
/*
* The GUID string has the form:
* XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX
* Two Xs per byte, plus four dashes and a NUL byte.
*/
#define NVKMS_GUID_STRING_SIZE ((NVKMS_GUID_SIZE * 2) + 5)
#define NVKMS_MODE_VALIDATION_MAX_INFO_STRING_LENGTH 2048
#define NVKMS_EDID_INFO_STRING_LENGTH (32 * 1024)
/*!
* A base EDID is 128 bytes, with 128 bytes per extension block. 2048
* should be large enough for any EDID we see.
*/
#define NVKMS_EDID_BUFFER_SIZE 2048
/*!
* Description of modetimings.
*
* YUV420 modes require special care since some GPUs do not support YUV420
* scanout in hardware. When timings::yuv420Mode is NV_YUV420_SW, NVKMS will
* set a mode with horizontal values that are half of what are described in
* NvKmsMode, and not enable any color space conversion. When clients allocate
* a surface and populate it with content, the region of interest within the
* surface should be half the width of the NvKmsMode, and the surface content
* should be RGB->YUV color space converted, and decimated from 4:4:4 to 4:2:0.
*
* The NvKmsMode and viewPortOut, specified by the NVKMS client,
* should be in "full" horizontal space, but the surface and
* viewPortIn should be in "half" horizontal space.
*/
struct NvKmsMode {
NvModeTimings timings;
char name[32];
};
/*!
* Mode validation override bit flags, for use in
* NvKmsModeValidationParams::overrides.
*/
enum NvKmsModeValidationOverrides {
NVKMS_MODE_VALIDATION_NO_MAX_PCLK_CHECK = (1 << 0),
NVKMS_MODE_VALIDATION_NO_EDID_MAX_PCLK_CHECK = (1 << 1),
NVKMS_MODE_VALIDATION_NO_HORIZ_SYNC_CHECK = (1 << 2),
NVKMS_MODE_VALIDATION_NO_VERT_REFRESH_CHECK = (1 << 3),
NVKMS_MODE_VALIDATION_NO_EDID_DFP_MAX_SIZE_CHECK = (1 << 4),
NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK = (1 << 5),
NVKMS_MODE_VALIDATION_OBEY_EDID_CONTRADICTIONS = (1 << 6),
NVKMS_MODE_VALIDATION_NO_TOTAL_SIZE_CHECK = (1 << 7),
NVKMS_MODE_VALIDATION_NO_DUAL_LINK_DVI_CHECK = (1 << 8),
NVKMS_MODE_VALIDATION_NO_DISPLAYPORT_BANDWIDTH_CHECK = (1 << 9),
NVKMS_MODE_VALIDATION_ALLOW_NON_3DVISION_MODES = (1 << 10),
NVKMS_MODE_VALIDATION_ALLOW_NON_EDID_MODES = (1 << 11),
NVKMS_MODE_VALIDATION_ALLOW_NON_HDMI3D_MODES = (1 << 12),
NVKMS_MODE_VALIDATION_NO_MAX_SIZE_CHECK = (1 << 13),
NVKMS_MODE_VALIDATION_NO_HDMI2_CHECK = (1 << 14),
NVKMS_MODE_VALIDATION_NO_RRX1K_CHECK = (1 << 15),
NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS = (1 << 16),
NVKMS_MODE_VALIDATION_ALLOW_DP_INTERLACED = (1 << 17),
NVKMS_MODE_VALIDATION_NO_INTERLACED_MODES = (1 << 18),
};
/*!
* Frequency information used during mode validation (for HorizSync
* and VertRefresh) can come from several possible sources. NVKMS
* selects the frequency information by prioritizing the input sources
* and then reports the selected source.
*
* Without client input, NVKMS will use frequency ranges from the
* EDID, if available. If there is no EDID, NVKMS will fall back to
* builtin conservative defaults.
*
* The client can specify frequency ranges that are used instead of
* anything in the EDID (_CLIENT_BEFORE_EDID), or frequency ranges
* that are used only if no EDID-reported ranges are available
* (_CLIENT_AFTER_EDID).
*/
enum NvKmsModeValidationFrequencyRangesSource {
NVKMS_MODE_VALIDATION_FREQUENCY_RANGE_SOURCE_NONE = 0,
NVKMS_MODE_VALIDATION_FREQUENCY_RANGE_SOURCE_CLIENT_BEFORE_EDID = 1,
NVKMS_MODE_VALIDATION_FREQUENCY_RANGE_SOURCE_EDID = 2,
NVKMS_MODE_VALIDATION_FREQUENCY_RANGE_SOURCE_CLIENT_AFTER_EDID = 3,
NVKMS_MODE_VALIDATION_FREQUENCY_RANGE_SOURCE_CONSERVATIVE_DEFAULTS = 4,
};
/*!
* Mode validation parameters.
*/
struct NvKmsModeValidationFrequencyRanges {
enum NvKmsModeValidationFrequencyRangesSource source;
NvU32 numRanges;
struct {
NvU32 high;
NvU32 low;
} range[NVKMS_MAX_VALID_SYNC_RANGES];
};
struct NvKmsModeValidationValidSyncs {
/*! If TRUE, ignore frequency information from the EDID. */
NvBool ignoreEdidSource;
/*! values are in Hz */
struct NvKmsModeValidationFrequencyRanges horizSyncHz;
/*! values are in 1/1000 Hz */
struct NvKmsModeValidationFrequencyRanges vertRefreshHz1k;
};
enum NvKmsStereoMode {
NVKMS_STEREO_DISABLED = 0,
NVKMS_STEREO_NVIDIA_3D_VISION,
NVKMS_STEREO_NVIDIA_3D_VISION_PRO,
NVKMS_STEREO_HDMI_3D,
NVKMS_STEREO_OTHER,
};
struct NvKmsModeValidationParams {
NvBool verboseModeValidation;
NvBool moreVerboseModeValidation;
/*!
* Normally, if a mode supports both YUV 4:2:0 and RGB 4:4:4,
* NVKMS will prefer RGB 4:4:4 if both the monitor and the GPU
* support it. Use preferYUV420 to override that preference.
*/
NvBool preferYUV420;
enum NvKmsStereoMode stereoMode;
NvU32 overrides;
struct NvKmsModeValidationValidSyncs validSyncs;
/*!
* Normally, NVKMS will determine on its own whether to use Display
* Stream Compression (DSC). Use forceDsc to force NVKMS to use DSC,
* when the GPU supports it.
*/
NvBool forceDsc;
/*!
* When enabled, Display Stream Compression (DSC) has an
* associated bits/pixel rate, which NVKMS normally computes.
* Use dscOverrideBitsPerPixelX16 to override the DSC bits/pixel rate.
* This is in units of 1/16 of a bit per pixel.
*
* This target bits/pixel rate should be >= 8.0 and <= 32.0, i.e. the valid
* bits/pixel values are members of the sequence 8.0, 8.0625, 8.125, ...,
* 31.9375, 32.0. You can convert bits/pixel value to
* the dscOverrideBitsPerPixelX16 as follow:
*
* +------------------+--------------------------------------------+
* | bits_per_pixel | dscBitsPerPixelX16 = bits_per_pixel * 16 |
* +------------------+--------------------------------------------+
* | 8.0 | 128 |
* | 8.0625 | 129 |
* | . | . |
* | . | . |
* | . | . |
* | 31.9375 | 511 |
* | 32.0 | 512 |
* +------------------+--------------------------------------------+
*
* If the specified dscOverrideBitsPerPixelX16 is out of range,
* then mode validation may fail.
*
* When dscOverrideBitsPerPixelX16 is 0, NVKMS compute the rate itself.
*/
NvU32 dscOverrideBitsPerPixelX16;
};
/*!
* The list of pixelShift modes.
*/
enum NvKmsPixelShiftMode {
NVKMS_PIXEL_SHIFT_NONE = 0,
NVKMS_PIXEL_SHIFT_4K_TOP_LEFT,
NVKMS_PIXEL_SHIFT_4K_BOTTOM_RIGHT,
NVKMS_PIXEL_SHIFT_8K,
};
/*!
* The available resampling methods used when viewport scaling is requested.
*/
enum NvKmsResamplingMethod {
NVKMS_RESAMPLING_METHOD_BILINEAR = 0,
NVKMS_RESAMPLING_METHOD_BICUBIC_TRIANGULAR,
NVKMS_RESAMPLING_METHOD_BICUBIC_BELL_SHAPED,
NVKMS_RESAMPLING_METHOD_BICUBIC_BSPLINE,
NVKMS_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_TRIANGULAR,
NVKMS_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BELL_SHAPED,
NVKMS_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BSPLINE,
NVKMS_RESAMPLING_METHOD_NEAREST,
NVKMS_RESAMPLING_METHOD_DEFAULT = NVKMS_RESAMPLING_METHOD_BILINEAR,
};
enum NvKmsWarpMeshDataType {
NVKMS_WARP_MESH_DATA_TYPE_TRIANGLES_XYUVRQ,
NVKMS_WARP_MESH_DATA_TYPE_TRIANGLE_STRIP_XYUVRQ,
};
/*!
* Description of a cursor image on a single head; this is used by any
* NVKMS request that needs to specify the cursor image.
*/
struct NvKmsSetCursorImageCommonParams {
/*! The surface to display in the cursor. */
NvKmsSurfaceHandle surfaceHandle[NVKMS_MAX_EYES];
/*!
* The cursor composition parameters gets read and applied only if the
* specified cursor surface is not null.
*/
struct NvKmsCompositionParams cursorCompParams;
};
/*!
* Description of the cursor position on a single head; this is used
* by any NVKMS request that needs to specify the cursor position.
*
* x,y are relative to the current viewPortIn configured on the head.
*/
struct NvKmsMoveCursorCommonParams {
NvS16 x; /*! in */
NvS16 y; /*! in */
};
/*!
* Per-component arrays of NvU16s describing the LUT; used for both the input
* LUT and output LUT.
*/
struct NvKmsLutRamps {
NvU16 red[NVKMS_LUT_ARRAY_SIZE]; /*! in */
NvU16 green[NVKMS_LUT_ARRAY_SIZE]; /*! in */
NvU16 blue[NVKMS_LUT_ARRAY_SIZE]; /*! in */
};
/*!
* Description of the main layer LUT on a single head; this is used by any NVKMS
* request that needs to specify the LUT.
*/
struct NvKmsSetInputLutParams {
NvBool specified;
NvU32 depth; /*! used bits per pixel (8, 15, 16, 24, 30) */
/*!
* The first and last elements (inclusive) in the color arrays to
* use. Valid values are in the range [0,N], where N is a
* function of depth:
*
* Depth N
* 8 256
* 15 32
* 16 64
* 24 256
* 30 1024
*
* 'start' is the first element in the color arrays to use.
*/
NvU32 start;
/*!
* 'end' is the last element (inclusive) in the color arrays to
* use. If end == 0, this command will disable the HW LUT for
* this head.
*
* The other fields in this structure, besides 'specified', are ignored if
* end == 0.
*/
NvU32 end;
/*!
* Pointer to struct NvKmsLutRamps describing the LUT.
* Elements [start,end] will be used.
*
* Each entry in the input LUT has valid values in the range [0, 65535].
* However, on pre-Turing GPUs only 11 bits are significant; NVKMS will
* convert values in this range into the appropriate internal format.
*
* Use nvKmsPointerToNvU64() to assign pRamps.
*/
NvU64 pRamps NV_ALIGN_BYTES(8);
};
/*!
* Description of the output LUT on a single head; this is used by any NVKMS
* request that needs to specify the LUT.
*
* Unlike the input LUT:
* - specifying the output LUT updates all values at once.
*
* Each entry in the output LUT has valid values in the range [0, 65535].
* However, only 11 bits are significant; NVKMS will convert values in this
* range into the appropriate internal format.
*/
struct NvKmsSetOutputLutParams {
NvBool specified;
NvBool enabled;
/*!
* Pointer to struct NvKmsLutRamps containing the actual LUT data, if
* required.
* Use nvKmsPointerToNvU64() to assign pRamps.
*/
NvU64 pRamps NV_ALIGN_BYTES(8);
};
/*!
* Description of the LUT on a single head; this is used by any NVKMS
* request that needs to specify the LUT.
*/
struct NvKmsSetLutCommonParams {
struct NvKmsSetInputLutParams input;
struct NvKmsSetOutputLutParams output;
NvBool synchronous; /*! block until the LUT update is complete */
};
struct NvKmsNIsoSurface {
NvKmsSurfaceHandle surfaceHandle;
enum NvKmsNIsoFormat format;
NvU16 offsetInWords;
};
struct NvKmsCompletionNotifierDescription {
struct NvKmsNIsoSurface surface;
NvBool awaken;
};
struct NvKmsSemaphore {
struct NvKmsNIsoSurface surface;
NvU32 value;
};
enum NvKmsSyncptType {
NVKMS_SYNCPT_TYPE_NONE,
NVKMS_SYNCPT_TYPE_RAW,
NVKMS_SYNCPT_TYPE_FD,
};
struct NvKmsSyncpt {
enum NvKmsSyncptType type;
union {
int fd;
struct {
NvU32 id;
NvU32 value;
} raw;
} u;
};
struct NvKmsChannelSyncObjects {
/*
* If useSyncpt is set to FALSE, clients can provide an acquisition and/or
* release semaphore via the 'syncObjects.semaphores' struct.
*
* If NvKmsAllocDeviceReply::supportsIndependentAcqRelSemaphore is
* FALSE, then 'syncObjects.semaphores.acquire.surface' must be the same
* as 'syncObjects.semaphores.release.surface'. In other words, the same
* exact semaphore surface must be used for both acquire and release.
*
* If NvKmsAllocDeviceReply::supportsIndependentAcqRelSemaphore is
* TRUE, then the client is allowed to provide different semaphore
* surfaces for acquire and release.
*
* If useSyncpt is set to TRUE, clients can provide a pre-syncpt that they
* want the display engine to wait on before scanning out from the given
* buffer, and can specify that they want NVKMS to return a post-syncpt
* that they can wait on, via the 'syncObjects.syncpts' struct.
*
* The post-syncpt that NVKMS returns will be signaled once the
* buffer that was activated by this flip is displaced. As a typical
* example:
* - Client flips buffer A, and requests a post-syncpt PS.
* - Buffer A becomes active at the next frame boundary, and display
* starts scanning out buffer A.
* - Client flips buffer B.
* - Once the UPDATE for the buffer B flip is processed and display
* has finished sending the last pixel of buffer A to precomp for
* the current frame, post-syncpt PS will get signaled.
*
* Clients can use this option iff
* NvKmsAllocDeviceReply::supportsSyncpts is TRUE.
*/
NvBool useSyncpt;
union {
struct {
struct NvKmsSemaphore acquire;
struct NvKmsSemaphore release;
} semaphores;
struct {
struct NvKmsSyncpt pre;
enum NvKmsSyncptType requestedPostType;
} syncpts;
} u;
};
enum NvKmsOutputTf {
/*
* NVKMS itself won't apply any OETF (clients are still
* free to provide a custom OLUT)
*/
NVKMS_OUTPUT_TF_NONE = 0,
NVKMS_OUTPUT_TF_PQ = 1,
};
/*!
* HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec.
* This is expected to match exactly with the spec.
*/
struct NvKmsHDRStaticMetadata {
/*!
* Color primaries of the data.
* These are coded as unsigned 16-bit values in units of 0.00002,
* where 0x0000 represents zero and 0xC350 represents 1.0000.
*/
struct {
NvU16 x, y;
} displayPrimaries[3];
/*!
* White point of colorspace data.
* These are coded as unsigned 16-bit values in units of 0.00002,
* where 0x0000 represents zero and 0xC350 represents 1.0000.
*/
struct {
NvU16 x, y;
} whitePoint;
/**
* Maximum mastering display luminance.
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
*/
NvU16 maxDisplayMasteringLuminance;
/*!
* Minimum mastering display luminance.
* This value is coded as an unsigned 16-bit value in units of
* 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF
* represents 6.5535 cd/m2.
*/
NvU16 minDisplayMasteringLuminance;
/*!
* Maximum content light level.
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
*/
NvU16 maxCLL;
/*!
* Maximum frame-average light level.
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
*/
NvU16 maxFALL;
};
enum NvKmsInputColorSpace {
/* Unknown colorspace; no de-gamma will be applied */
NVKMS_SURFACE_COLORSPACE_NONE = 0,
};
/*!
* Description of how to flip on a single head.
*
* viewPortIn::point describes the position of the viewPortIn that
* should be scaled to the viewPortOut of the head. The
* viewPortSizeIn is specified by NvKmsSetModeOneHeadRequest. Note
* that viewPortIn::point is in desktop coordinate space, and
* therefore applies across all layers.
*
* For YUV420 modes, the surfaces and position should be in "half"
* horizontal space. See the explanation in NvKmsMode.
*
* If 'specified' is FALSE for any of the layers, then the current
* hardware value is used.
*/
struct NvKmsFlipCommonParams {
struct {
NvBool specified;
struct NvKmsPoint point;
} viewPortIn;
struct {
struct NvKmsSetCursorImageCommonParams image;
NvBool imageSpecified;
struct NvKmsMoveCursorCommonParams position;
NvBool positionSpecified;
} cursor;
/*
* Set the output transfer function.
*
* If output transfer function is HDR and staticMetadata is disabled
* for all the layers, flip request will be rejected.
*
* If output transfer function is HDR and staticMetadata is enabled
* for any of the layers, HDR output will be enabled. In this case,
* output lut values specified during modeset will be ignored and
* output lut will be set with the specified HDR transfer function.
*
* If output transfer function is SDR and staticMetadata is enabled,
* HDR content for that layer will be tonemapped to the SDR output
* range.
*/
struct {
enum NvKmsOutputTf val;
NvBool specified;
} tf;
struct {
struct {
NvKmsSurfaceHandle handle[NVKMS_MAX_EYES];
struct NvKmsRRParams rrParams;
NvBool specified;
} surface;
/*
* sizeIn/sizeOut can be used when
* NvKmsAllocDeviceReply::layerCaps[layer].supportsWindowMode is TRUE.
*/
struct {
struct NvKmsSize val;
NvBool specified;
} sizeIn;
struct {
struct NvKmsSize val;
NvBool specified;
} sizeOut;
/*
* Set the position of the layer, relative to the upper left
* corner of the surface. This controls the same state as
* NVKMS_IOCTL_SET_LAYER_POSITION.
*
* This field can be used when
* NvKmsAllocDeviceReply::layerCaps[layer].supportsWindowMode is TRUE.
*/
struct {
struct NvKmsSignedPoint val;
NvBool specified;
} outputPosition;
struct {
struct NvKmsCompletionNotifierDescription val;
NvBool specified;
} completionNotifier;
struct {
struct NvKmsChannelSyncObjects val;
/* If 'specified' is FALSE, then the current hardware value is used. */
NvBool specified;
} syncObjects;
/*
* If 'maxDownscaleFactors::specified' is true, nvkms will set the
* max H/V downscale usage bounds to the values specified in
* 'maxDownscaleFactors::horizontal' and 'maxDownscaleFactors::vertical'.
*
* If the 'maxDownscaleFactors::specified' values are within the bounds
* of 'NvKmsSetModeOneHeadReply::guaranteedUsage', then clients can expect
* the flip to succeed. If the 'maxDownscaleFactors::specified' values are
* beyond the bounds of 'NvKmsSetModeOneHeadReply::guaranteedUsage' but
* within 'NvKmsSetModeOneHeadReply::possibleUsage', then the request may
* legitimately fail due to insufficient display bandwidth and clients
* need to be prepared to handle that flip request failure.
*
* If 'maxDownscaleFactors::specified' is false, nvkms will calculate max
* H/V downscale factor by quantizing the range. E.g., max H/V downscale
* factor supported by HW is 4x for 5-tap and 2x for 2-tap mode. If
* 5-tap mode is required, the target usage bound that nvkms will
* attempt to program will either allow up to 2x downscaling, or up to
* 4x downscaling. If 2-tap mode is required, the target usage bound
* that NVKMS will attempt to program will allow up to 2x downscaling.
* Example: to downscale from 4096x2160 -> 2731x864 in 5-tap mode,
* NVKMS would specify up to 2x for the H downscale bound (required is
* 1.5x), and up to 4x for the V downscale bound (required is 2.5x).
*/
struct {
/*
* Maximum vertical downscale factor (scaled by 1024)
*
* For example, if the downscale factor is 1.5, then maxVDownscaleFactor
* would be 1.5 x 1024 = 1536.
*/
NvU16 vertical;
/*
* Maximum horizontal downscale factor (scaled by 1024)
*
* See the example above for vertical.
*/
NvU16 horizontal;
NvBool specified;
} maxDownscaleFactors;
NvBool tearing;
/*
* When true, we will flip to this buffer whenever the current eye is
* finished scanning out. Otherwise, this flip will only execute after
* both eyes have finished scanout.
*
* Note that if this is FALSE and a vsynced stereo flip is requested,
* the buffers in this flip will be displayed for minPresentInterval*2
* vblanks, one for each eye.
*
* This flag cannot be used for the overlay layer.
*/
NvBool perEyeStereoFlip;
/* When non-zero, block the flip until PTIMER >= timeStamp. */
NvU64 timeStamp NV_ALIGN_BYTES(8);
NvU8 minPresentInterval;
/* This field cannot be used for the main layer right now. */
struct {
struct NvKmsCompositionParams val;
NvBool specified;
} compositionParams;
/*
* Color-space conversion matrix applied to the layer before
* compositing.
*
* If csc::specified is TRUE and csc::useMain is TRUE, then the CSC
* matrix specified in the main layer is used instead of the one here.
* If csc::specified is FALSE, then the CSC matrix used from the previous
* flip is used. csc::useMain must be set to FALSE for the main layer.
*/
struct {
NvBool specified;
NvBool useMain;
struct NvKmsCscMatrix matrix;
} csc;
/*
* When true, all pending flips and synchronization operations get
* ignored, and channel flips to given buffer. Notifier and semaphore
* should not be specified if this flag is true. This flag does
* nothing if set true for NVKMS_IOCTL_SET_MODE ioctl.
*
* This flag allows client to remove stalled flips and unblock
* the channel.
*
* This flag cannot be used for the overlay layer.
*/
NvBool skipPendingFlips;
/*
* This field can be used when
* NvKmsAllocDeviceReply::layerCaps[layer].supportsHDR = TRUE.
*
* If staticMetadata is enabled for multiple layers, flip request
* will be rejected.
*/
struct {
NvBool specified;
/*!
* If TRUE, enable HDR static metadata. If FALSE, disable it.
*
* Note that “specified” serves to mark the field as being changed
* in this flip request, rather than as specified for this frame.
* So to disable HDR static metadata, set hdr.specified = TRUE and
* hdr.staticMetadata.enabled = FALSE.
*/
NvBool enabled;
struct NvKmsHDRStaticMetadata staticMetadata;
} hdr;
struct {
enum NvKmsInputColorSpace val;
NvBool specified;
} colorspace;
} layer[NVKMS_MAX_LAYERS_PER_HEAD];
};
struct NvKmsFlipCommonReplyOneHead {
struct {
struct NvKmsSyncpt postSyncpt;
} layer[NVKMS_MAX_LAYERS_PER_HEAD];
};
/*!
* NVKMS_IOCTL_ALLOC_DEVICE: Allocate an NVKMS device object.
*
* This has the scope of a resman SLI device.
*
* Multiple clients can allocate devices (DRM-KMS, multiple X
* servers). Clients should configure SLI before initializing NVKMS.
* NVKMS will query resman for the current SLI topology.
*
* The SLI configuration (both the linked SLI device, and the sliMosaic
* boolean below) will be latched when the specified GPU transitions
* from zero NVKMS devices allocated to one NVKMS device allocated.
*
* The returned information will remain static until the NVKMS device
* object is freed.
*/
struct NvKmsAllocDeviceRequest {
/*!
* Clients should populate versionString with the value of
* NV_VERSION_STRING from nvUnixVersion.h. This is used for a
* version handshake.
*/
char versionString[NVKMS_NVIDIA_DRIVER_VERSION_STRING_LENGTH];
/*!
* The (primary) GPU for this device; this is used as the value
* for NV0080_ALLOC_PARAMETERS::deviceId.
*/
NvU32 deviceId;
/*!
* Whether SLI Mosaic is requested: i.e., multiple disps, one
* per physical GPU, for the SLI device.
*/
NvBool sliMosaic;
/*!
* When tryInferSliMosaicFromExistingDevice=TRUE, then the above
* 'sliMosaic' field is ignored and the ALLOC_DEVICE request will
* inherit the current sliMosaic state of the existing device
* identified by deviceId. If there is not an existing device for
* deviceId, then the ALLOC_DEVICE request will proceed normally, honoring
* the requested sliMosaic state.
*/
NvBool tryInferSliMosaicFromExistingDevice;
/*!
* NVKMS will use the 3D engine for headSurface. If clients want to avoid
* the use of the 3D engine, set no3d = TRUE. Note this will cause modesets
* that require headSurface to fail.
*
* This flag is only honored when there is not already an existing device
* for the deviceId.
*/
NvBool no3d;
/*!
* When enableConsoleHotplugHandling is TRUE, NVKMS will start handling
* hotplug events at the console when no modeset owner is present.
*
* If FALSE, console hotplug handling behavior is not changed.
*
* This should be set to TRUE for clients that intend to allocate the device
* but don't intend to become the modeset owner right away. It should be set
* to FALSE for clients that may take modeset ownership immediately, in
* order to suppress hotplug handling between the NVKMS_IOCTL_ALLOC_DEVICE
* and NVKMS_IOCTL_GRAB_OWNERSHIP calls when the calling client is the first
* to allocate the device.
*
* Note that NVKMS_IOCTL_RELEASE_OWNERSHIP also enables console hotplug
* handling. Once enabled, console hotplug handling remains enabled until
* the last client frees the device.
*/
NvBool enableConsoleHotplugHandling;
struct {
/* name[0] == '\0' for unused registryKeys[] array elements. */
char name[NVKMS_MAX_DEVICE_REGISTRY_KEYNAME_LEN];
NvU32 value;
} registryKeys[NVKMS_MAX_DEVICE_REGISTRY_KEYS];
};
enum NvKmsAllocDeviceStatus {
NVKMS_ALLOC_DEVICE_STATUS_SUCCESS,
NVKMS_ALLOC_DEVICE_STATUS_VERSION_MISMATCH,
NVKMS_ALLOC_DEVICE_STATUS_BAD_REQUEST,
NVKMS_ALLOC_DEVICE_STATUS_FATAL_ERROR,
NVKMS_ALLOC_DEVICE_STATUS_NO_HARDWARE_AVAILABLE,
NVKMS_ALLOC_DEVICE_STATUS_CORE_CHANNEL_ALLOC_FAILED,
};
struct NvKmsAllocDeviceReply {
enum NvKmsAllocDeviceStatus status;
/*!
* The handle to use when identifying this NVKMS device in
* subsequent calls.
*/
NvKmsDeviceHandle deviceHandle;
/*!
* A bitmask, indicating the GPUs, one per bit, contained by this
* device.
*/
NvU32 subDeviceMask;
/*! The number of heads on each disp. */
NvU32 numHeads;
/*! The number of disps. */
NvU32 numDisps;
/*! The handle to identify each disp, in dispHandles[0..numDisps). */
NvKmsDispHandle dispHandles[NVKMS_MAX_SUBDEVICES];
/*!
* Device-wide Capabilities: of the display engine.
*
* IMPLEMENTATION NOTE: this is the portion of DispHalRec::caps
* that can vary between EVO classes.
*/
NvBool supportsInbandStereoSignaling;
NvBool requiresVrrSemaphores;
NvBool inputLutAppliesToBase;
/*!
* Whether the client can allocate and manipulate SwapGroup objects via
* NVKMS_IOCTL_ALLOC_SWAP_GROUP and friends.
*/
NvBool supportsSwapGroups;
/*!
* Whether the NVKMS SwapGroup implementation supports Warp and Blend on
* this device.
*/
NvBool supportsWarpAndBlend;
/*!
* When nIsoSurfacesInVidmemOnly=TRUE, then only video memory
* surfaces can be used for the surface in
* NvKmsCompletionNotifierDescription or NvKmsSemaphore.
*/
NvBool nIsoSurfacesInVidmemOnly;
/*
* When requiresAllAllocationsInSysmem=TRUE, then all memory allocations
* that will be accessed by display must come from sysmem.
*/
NvBool requiresAllAllocationsInSysmem;
/*
* Whether the device that NVKMS is driving supports headSurface GPU
* composition.
*/
NvBool supportsHeadSurface;
/*!
* The display engine supports a "legacy" format for notifiers and
* semaphores (one word for semaphores and base channel notifiers;
* two words for overlay notifiers). On newer GPUs, the display
* engine also supports a similar four word semaphore and notifier
* format used by graphics.
*
* This describes which values are valid for NvKmsNIsoFormat.
*
* Iff a particular enum NvKmsNIsoFormat 'value' is supported,
* then (1 << value) will be set in validNIsoFormatMask.
*/
NvU8 validNIsoFormatMask;
/*!
* Which NvKmsResamplingMethod enum values are supported by the NVKMS
* device.
*
* Iff a particular enum NvKmsResamplingMethod 'value' is supported, then (1
* << value) will be set in validResamplingMethodMask.
*/
NvU32 validResamplingMethodMask;
NvU32 surfaceAlignment;
NvU32 maxWidthInBytes;
NvU32 maxWidthInPixels;
NvU32 maxHeightInPixels;
NvU32 maxCursorSize;
/*!
* The page kind used by the GPU's MMU for uncompressed block-linear color
* formats.
*/
NvU8 genericPageKind;
/*!
* Describes the supported Color Key selects and blending modes for match
* and nomatch cursor pixels.
*/
struct NvKmsCompositionCapabilities cursorCompositionCaps;
/*! The number of layers attached to each head. */
NvU32 numLayers[NVKMS_MAX_HEADS_PER_DISP];
/*!
* Describes supported functionalities for each layer.
*/
struct NvKmsLayerCapabilities layerCaps[NVKMS_MAX_LAYERS_PER_HEAD];
/*!
* This bitmask specifies all of the (rotation, reflectionX, reflectionY)
* combinations that are supported for the main and overlay layers.
* Each bit in this bitmask is mapped to one combination per the scheme
* in NvKmsRRParamsToCapBit().
*/
NvU16 validLayerRRTransforms;
/*!
* IO coherency modes that display supports for ISO and NISO memory
* allocations, respectively.
*/
NvKmsDispIOCoherencyModes isoIOCoherencyModes;
NvKmsDispIOCoherencyModes nisoIOCoherencyModes;
/*!
* 'supportsSyncpts' indicates whether NVKMS supports the use of syncpts
* for synchronization.
*/
NvBool supportsSyncpts;
/*!
* 'supportsIndependentAcqRelSemaphore' indicates whether HW supports
* configuring different semaphores for acquire and release for a buffer
* flip on a given layer.
*/
NvBool supportsIndependentAcqRelSemaphore;
/*!
* 'supportsVblankSyncObjects' indicates whether HW supports raster
* generator sync objects that signal at vblank.
*/
NvBool supportsVblankSyncObjects;
};
struct NvKmsAllocDeviceParams {
struct NvKmsAllocDeviceRequest request; /*! in */
struct NvKmsAllocDeviceReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_FREE_DEVICE: Free the NVKMS device object specified by
* deviceHandle.
*
* The underlying device is not actually freed until all callers of
* NVKMS_IOCTL_ALLOC_DEVICE have freed their reference to the device.
*
* When a client calls FREE_DEVICE, any configuration specified by
* that client will be removed:
* - Any EDID overrides.
* - Any interest declared on dynamic dpys.
* - Any cursor image on any head.
* - Any custom LUT contents.
* - Any interest declared on any events.
*
* XXX define how FREE_DEVICE interacts with:
* - concurrent X servers on different VTs
* - console restore
*/
struct NvKmsFreeDeviceRequest {
NvKmsDeviceHandle deviceHandle;
};
struct NvKmsFreeDeviceReply {
NvU32 padding;
};
struct NvKmsFreeDeviceParams {
struct NvKmsFreeDeviceRequest request; /*! in */
struct NvKmsFreeDeviceReply reply; /*!out */
};
/*!
* NVKMS_IOCTL_QUERY_DISP: Query information about the NVKMS disp
* object specified by the tuple (deviceHandle, dispHandle).
*
* The returned information will remain static until the NVKMS device
* object is freed.
*/
struct NvKmsQueryDispRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
};
struct NvKmsQueryDispReply {
/*!
* The instance of the subdevice that owns this disp.
* NVBIT(displayOwner) will be present in subDeviceMask.
*/
NvU32 displayOwner;
/*! A bitmask of the device's subdevices used by this disp. */
NvU32 subDeviceMask;
/*! The possible dpys for this disp, excluding any dynamic dpys. */
NVDpyIdList validDpys;
/*! The dpys that were driven at boot-time, if any. */
NVDpyIdList bootDpys;
/*! The dpys that are capable of dynamic mux switching, if any. */
NVDpyIdList muxDpys;
/*! The framelock device, if any, connected to this disp. */
NvKmsFrameLockHandle frameLockHandle;
/*! The number of connectors on this disp. */
NvU32 numConnectors;
/*!
* The handle to identify each connector, in
* connectorHandles[0..numConnectors)
*/
NvKmsConnectorHandle connectorHandles[NVKMS_MAX_CONNECTORS_PER_DISP];
/*!
* A string describing one of the the GPUs used by this disp. The
* NVKMS log will also print this string to the kernel log. Users
* should be able to correlate GPUs between NVKMS and NVKMS
* clients using this string.
*/
char gpuString[NVKMS_GPU_STRING_SIZE];
};
struct NvKmsQueryDispParams {
struct NvKmsQueryDispRequest request; /*! in */
struct NvKmsQueryDispReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_QUERY_CONNECTOR_STATIC_DATA: Query information about the NVKMS
* connector object specified by the triplet (deviceHandle, dispHandle,
* connectorHandle).
*
* The returned information will remain static until the NVKMS device
* object is freed.
*/
struct NvKmsQueryConnectorStaticDataRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvKmsConnectorHandle connectorHandle;
};
struct NvKmsQueryConnectorStaticDataReply {
NVDpyId dpyId;
NvBool isDP;
NvBool isLvds;
NvBool locationOnChip;
NvU32 legacyTypeIndex;
NvKmsConnectorType type;
NvU32 typeIndex;
NvKmsConnectorSignalFormat signalFormat;
NvU32 physicalIndex;
NvU32 physicalLocation;
/* Bitmask of valid heads to drive dpy(s) on this connector. */
NvU32 headMask;
};
struct NvKmsQueryConnectorStaticDataParams {
struct NvKmsQueryConnectorStaticDataRequest request; /*! in */
struct NvKmsQueryConnectorStaticDataReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_QUERY_CONNECTOR_DYNAMIC_DATA: Query dynamic information about the
* NVKMS connector object specified by the triplet (deviceHandle, dispHandle,
* connectorHandle).
*/
struct NvKmsQueryConnectorDynamicDataRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvKmsConnectorHandle connectorHandle;
};
struct NvKmsQueryConnectorDynamicDataReply {
#define NVKMS_DP_DETECT_COMPLETE_POLL_INTERVAL_USEC 100000 /* in microseconds */
#define NVKMS_DP_DETECT_COMPLETE_TIMEOUT_USEC 10000000 /* in microseconds */
/*
* For DisplayPort devices, indicates whether the DisplayPort library is
* finished detecting devices on this connector. This is set to TRUE for
* other devices because NVKMS knows as soon as ALLOC_DEVICE is complete
* whether the device is connected or not.
*/
NvBool detectComplete;
/*
* Contains the list of display IDs for dynamic dpys detected on this
* connector.
*/
NVDpyIdList dynamicDpyIdList;
};
struct NvKmsQueryConnectorDynamicDataParams {
struct NvKmsQueryConnectorDynamicDataRequest request; /*! in */
struct NvKmsQueryConnectorDynamicDataReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_QUERY_DPY_STATIC_DATA: Query static information about
* the NVKMS dpy object specified by the triplet (deviceHandle,
* dispHandle, dpyId). This information should remain static for the
* lifetime of the dpy.
*/
struct NvKmsQueryDpyStaticDataRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
};
struct NvKmsQueryDpyStaticDataReply {
NvKmsConnectorHandle connectorHandle; /*! The connector driving this dpy. */
NvU32 type; /*! NV0073_CTRL_SPECIFIC_DISPLAY_TYPE_ */
char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH];
NvBool mobileInternal;
NvBool isDpMST;
};
struct NvKmsQueryDpyStaticDataParams {
struct NvKmsQueryDpyStaticDataRequest request; /*! in */
struct NvKmsQueryDpyStaticDataReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_QUERY_DPY_DYNAMIC_DATA: Query dynamic information about
* the NVKMS dpy object specified by the triplet (deviceHandle,
* dispHandle, dpyId).
*
* This information should be re-queried after an
* NVKMS_EVENT_TYPE_DPY_CHANGED event.
*/
struct NvKmsQueryDpyDynamicDataRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
NvBool forceConnected;
NvBool forceDisconnected;
NvBool overrideEdid;
NvBool ignoreEdid;
NvBool ignoreEdidChecksum;
NvBool allowDVISpecPClkOverride;
NvBool dpInbandStereoSignaling;
NvBool disableACPIBrightnessHotkeys;
/*
* If overrideEdid is TRUE, then edid::buffer[] contains an EDID
* to override anything detected.
*/
struct {
NvU16 bufferSize;
NvU8 buffer[NVKMS_EDID_BUFFER_SIZE];
} edid;
};
enum NvKmsDpyVRRType {
NVKMS_DPY_VRR_TYPE_NONE,
NVKMS_DPY_VRR_TYPE_GSYNC,
NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED,
NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED,
};
struct NvKmsQueryDpyDynamicDataReply {
char name[NVKMS_DPY_NAME_SIZE];
NvU32 maxPixelClockKHz;
NvBool connected;
NvBool isVirtualRealityHeadMountedDisplay;
struct {
NvU8 heightInCM; /* vertical screen size */
NvU8 widthInCM; /* horizontal screen size */
} physicalDimensions;
/*!
* Which VRR type has been selected for this display, either true
* G-SYNC, Adaptive-Sync defaultlisted, or Adaptive-Sync non-defaultlisted.
*/
enum NvKmsDpyVRRType vrrType;
struct {
NvBool supported;
NvBool isDLP;
NvBool isAegis;
NvU32 subType; /*! STEREO_PLUG_AND_PLAY_ from nvStereoDisplayDef.h */
} stereo3DVision;
struct {
struct {
NvBool valid;
NvU8 buffer[NVKMS_GUID_SIZE];
char str[NVKMS_GUID_STRING_SIZE];
} guid;
} dp;
struct {
/*!
* The size of the EDID in buffer[], or 0 if there is no EDID
* available in buffer[].
*/
NvU16 bufferSize;
/*!
* Whether NVKMS determined that the EDID is valid. If the
* EDID is not valid, there may still be information available
* in infoString: the infoString will describe why the EDID
* was deemed invalid.
*/
NvBool valid;
/*!
* The raw EDID bytes.
*/
NvU8 buffer[NVKMS_EDID_BUFFER_SIZE];
/*!
* Parsed information from the EDID. For the raw EDID bytes,
* see NvKmsQueryDpyDynamicDataParams::edid::buffer[].
*/
char infoString[NVKMS_EDID_INFO_STRING_LENGTH];
} edid;
};
struct NvKmsQueryDpyDynamicDataParams {
struct NvKmsQueryDpyDynamicDataRequest request; /*! in */
struct NvKmsQueryDpyDynamicDataReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_VALIDATE_MODE_INDEX: Validate a particular mode from a
* dpy's candidate modes.
*
* NVKMS can consider modes from a dpy's EDID, as well as a
* variety of builtin modes.
*
* This ioctl identifies one of those candidate modes by index. NVKMS
* will attempt to validate that candidate mode for the dpy, using the
* specified mode validation parameters.
*
* If the mode index is larger than the list of candidate modes,
* reply::end will be TRUE. Otherwise, reply::end will be FALSE, and
* reply::mode will contain the candidate mode.
*
* If the mode is valid, then reply::valid will be TRUE. Otherwise,
* reply::valid will be FALSE. In either case, request::pInfoString[]
* will contain a description of what happened during mode validation.
*
* To query the full modepool, clients should repeatedly call
* NVKMS_IOCTL_VALIDATE_MODE_INDEX with increasing mode index values,
* until NVKMS reports end==TRUE.
*
* Note that the candidate mode list can change when the dpy changes
* (reported by the NVKMS_EVENT_TYPE_DPY_CHANGED event). The client
* should restart its modepool querying if it receives a DPY_CHANGED
* event. The candidate mode list can also change based on the
* parameters in request::modeValidation. Clients should not change
* request::modeValidation while looping over candidate mode indices.
*
* Pseudocode example usage pattern:
*
* struct NvKmsModeValidationParams modeValidation = Initialize();
*
* retry:
* NvU32 modeIndex = 0;
*
* while (1) {
* char infoString[INFO_STRING_LENGTH];
* memset(¶ms);
* params.request.dpyId = dpyId;
* params.request.modeIndex = modeIndex++;
* params.request.modeValidation = modeValidation;
* params.request.pInfoString = nvKmsPointerToNvU64(infoString);
* params.request.infoStringLength = sizeof(infoString);
*
* ioctl(¶ms);
*
* if (params.reply.end) break;
*
* print(infoString);
*
* if (params.reply.valid) {
* AddToModePool(params.reply.mode);
* }
* }
*
* if (dpyChanged) goto retry;
*
*/
struct NvKmsValidateModeIndexRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
struct NvKmsModeValidationParams modeValidation;
NvU32 modeIndex;
/*
* Pointer to a string of size 'infoStringSize'.
* Use nvKmsPointerToNvU64() to assign pInfoString.
* The maximum size allowed is
* NVKMS_MODE_VALIDATION_MAX_INFO_STRING_LENGTH.
*/
NvU32 infoStringSize;
NvU64 pInfoString NV_ALIGN_BYTES(8);
};
struct NvKmsValidateModeIndexReply {
NvBool end;
NvBool valid;
struct NvKmsMode mode;
/*! The validSyncs used by NVKMS when validating the mode. */
struct NvKmsModeValidationValidSyncs validSyncs;
/*! Whether this mode is marked as "preferred" by the EDID. */
NvBool preferredMode;
/*! A text description of the mode. */
char description[64];
/*! Where the mode came from. */
enum NvKmsModeSource {
NvKmsModeSourceUnknown = 0,
NvKmsModeSourceEdid = 1,
NvKmsModeSourceVesa = 2,
} source;
/* The number of bytes written to 'pInfoString' (from the request) */
NvU32 infoStringLenWritten;
/*!
* These are the usage bounds that may be possible with this mode,
* assuming that only one head is active. For actual usage bounds,
* see guaranteedUsage and possibleUsage returned in
* NvKmsSetModeOneHeadReply.
*/
struct NvKmsUsageBounds modeUsage;
};
struct NvKmsValidateModeIndexParams {
struct NvKmsValidateModeIndexRequest request; /*! in */
struct NvKmsValidateModeIndexReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_VALIDATE_MODE: Validate an individual mode for the
* specified dpy.
*
* Given the validation parameters, NVKMS will test whether the given
* mode is currently valid for the specified dpy.
*
* If the mode is valid, then reply::valid will be TRUE. Otherwise,
* reply::valid will be FALSE. In either case, reply::infoString[]
* will contain a description of what happened during mode validation.
*/
struct NvKmsValidateModeRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
struct NvKmsModeValidationParams modeValidation;
struct NvKmsMode mode;
/*
* Pointer to a string of size 'infoStringSize'.
* Use nvKmsPointerToNvU64() to assign pInfoString.
* The maximum size allowed is
* NVKMS_MODE_VALIDATION_MAX_INFO_STRING_LENGTH.
*/
NvU32 infoStringSize;
NvU64 pInfoString NV_ALIGN_BYTES(8);
};
struct NvKmsValidateModeReply {
NvBool valid;
/*! The validSyncs used by NVKMS when validating the mode. */
struct NvKmsModeValidationValidSyncs validSyncs;
/* The number of bytes written to 'pInfoString' (from the request) */
NvU32 infoStringLenWritten;
/*!
* These are the usage bounds that may be possible with this mode,
* assuming that only one head is active. For actual usage bounds,
* see guaranteedUsage and possibleUsage returned in
* NvKmsSetModeOneHeadReply.
*/
struct NvKmsUsageBounds modeUsage;
};
struct NvKmsValidateModeParams {
struct NvKmsValidateModeRequest request; /*! in */
struct NvKmsValidateModeReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_MODE: Perform a modeset.
*
* NvKmsSetModeRequest can describe the modetiming configuration
* across all heads of all disps within the SLI device.
*
* The elements in NvKmsSetModeRequest::disp[] correspond to the disps
* returned in NvKmsAllocDeviceReply::dispHandles[].
*
* To only touch certain heads and disps, use the
* requestedHeadsBitMask and requestedDispsBitMask fields to limit
* which array elements are honored.
*
* If the request is invalid, one or more of the
* NvKmsSetMode{,OneDisp,OneHead}Reply::status fields will have a
* non-SUCCESS value. If the mode set completed successfully, then
* all {NvKmsSetMode{,OneDisp,OneHead}Reply::status fields should be
* SUCCESS.
*/
struct NvKmsSetModeHeadSurfaceParams {
NvBool forceCompositionPipeline;
NvBool forceFullCompositionPipeline;
NvBool fakeOverlay;
NvBool blendAfterWarp;
NvBool transformSpecified;
/* Reflect the image along the X axis. */
NvBool reflectionX;
/* Reflect the image along the Y axis. */
NvBool reflectionY;
/*
* Rotate the image counter-clockwise in 90 degree increments.
*
* Reflection (specified above by ::reflection[XY]) is applied
* before rotation. This matches the semantics of RandR. From:
*
* https://cgit.freedesktop.org/xorg/proto/randrproto/tree/randrproto.txt
*
* "Rotation and reflection and how they interact can be confusing. In
* Randr, the coordinate system is rotated in a counter-clockwise direction
* relative to the normal orientation. Reflection is along the window system
* coordinate system, not the physical screen X and Y axis, so that rotation
* and reflection do not interact. The other way to consider reflection is
* to is specified in the 'normal' orientation, before rotation, if you find
* the other way confusing."
*/
enum NvKmsRotation rotation;
enum NvKmsPixelShiftMode pixelShift;
enum NvKmsResamplingMethod resamplingMethod;
struct NvKmsMatrix transform; /* Only honored if transformSpecified. */
NvKmsSurfaceHandle blendTexSurfaceHandle;
NvKmsSurfaceHandle offsetTexSurfaceHandle;
/*
* When warpMesh::surfaceHandle is non-zero, it indicates a surface
* containing warp mesh vertex data. The surface should:
*
* - Have a width multiple of 1024 pixels.
* - Have a depth of 32.
* - Contain a binary representation of a list of six-component
* vertices. Each of these components is a 32-bit floating point value.
*
* The X, Y components should contain normalized vertex coordinates, to be
* rendered as a triangle list or strip. The X and Y components' [0,1]
* range map to the head's ViewportOut X and Y, respectively.
*
* The U, V, R, and Q components should contain normalized, projective
* texture coordinates:
*
* U, V: 2D texture coordinate. U and V components' [0,1] range maps to the
* display's MetaMode ViewportIn X and Y, respectively.
*
* R: unused
*
* Q: Used for interpolation purposes. This is typically the third
* component of the result of a multiplication by a 3x3 projective transform
* matrix.
*
* warpMesh::vertexCount should contain the amount of vertices stored in the
* surface.
*
* warpMesh::dataType indicates if the vertices describe a triangle list or
* a triangle strip. A triangle list must have a vertexCount that is a
* multiple of 3.
*/
struct {
NvKmsSurfaceHandle surfaceHandle;
NvU32 vertexCount;
enum NvKmsWarpMeshDataType dataType;
} warpMesh;
};
#define NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE 10 // 10hz
enum NvKmsAllowAdaptiveSync {
NVKMS_ALLOW_ADAPTIVE_SYNC_DISABLED = 0,
NVKMS_ALLOW_ADAPTIVE_SYNC_DEFAULTLISTED_ONLY,
NVKMS_ALLOW_ADAPTIVE_SYNC_ALL,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE attribute. */
enum NvKmsDpyAttributeRequestedColorSpaceValue {
NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_RGB = 0,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr422 = 1,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE_YCbCr444 = 2,
};
/*!
* Values for the NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_RANGE and
* NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_RANGE attributes.
*/
enum NvKmsDpyAttributeColorRangeValue {
NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL = 0,
NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_LIMITED = 1,
};
struct NvKmsSetModeOneHeadRequest {
/*!
* The list of dpys to drive with this head; or, empty to disable
* the head.
*/
NVDpyIdList dpyIdList;
/*! The modetimings to set on the head. */
struct NvKmsMode mode;
/*! The above mode will be validated, using these validation parameters. */
struct NvKmsModeValidationParams modeValidationParams;
/*!
* The region within the raster timings that should contain an image.
* This is only used when viewPortOutSpecified is TRUE. Otherwise, the
* viewPortOut is inferred from the raster timings.
*
* For YUV420 modes, the viewPortOut should be in "full"
* horizontal space. See the explanation in NvKmsMode.
*/
struct NvKmsRect viewPortOut;
/*!
* The size, in pixels, that the head will fetch from any surface
* it scans from. The viewPortPointIn is specified in
* NvKmsFlipCommonParams.
*
* For YUV420 modes, the viewPortSizeIn should be in "half"
* horizontal space. See the explanation in NvKmsMode.
*/
struct NvKmsSize viewPortSizeIn;
/*!
* Describe the LUT to be used with the modeset.
*/
struct NvKmsSetLutCommonParams lut;
/*!
* Describe the surfaces to present on this head.
*/
struct NvKmsFlipCommonParams flip;
/*!
* The headSurface configuration requested, if any.
*/
struct NvKmsSetModeHeadSurfaceParams headSurface;
NvBool viewPortOutSpecified; /*! Whether to use viewPortOut. */
/*!
* Allow this head to be flipLocked to any other heads, set as
* part of this NVKMS_IOCTL_SET_MODE, who also have allowFlipLock
* set. FlipLock will only be enabled if additional criteria,
* such as identical modetimings, are also met.
*/
NvBool allowFlipLock;
/*!
* Allow G-SYNC to be enabled on this head if it is supported by the GPU
* and monitor.
*/
NvBool allowGsync;
/*!
* Whether to allow Adaptive-Sync to be enabled on this head if it is
* supported by the GPU:
*
* NVKMS_ALLOW_ADAPTIVE_SYNC_ALL:
* VRR is enabled as long as this monitor supports Adaptive-Sync.
*
* NVKMS_ALLOW_ADAPTIVE_SYNC_DEFAULTLISTED_ONLY:
* VRR is only enabled on this head if the monitor is on the
* Adaptive-Sync defaultlist.
*
* NVKMS_ALLOW_ADAPTIVE_SYNC_DISABLED:
* VRR is forced to be disabled if this is an Adaptive-Sync monitor.
*/
enum NvKmsAllowAdaptiveSync allowAdaptiveSync;
/*!
* Override the minimum refresh rate for VRR monitors specified by the
* EDID (0 to not override the EDID-provided value). Clamped at modeset
* time to within NVKMS_VRR_MIN_REFRESH_RATE_MAX_VARIANCE of the
* EDID-specified minimum refresh rate, as long as the minimum is no
* lower than 1hz and the maximum does not exceed the maximum refresh rate
* defined by the mode timings. The current minimum refresh rate and this
* valid range are exposed through
* NV_KMS_DPY_ATTRIBUTE_VRR_MIN_REFRESH_RATE.
*
* Does not affect G-SYNC monitors, which do not have a minimum refresh
* rate.
*/
NvU32 vrrOverrideMinRefreshRate;
/*!
* Output colorspace. Valid only when colorSpaceSpecified is true.
*/
enum NvKmsDpyAttributeRequestedColorSpaceValue colorSpace;
NvBool colorSpaceSpecified;
/*!
* Output color range. Valid only when colorRangeSpecified is true.
*/
enum NvKmsDpyAttributeColorRangeValue colorRange;
NvBool colorRangeSpecified;
};
struct NvKmsSetModeOneDispRequest {
/*!
* The bit mask of which head[] elements to look at on this disp;
* any other head will use its existing configuration.
*/
NvU32 requestedHeadsBitMask;
struct NvKmsSetModeOneHeadRequest head[NVKMS_MAX_HEADS_PER_DISP];
};
struct NvKmsSetModeRequest {
NvKmsDeviceHandle deviceHandle;
/*!
* When a modeset request is made, NVKMS will first perform
* validation to confirm whether the request can be satisfied. If
* the requested configuration cannot be fulfilled, the request
* returns FALSE.
*
* Only the modeset owner can issue a modeset with commit set to TRUE.
*
* If 'commit' is FALSE, then the status of validation will be returned.
*
* If 'commit' is TRUE, and validation passes, then NVKMS will
* apply the requested configuration.
*/
NvBool commit;
/*!
* The bitmask of which indices within disp[] describe requested
* configuration changes. Any other disps will use their existing
* configuration.
*/
NvU32 requestedDispsBitMask;
/*
* disp[n] corresponds to the disp named by
* NvKmsAllocDeviceReply::dispHandles[n].
*/
struct NvKmsSetModeOneDispRequest disp[NVKMS_MAX_SUBDEVICES];
/*!
* Whether to use NVKMS's builtin headSurface support when necessary.
*
* XXX NVKMS HEADSURFACE TODO: Make this the default and remove this field.
*/
NvBool allowHeadSurfaceInNvKms;
};
enum NvKmsSetModeOneHeadStatus {
NVKMS_SET_MODE_ONE_HEAD_STATUS_SUCCESS = 0,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE = 1,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_DPY = 2,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_CURSOR_IMAGE = 3,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_CURSOR_POSITION = 4,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_LUT = 5,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_FLIP = 6,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_PERMISSIONS = 7,
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_HEAD_SURFACE = 8,
NVKMS_SET_MODE_ONE_HEAD_STATUS_UNSUPPORTED_HEAD_SURFACE_COMBO = 9,
NVKMS_SET_MODE_ONE_HEAD_STATUS_UNSUPPORTED_HEAD_SURFACE_FEATURE = 10,
};
struct NvKmsSetModeOneHeadReply {
/*!
* When the NVKMS_IOCTL_SET_MODE succeeds, then this will be SUCCESS.
* Otherwise, 'status' will be a non-SUCCESS value for one or more
* heads and/or one or more disps.
*
* Note that a failure could occur for a preexisting head
* configuration, so this status could be != SUCCESS for a head
* not listed in NvKmsSetModeOneDispRequest::requestedHeadsBitMask.
*/
enum NvKmsSetModeOneHeadStatus status;
/*!
* The identifier that we use to talk to RM about the display
* device(s) driven by this head. For DP MST, it is the identifier
* of the DisplayPort library group to which the MST device belongs.
* Otherwise, it is the identifier of the connector.
*/
NvU32 activeRmId;
/*!
* The usage bounds that may be possible on this head based on the ISO
* BW at that point.
*
* If a flip request is within the bounds of NvKmsSetModeOneHeadReply::
* guaranteedUsage, then clients can expect the flip to succeed.
* If a flip request is beyond the bounds of NvKmsSetModeOneHeadReply::
* guaranteedUsage but within NvKmsSetModeOneHeadReply::possibleUsage,
* then the request may legitimately fail due to insufficient display
* bandwidth and clients need to be prepared to handle that flip
* request failure.
*/
struct NvKmsUsageBounds possibleUsage;
/*!
* The guaranteed usage bounds usable on this head.
*/
struct NvKmsUsageBounds guaranteedUsage;
/*!
* Whether NVKMS chose to use headSurface on this head.
*/
NvBool usingHeadSurface;
/*!
* Whether NVKMS enabled VRR on this head.
*/
NvBool vrrEnabled;
/*!
* Contains the 'postSyncObject' that the client requested via
* NvKmsSetModeOneHeadRequest::flip.
*/
struct NvKmsFlipCommonReplyOneHead flipReply;
};
enum NvKmsSetModeOneDispStatus {
NVKMS_SET_MODE_ONE_DISP_STATUS_SUCCESS = 0,
NVKMS_SET_MODE_ONE_DISP_STATUS_INVALID_REQUESTED_HEADS_BITMASK = 1,
NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_EXTENDED_GPU_CAPABILITIES_CHECK = 2,
NVKMS_SET_MODE_ONE_DISP_STATUS_FAILED_DISPLAY_PORT_BANDWIDTH_CHECK = 3,
NVKMS_SET_MODE_ONE_DISP_STATUS_INCOMPATIBLE_DPYS = 4,
NVKMS_SET_MODE_ONE_DISP_STATUS_DUPLICATE_DPYS = 5,
};
struct NvKmsSetModeOneDispReply {
/*!
* When the NVKMS_IOCTL_SET_MODE succeeds, then this will be SUCCESS.
* Otherwise, 'status' will be a non-SUCCESS value for one or more
* heads and/or one or more disps.
*
* Note that a failure could occur for a preexisting disp
* configuration, so this status could be != SUCCESS for a disp
* not listed in NvKmsSetModeRequest::requestedDispsBitMask.
*/
enum NvKmsSetModeOneDispStatus status;
struct NvKmsSetModeOneHeadReply head[NVKMS_MAX_HEADS_PER_DISP];
};
enum NvKmsSetModeStatus {
NVKMS_SET_MODE_STATUS_SUCCESS = 0,
NVKMS_SET_MODE_STATUS_INVALID_REQUESTED_DISPS_BITMASK = 1,
NVKMS_SET_MODE_STATUS_NOT_MODESET_OWNER = 2,
};
struct NvKmsSetModeReply {
enum NvKmsSetModeStatus status;
struct NvKmsSetModeOneDispReply disp[NVKMS_MAX_SUBDEVICES];
};
struct NvKmsSetModeParams {
struct NvKmsSetModeRequest request; /*! in */
struct NvKmsSetModeReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_CURSOR_IMAGE: Set the cursor image for the
* specified head.
*/
struct NvKmsSetCursorImageRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvU32 head;
struct NvKmsSetCursorImageCommonParams common;
};
struct NvKmsSetCursorImageReply {
NvU32 padding;
};
struct NvKmsSetCursorImageParams {
struct NvKmsSetCursorImageRequest request; /*! in */
struct NvKmsSetCursorImageReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_MOVE_CURSOR: Set the cursor position for the specified
* head.
*
* x,y are relative to the current viewPortIn configured on the head.
*/
struct NvKmsMoveCursorRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvU32 head;
struct NvKmsMoveCursorCommonParams common;
};
struct NvKmsMoveCursorReply {
NvU32 padding;
};
struct NvKmsMoveCursorParams {
struct NvKmsMoveCursorRequest request; /*! in */
struct NvKmsMoveCursorReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_LUT: Set the LUT contents for the specified head.
*/
struct NvKmsSetLutRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvU32 head;
struct NvKmsSetLutCommonParams common;
};
struct NvKmsSetLutReply {
NvU32 padding;
};
struct NvKmsSetLutParams {
struct NvKmsSetLutRequest request; /*! in */
struct NvKmsSetLutReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_IDLE_BASE_CHANNEL: Wait for the base channel to be idle on
* the requested heads on the requested subdevices of a device.
*
* Each (head,sd) pair to be idled is described by:
*
* subDevicesPerHead[head] |= NVBIT(sd)
*/
struct NvKmsIdleBaseChannelRequest {
NvKmsDeviceHandle deviceHandle;
NvU32 subDevicesPerHead[NVKMS_MAX_HEADS_PER_DISP];
};
struct NvKmsIdleBaseChannelReply {
/*!
* If stopping the base channel is necessary due to a timeout, (head,sd)
* pairs will be described with:
*
* stopSubDevicesPerHead[head] |= NVBIT(sd)
*
* indicating that semaphore releases from the stalled channels may not have
* occurred.
*/
NvU32 stopSubDevicesPerHead[NVKMS_MAX_HEADS_PER_DISP];
};
struct NvKmsIdleBaseChannelParams {
struct NvKmsIdleBaseChannelRequest request; /*! in */
struct NvKmsIdleBaseChannelReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_FLIP: Flip one or more heads on the subdevices of a device.
*
* At least one head on one subdevice must be specified in a flip request.
*/
struct NvKmsFlipRequestOneSubDevice {
/*!
* The bit mask of which head[] elements to look at on this disp.
*/
NvU32 requestedHeadsBitMask;
struct NvKmsFlipCommonParams head[NVKMS_MAX_HEADS_PER_DISP];
};
struct NvKmsFlipRequest {
NvKmsDeviceHandle deviceHandle;
/*
* sd[n] corresponds to bit N in NvKmsQueryDispReply::subDeviceMask and
* NvKmsAllocDeviceReply::subDeviceMask.
*/
struct NvKmsFlipRequestOneSubDevice sd[NVKMS_MAX_SUBDEVICES];
/*!
* When a flip request is made, NVKMS will first perform
* validation to confirm whether the request can be satisfied. If
* the requested configuration cannot be fulfilled, the request
* returns FALSE.
*
* If 'commit' is FALSE, then the status of validation will be returned.
*
* If 'commit' is TRUE, and validation passes, then NVKMS will
* apply the requested configuration.
*/
NvBool commit;
/*!
* When set, indicates that the client is capable of releasing the VRR
* semaphore to indicate when the flip is ready. Setting this to FALSE
* disables VRR.
*/
NvBool allowVrr;
};
enum NvKmsVrrFlipType {
NV_KMS_VRR_FLIP_NON_VRR = 0,
NV_KMS_VRR_FLIP_GSYNC,
NV_KMS_VRR_FLIP_ADAPTIVE_SYNC,
};
struct NvKmsFlipReplyOneSubDevice {
struct NvKmsFlipCommonReplyOneHead head[NVKMS_MAX_HEADS_PER_DISP];
};
struct NvKmsFlipReply {
/*!
* If vrrFlipType != NV_KMS_VRR_FLIP_NON_VRR, then VRR was used for the
* requested flip. In this case, vrrSemaphoreIndex indicates the index
* into the VRR semaphore surface that the client should release to
* trigger the flip.
*
* A value of -1 indicates that no VRR semaphore release is needed.
*/
NvS32 vrrSemaphoreIndex;
/*!
* Indicates whether the flip was non-VRR, was a VRR flip on one or more
* G-SYNC displays, or was a VRR flip exclusively on Adaptive-Sync
* displays.
*/
enum NvKmsVrrFlipType vrrFlipType;
/*!
* sd[n] corresponds to bit N in NvKmsQueryDispReply::subDeviceMask and
* NvKmsAllocDeviceReply::subDeviceMask.
*/
struct NvKmsFlipReplyOneSubDevice sd[NVKMS_MAX_SUBDEVICES];
};
struct NvKmsFlipParams {
struct NvKmsFlipRequest request; /*! in */
struct NvKmsFlipReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_DECLARE_DYNAMIC_DPY_INTEREST: "Dynamic dpy" reference
* counting.
*
* Most dpys have a lifetime equal to the NVKMS device. However, some
* dpys are dynamic and are created and destroyed in response to
* getting connected or disconnected. DisplayPort MST dpys are dynamic dpys.
*
* When a dynamic dpy is disconnected, its NVDpyId will be freed and
* made available for use by dynamic dpys connected later, unless any
* client has declared "interest" in the NVDpyId. The dynamic NVDpyId
* will persist as long as a client has declared interest on it, and
* will be reused for newly connected monitors at the same dynamic dpy
* address (port address, in the case of DP MST dynamic dpys).
*
* The 'interest' field selects interest in the dynamic dpy.
*
* If the dynamic dpy has already been disconnected (and therefore
* removed) before the client has declared interest in it, this ioctl
* will fail.
*
* The recommended usage pattern is:
*
* - Declare interest in the event types:
* NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED
* NVKMS_EVENT_TYPE_DYNAMIC_DPY_DISCONNECTED
*
* - When a DYNAMIC_DPY_CONNECTED event is received, call
* NVKMS_IOCTL_DECLARE_DYNAMIC_DPY_INTEREST
* to declare interest on the dpy. Be sure to check the return
* value, in case the dynamic dpy was already removed. Update any
* client bookkeeping, to start tracking the dpy.
*
* - When a DYNAMIC_DPY_DISCONNECTED event is received, update any
* client bookkeeping, to stop tracking this dynamic dpy. Call
* NVKMS_IOCTL_DECLARE_DYNAMIC_DPY_INTEREST
* to remove interest on the dpy.
*/
struct NvKmsDeclareDynamicDpyInterestRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
NvBool interest;
};
struct NvKmsDeclareDynamicDpyInterestReply {
NvU32 padding;
};
struct NvKmsDeclareDynamicDpyInterestParams {
struct NvKmsDeclareDynamicDpyInterestRequest request; /*! in */
struct NvKmsDeclareDynamicDpyInterestReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_{,UN}REGISTER_SURFACE: Register and unregister an
* RM-allocated surface with NVKMS.
*
* A surface must be registered with NVKMS before NVKMS can display
* it. Note that NVKMS will create its own RM object for the registered
* surface. The surface will not be freed by resman until the surface
* is unregistered by the client.
*/
struct NvKmsRegisterSurfaceRequest {
NvKmsDeviceHandle deviceHandle;
/*!
* Surfaces can be specified either by file descriptor or by
* (rmClient, rmObject) tuple. useFd indicates which is specified
* in this request. Userspace clients are required to specify surface by
* file descriptor.
*/
NvBool useFd;
/*!
* The RM client handle that was used to allocate the surface.
* NVKMS will use this as the hClientSrc argument to
* NvRmDupObject(). Only used when useFd is FALSE.
*/
NvU32 rmClient;
/*
* For multi-plane formats, clients are free to use one memory allocation
* for all planes, or a separate memory allocation per plane:
* - For the first usecase, 'rmObject'/'fd' and 'rmObjectSizeInBytes'
* should be the same for all planes, and each plane should have a
* different 'offset'.
* - For the second usecase, 'rmObject'/'fd' should be different for each
* plane.
*
* The 'planes' array is indexed as follows:
* - For RGB and YUV packed formats, 'planes[0]' refers to the single plane
* that's used for these formats.
* - For YUV semi-planar formats, 'planes[0]' refers to the Y-plane and
* 'planes[1]' refers to the UV-plane.
* - For YUV planar formats, 'planes[0]' refers to the Y-plane, 'planes[1]'
* refers to the U plane, and 'planes[2]' refers to the V plane.
*/
struct {
union {
NvU32 rmObject; /* RM memory handle */
NvS32 fd; /* file descriptor describing memory */
} u;
/*
* This byte offset will be added to the base address of the RM memory
* allocation, and determines the starting address of this plane within
* that allocation. This offset must be 1KB-aligned.
*/
NvU64 offset NV_ALIGN_BYTES(8);
/*
* If the surface layout is NvKmsSurfaceMemoryLayoutPitch, then
* 'pitch' should be the pitch of this plane in bytes, and must
* have an alignment of 256 bytes. If the surface layout is
* NvKmsSurfaceMemoryLayoutBlockLinear, then 'pitch' should be the
* pitch of this plane in _blocks_. Blocks are always 64 bytes
* wide.
*/
NvU32 pitch;
/*
* This is the size of the entire RM memory allocation pointed to by
* rmObject or fd prior to taking the offset into account. This is
* _not_ always the size of this plane since a single RM memory
* allocation can contain multiple planes, and we're also not taking
* the offset into account.
*/
NvU64 rmObjectSizeInBytes NV_ALIGN_BYTES(8);
} planes[NVKMS_MAX_PLANES_PER_SURFACE];
NvU32 widthInPixels;
NvU32 heightInPixels;
enum NvKmsSurfaceMemoryLayout layout;
enum NvKmsSurfaceMemoryFormat format;
NvBool noDisplayHardwareAccess;
/*
* If isoType == NVKMS_MEMORY_NISO, NVKMS will create CPU and GPU mappings
* for the surface memory.
*/
NvKmsMemoryIsoType isoType;
NvU32 log2GobsPerBlockY;
};
struct NvKmsRegisterSurfaceReply {
NvKmsSurfaceHandle surfaceHandle;
};
struct NvKmsRegisterSurfaceParams {
struct NvKmsRegisterSurfaceRequest request; /*! in */
struct NvKmsRegisterSurfaceReply reply; /*! out */
};
struct NvKmsUnregisterSurfaceRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSurfaceHandle surfaceHandle;
};
struct NvKmsUnregisterSurfaceReply {
NvU32 padding;
};
struct NvKmsUnregisterSurfaceParams {
struct NvKmsUnregisterSurfaceRequest request; /*! in */
struct NvKmsUnregisterSurfaceReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_GRANT_SURFACE:
* NVKMS_IOCTL_ACQUIRE_SURFACE:
* NVKMS_IOCTL_RELEASE_SURFACE:
*
* An NVKMS client can "grant" a registered surface to another NVKMS
* client through the following steps:
*
* - The granting NVKMS client should open /dev/nvidia-modeset, and
* call NVKMS_IOCTL_GRANT_SURFACE to associate an NvKmsSurfaceHandle
* with the file descriptor.
*
* - The granting NVKMS client should pass the file descriptor over a
* UNIX domain socket to one or more clients who should acquire the
* surface.
*
* - The granting NVKMS client can optionally close the file
* descriptor now or later.
*
* - Each acquiring client should call NVKMS_IOCTL_ACQUIRE_SURFACE,
* and pass in the file descriptor it received. This returns an
* NvKmsSurfaceHandle that the acquiring client can use to refer to
* the surface in any other NVKMS API call that takes an
* NvKmsSurfaceHandle.
*
* - The acquiring clients can optionally close the file descriptor
* now or later.
*
* - Each acquiring client should call NVKMS_IOCTL_RELEASE_SURFACE to
* release it when they are done with the surface.
*
* - When the granting client unregisters the surface, it is
* "orphaned": NVKMS will flip away from the surface if necessary,
* the RM surface allocation is unduped, and the surface is
* unregistered from EVO. But, the acquiring clients will continue
* to hold a reference to this orphaned surface until they release
* it.
*
* Notes:
*
* - It is an error to call NVKMS_IOCTL_GRANT_SURFACE more than once
* on a /dev/nvidia-modeset file descriptor, or to use a file
* descriptor other than one created by opening /dev/nvidia-modeset,
* or to use a file descriptor that was previously used as the first
* argument to ioctl(2).
*
* - The special handling of surfaces when the granting client
* unregisters the surface might be a little asymmetric. However,
* this strikes a balance between:
*
* (a) Making sure modesetting NVKMS clients can free memory when
* they intend to.
*
* (b) Making sure acquiring clients don't get a stale view of their
* surface handle namespace: if the surface were completely
* unregistered out from under them, the surface handle could be
* recycled without them knowing. If they later attempted to
* release the original surface, they could inadvertently release a
* different surface that happened to have the recycled handle.
*
* - Do we need an NVKMS_IOCTL_REVOKE_SURFACE? Or is the
* automatic-unregistration-in-acquiring-clients behavior
* sufficient?
*/
struct NvKmsGrantSurfaceRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSurfaceHandle surfaceHandle;
int fd;
};
struct NvKmsGrantSurfaceReply {
NvU32 padding;
};
struct NvKmsGrantSurfaceParams {
struct NvKmsGrantSurfaceRequest request; /*! in */
struct NvKmsGrantSurfaceReply reply; /*! out */
};
struct NvKmsAcquireSurfaceRequest {
int fd;
};
struct NvKmsAcquireSurfaceReply {
NvKmsDeviceHandle deviceHandle;
NvKmsSurfaceHandle surfaceHandle;
};
struct NvKmsAcquireSurfaceParams {
struct NvKmsAcquireSurfaceRequest request; /*! in */
struct NvKmsAcquireSurfaceReply reply; /*! out */
};
struct NvKmsReleaseSurfaceRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSurfaceHandle surfaceHandle;
};
struct NvKmsReleaseSurfaceReply {
NvU32 padding;
};
struct NvKmsReleaseSurfaceParams {
struct NvKmsReleaseSurfaceRequest request; /*! in */
struct NvKmsReleaseSurfaceReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_DPY_ATTRIBUTE:
* NVKMS_IOCTL_GET_DPY_ATTRIBUTE:
* NVKMS_IOCTL_GET_DPY_ATTRIBUTE_VALID_VALUES:
*
* Dpys have several attributes that can be queried and set.
*
* An attribute has a type (defined by NvKmsAttributeType), read/write
* permissions, and potentially other descriptions of its valid
* values. Use NVKMS_IOCTL_GET_DPY_ATTRIBUTE_VALID_VALUES to get the
* valid values of an attribute.
*/
enum NvKmsAttributeType {
NV_KMS_ATTRIBUTE_TYPE_INTEGER = 0,
NV_KMS_ATTRIBUTE_TYPE_BOOLEAN,
NV_KMS_ATTRIBUTE_TYPE_INTBITS,
NV_KMS_ATTRIBUTE_TYPE_RANGE,
NV_KMS_ATTRIBUTE_TYPE_BITMASK,
NV_KMS_ATTRIBUTE_TYPE_DPY_ID,
NV_KMS_ATTRIBUTE_TYPE_DPY_ID_LIST,
};
enum NvKmsDpyAttribute {
NV_KMS_DPY_ATTRIBUTE_BACKLIGHT_BRIGHTNESS = 0,
NV_KMS_DPY_ATTRIBUTE_SCANLINE,
NV_KMS_DPY_ATTRIBUTE_HEAD,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_VIBRANCE,
NV_KMS_DPY_ATTRIBUTE_IMAGE_SHARPENING,
NV_KMS_DPY_ATTRIBUTE_IMAGE_SHARPENING_AVAILABLE,
NV_KMS_DPY_ATTRIBUTE_IMAGE_SHARPENING_DEFAULT,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_SPACE,
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_COLOR_RANGE,
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_RANGE,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_LINK_RATE,
NV_KMS_DPY_ATTRIBUTE_FRAMELOCK_DISPLAY_CONFIG,
/*
* XXX NVKMS TODO: Delete UPDATE_GLS_FRAMELOCK; this event-only
* attribute is a kludge to tell GLS about a change in framelock
* configuration made by NVKMS. Eventually, NVKMS should manage
* framelock itself and GLS shouldn't need to be notified.
*
* Note that the event data reports two boolean values: enable
* (bit 0) and server (bit 1).
*/
NV_KMS_DPY_ATTRIBUTE_UPDATE_GLS_FRAMELOCK,
NV_KMS_DPY_ATTRIBUTE_RASTER_LOCK,
NV_KMS_DPY_ATTRIBUTE_UPDATE_FLIPLOCK,
NV_KMS_DPY_ATTRIBUTE_UPDATE_STEREO,
NV_KMS_DPY_ATTRIBUTE_DPMS,
NV_KMS_DPY_ATTRIBUTE_VRR_MIN_REFRESH_RATE,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_IS_MULTISTREAM,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_SINK_IS_AUDIO_CAPABLE,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING attribute. */
enum NvKmsDpyAttributeRequestedDitheringValue {
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_AUTO = 0,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_ENABLED = 1,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DISABLED = 2,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE attribute. */
enum NvKmsDpyAttributeRequestedDitheringModeValue {
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_AUTO = 0,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_DYNAMIC_2X2 = 1,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_STATIC_2X2 = 2,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_MODE_TEMPORAL = 3,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE attribute. */
enum NvKmsDpyAttributeCurrentDitheringModeValue {
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_NONE = 0,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_DYNAMIC_2X2 = 1,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_STATIC_2X2 = 2,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_MODE_TEMPORAL = 3,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH attribute. */
enum NvKmsDpyAttributeRequestedDitheringDepthValue {
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_AUTO = 0,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_6_BITS = 1,
NV_KMS_DPY_ATTRIBUTE_REQUESTED_DITHERING_DEPTH_8_BITS = 2,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH attribute. */
enum NvKmsDpyAttributeCurrentDitheringDepthValue {
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_NONE = 0,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_6_BITS = 1,
NV_KMS_DPY_ATTRIBUTE_CURRENT_DITHERING_DEPTH_8_BITS = 2,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE attribute. */
enum NvKmsDpyAttributeCurrentColorSpaceValue {
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB = 0,
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr422 = 1,
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr444 = 2,
NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_YCbCr420 = 3,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL attribute. */
enum NvKmsDpyAttributeDigitalSignalValue {
NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_LVDS = 0,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_TMDS = 1,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_DISPLAYPORT = 2,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_HDMI_FRL = 3,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_SIGNAL_DSI = 4,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE attribute. */
enum NvKmsDpyAttributeDigitalLinkTypeValue {
NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE_SINGLE = 0,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE_DUAL = 1,
NV_KMS_DPY_ATTRIBUTE_DIGITAL_LINK_TYPE_QUAD = 3,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_FRAMELOCK_DISPLAY_CONFIG attribute. */
enum NvKmsDpyAttributeFrameLockDisplayConfigValue {
NV_KMS_DPY_ATTRIBUTE_FRAMELOCK_DISPLAY_CONFIG_DISABLED = 0,
NV_KMS_DPY_ATTRIBUTE_FRAMELOCK_DISPLAY_CONFIG_CLIENT = 1,
NV_KMS_DPY_ATTRIBUTE_FRAMELOCK_DISPLAY_CONFIG_SERVER = 2,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_DPMS attribute. */
enum NvKmsDpyAttributeDpmsValue {
NV_KMS_DPY_ATTRIBUTE_DPMS_ON,
NV_KMS_DPY_ATTRIBUTE_DPMS_STANDBY,
NV_KMS_DPY_ATTRIBUTE_DPMS_SUSPEND,
NV_KMS_DPY_ATTRIBUTE_DPMS_OFF,
};
/*! Values for the NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE attribute */
enum NvKmsDpyAttributeDisplayportConnectorTypeValue {
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE_UNKNOWN = 0,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE_DISPLAYPORT,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE_HDMI,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE_DVI,
NV_KMS_DPY_ATTRIBUTE_DISPLAYPORT_CONNECTOR_TYPE_VGA,
};
struct NvKmsSetDpyAttributeRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
enum NvKmsDpyAttribute attribute;
NvS64 value NV_ALIGN_BYTES(8);
};
struct NvKmsSetDpyAttributeReply {
NvU32 padding;
};
struct NvKmsSetDpyAttributeParams {
struct NvKmsSetDpyAttributeRequest request; /*! in */
struct NvKmsSetDpyAttributeReply reply; /*! out */
};
struct NvKmsGetDpyAttributeRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
enum NvKmsDpyAttribute attribute;
};
struct NvKmsGetDpyAttributeReply {
NvS64 value NV_ALIGN_BYTES(8);
};
struct NvKmsGetDpyAttributeParams {
struct NvKmsGetDpyAttributeRequest request; /*! in */
struct NvKmsGetDpyAttributeReply reply; /*! out */
};
struct NvKmsAttributeValidValuesCommonReply {
NvBool readable;
NvBool writable;
enum NvKmsAttributeType type;
union {
struct {
NvS64 min NV_ALIGN_BYTES(8);
NvS64 max NV_ALIGN_BYTES(8);
} range; /*! Used when type == NV_KMS_ATTRIBUTE_TYPE_RANGE. */
struct {
NvU32 ints;
} bits; /*! Used when type == NV_KMS_ATTRIBUTE_TYPE_INTBITS. */
} u;
};
struct NvKmsGetDpyAttributeValidValuesRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
enum NvKmsDpyAttribute attribute;
};
struct NvKmsGetDpyAttributeValidValuesReply {
struct NvKmsAttributeValidValuesCommonReply common;
};
struct NvKmsGetDpyAttributeValidValuesParams {
struct NvKmsGetDpyAttributeValidValuesRequest request; /*! in */
struct NvKmsGetDpyAttributeValidValuesReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_DISP_ATTRIBUTE:
* NVKMS_IOCTL_GET_DISP_ATTRIBUTE:
* NVKMS_IOCTL_GET_DISP_ATTRIBUTE_VALID_VALUES:
*/
enum NvKmsDispAttribute {
NV_KMS_DISP_ATTRIBUTE_FRAMELOCK = 0,
NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_SYNC,
NV_KMS_DISP_ATTRIBUTE_GPU_FRAMELOCK_FPGA_REVISION_UNSUPPORTED,
NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_STEREO_SYNC,
NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_TIMING,
NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_TEST_SIGNAL,
NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_RESET,
NV_KMS_DISP_ATTRIBUTE_FRAMELOCK_SET_SWAP_BARRIER,
NV_KMS_DISP_ATTRIBUTE_ALLOW_FLIPLOCK,
NV_KMS_DISP_ATTRIBUTE_QUERY_DP_AUX_LOG,
};
struct NvKmsSetDispAttributeRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
enum NvKmsDispAttribute attribute;
NvS64 value NV_ALIGN_BYTES(8);
};
struct NvKmsSetDispAttributeReply {
NvU32 padding;
};
struct NvKmsSetDispAttributeParams {
struct NvKmsSetDispAttributeRequest request; /*! in */
struct NvKmsSetDispAttributeReply reply; /*! out */
};
struct NvKmsGetDispAttributeRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
enum NvKmsDispAttribute attribute;
};
struct NvKmsGetDispAttributeReply {
NvS64 value NV_ALIGN_BYTES(8);
};
struct NvKmsGetDispAttributeParams {
struct NvKmsGetDispAttributeRequest request; /*! in */
struct NvKmsGetDispAttributeReply reply; /*! out */
};
struct NvKmsGetDispAttributeValidValuesRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
enum NvKmsDispAttribute attribute;
};
struct NvKmsGetDispAttributeValidValuesReply {
struct NvKmsAttributeValidValuesCommonReply common;
};
struct NvKmsGetDispAttributeValidValuesParams {
struct NvKmsGetDispAttributeValidValuesRequest request; /*! in */
struct NvKmsGetDispAttributeValidValuesReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_QUERY_FRAMELOCK: Query information about a framelock
* device.
*/
struct NvKmsQueryFrameLockRequest {
NvKmsFrameLockHandle frameLockHandle;
};
struct NvKmsQueryFrameLockReply {
NvU32 gpuIds[NVKMS_MAX_GPUS_PER_FRAMELOCK];
};
struct NvKmsQueryFrameLockParams {
struct NvKmsQueryFrameLockRequest request; /*! in */
struct NvKmsQueryFrameLockReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_FRAMELOCK_ATTRIBUTE:
* NVKMS_IOCTL_GET_FRAMELOCK_ATTRIBUTE:
* NVKMS_IOCTL_GET_FRAMELOCK_ATTRIBUTE_VALID_VALUES:
*/
enum NvKmsFrameLockAttribute {
NV_KMS_FRAMELOCK_ATTRIBUTE_POLARITY = 0,
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_DELAY,
NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_SYNC_MODE,
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_INTERVAL,
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_READY,
NV_KMS_FRAMELOCK_ATTRIBUTE_VIDEO_MODE,
NV_KMS_FRAMELOCK_ATTRIBUTE_FPGA_REVISION,
NV_KMS_FRAMELOCK_ATTRIBUTE_FIRMWARE_MAJOR_VERSION,
NV_KMS_FRAMELOCK_ATTRIBUTE_FIRMWARE_MINOR_VERSION,
NV_KMS_FRAMELOCK_ATTRIBUTE_BOARD_ID,
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_DELAY_RESOLUTION,
NV_KMS_FRAMELOCK_ATTRIBUTE_PORT0_STATUS,
NV_KMS_FRAMELOCK_ATTRIBUTE_PORT1_STATUS,
NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_STATUS,
NV_KMS_FRAMELOCK_ATTRIBUTE_ETHERNET_DETECTED,
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_RATE,
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_RATE_4,
NV_KMS_FRAMELOCK_ATTRIBUTE_INCOMING_HOUSE_SYNC_RATE,
};
/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_POLARITY attribute. */
enum NvKmsFrameLockAttributePolarityValue {
NV_KMS_FRAMELOCK_ATTRIBUTE_POLARITY_RISING_EDGE = 0x1,
NV_KMS_FRAMELOCK_ATTRIBUTE_POLARITY_FALLING_EDGE = 0x2,
NV_KMS_FRAMELOCK_ATTRIBUTE_POLARITY_BOTH_EDGES = 0x3,
};
/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_SYNC_MODE attribute. */
enum NvKmsFrameLockAttributeHouseSyncModeValue {
NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_SYNC_MODE_DISABLED = 0,
NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_SYNC_MODE_INPUT = 0x1,
NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_SYNC_MODE_OUTPUT = 0x2,
};
/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_ETHERNET_DETECTED attribute. */
enum NvKmsFrameLockAttributeEthernetDetectedValue {
NV_KMS_FRAMELOCK_ATTRIBUTE_ETHERNET_DETECTED_NONE = 0,
NV_KMS_FRAMELOCK_ATTRIBUTE_ETHERNET_DETECTED_PORT0 = 0x1,
NV_KMS_FRAMELOCK_ATTRIBUTE_ETHERNET_DETECTED_PORT1 = 0x2,
};
/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_VIDEO_MODE attribute. */
enum NvKmsFrameLockAttributeVideoModeValue {
NV_KMS_FRAMELOCK_ATTRIBUTE_VIDEO_MODE_COMPOSITE_AUTO = 0,
NV_KMS_FRAMELOCK_ATTRIBUTE_VIDEO_MODE_TTL = 1,
NV_KMS_FRAMELOCK_ATTRIBUTE_VIDEO_MODE_COMPOSITE_BI_LEVEL = 2,
NV_KMS_FRAMELOCK_ATTRIBUTE_VIDEO_MODE_COMPOSITE_TRI_LEVEL = 3,
};
/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_PORT[01]_STATUS attributes. */
enum NvKmsFrameLockAttributePortStatusValue {
NV_KMS_FRAMELOCK_ATTRIBUTE_PORT_STATUS_INPUT = 0,
NV_KMS_FRAMELOCK_ATTRIBUTE_PORT_STATUS_OUTPUT = 1,
};
struct NvKmsSetFrameLockAttributeRequest {
NvKmsFrameLockHandle frameLockHandle;
enum NvKmsFrameLockAttribute attribute;
NvS64 value NV_ALIGN_BYTES(8);
};
struct NvKmsSetFrameLockAttributeReply {
NvU32 padding;
};
struct NvKmsSetFrameLockAttributeParams {
struct NvKmsSetFrameLockAttributeRequest request; /*! in */
struct NvKmsSetFrameLockAttributeReply reply; /*! out */
};
struct NvKmsGetFrameLockAttributeRequest {
NvKmsFrameLockHandle frameLockHandle;
enum NvKmsFrameLockAttribute attribute;
};
struct NvKmsGetFrameLockAttributeReply {
NvS64 value NV_ALIGN_BYTES(8);
};
struct NvKmsGetFrameLockAttributeParams {
struct NvKmsGetFrameLockAttributeRequest request; /*! in */
struct NvKmsGetFrameLockAttributeReply reply; /*! out */
};
struct NvKmsGetFrameLockAttributeValidValuesRequest {
NvKmsFrameLockHandle frameLockHandle;
enum NvKmsFrameLockAttribute attribute;
};
struct NvKmsGetFrameLockAttributeValidValuesReply {
struct NvKmsAttributeValidValuesCommonReply common;
};
struct NvKmsGetFrameLockAttributeValidValuesParams {
struct NvKmsGetFrameLockAttributeValidValuesRequest request; /*! in */
struct NvKmsGetFrameLockAttributeValidValuesReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_GET_NEXT_EVENT, NVKMS_IOCTL_DECLARE_EVENT_INTEREST:
* Event handling.
*
* Clients should call NVKMS_IOCTL_DECLARE_EVENT_INTEREST to indicate
* the events in which they are interested. Then, block on poll(2) or
* select(2) until there are events available to read on the file
* descriptor.
*
* When events are available, the client should call
* NVKMS_IOCTL_GET_NEXT_EVENT to get an NvKmsEvent structure, and
* interpret the union based on eventType.
*
* Clients can remove interest for events by calling
* NVKMS_IOCTL_DECLARE_EVENT_INTEREST again, specifying a new
* interestMask.
*
* Note that there may still be events queued for the client when the
* client calls NVKMS_IOCTL_DECLARE_EVENT_INTEREST to change its
* interestMask. So, clients should be prepared to ignore unexpected
* events after calling NVKMS_IOCTL_DECLARE_EVENT_INTEREST.
*/
/*!
* NVKMS_EVENT_TYPE_DPY_CHANGED
*
* When a dpy changes, this event will be generated. The client
* should call NVKMS_IOCTL_QUERY_DPY_DYNAMIC_DATA to get an updated
* NvKmsQueryDpyDynamicDataReply.
*/
struct NvKmsEventDpyChanged {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
};
/*!
* NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED
*
* When a dynamic dpy is connected, this event will be generated.
*/
struct NvKmsEventDynamicDpyConnected {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
};
/*!
* NVKMS_EVENT_TYPE_DYNAMIC_DPY_DISCONNECTED
*
* When a dynamic dpy is disconnected, this event will be generated.
*/
struct NvKmsEventDynamicDpyDisconnected {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
};
/*!
* NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED
*
* When a dpy attribute changes, this event will be generated.
*/
struct NvKmsEventDpyAttributeChanged {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
enum NvKmsDpyAttribute attribute;
NvS64 value NV_ALIGN_BYTES(8);
};
/*!
* NVKMS_EVENT_TYPE_FRAMELOCK_ATTRIBUTE_CHANGED
*
* When a framelock attribute changes, this event will be generated.
*/
struct NvKmsEventFrameLockAttributeChanged {
NvKmsFrameLockHandle frameLockHandle;
enum NvKmsFrameLockAttribute attribute;
NvS64 value NV_ALIGN_BYTES(8);
};
/*!
* NVKMS_EVENT_TYPE_FLIP_OCCURRED
*
* When a client requests a flip and specifies a completion notifier
* with NvKmsCompletionNotifierDescription::awaken == TRUE, this event
* will be generated. This event is only delivered to clients with
* flipping permission.
*/
struct NvKmsEventFlipOccurred {
NvKmsDeviceHandle deviceHandle;
/* XXX NVKMS TODO: the dispHandle is currently hard-coded to 0. */
NvKmsDispHandle dispHandle;
NvU32 head;
NvU32 layer;
};
struct NvKmsEvent {
enum NvKmsEventType eventType;
union {
struct NvKmsEventDpyChanged dpyChanged;
struct NvKmsEventDynamicDpyConnected dynamicDpyConnected;
struct NvKmsEventDynamicDpyDisconnected dynamicDpyDisconnected;
struct NvKmsEventDpyAttributeChanged dpyAttributeChanged;
struct NvKmsEventFrameLockAttributeChanged frameLockAttributeChanged;
struct NvKmsEventFlipOccurred flipOccurred;
} u;
};
struct NvKmsGetNextEventRequest {
NvU32 padding;
};
struct NvKmsGetNextEventReply {
/*!
* If an event is available, valid = TRUE and the NvKmsEvent
* contains the event. If no event is available, valid = FALSE.
*/
NvBool valid;
struct NvKmsEvent event;
};
struct NvKmsGetNextEventParams {
struct NvKmsGetNextEventRequest request; /*! in */
struct NvKmsGetNextEventReply reply; /*! out */
};
struct NvKmsDeclareEventInterestRequest {
/*!
* Mask of event types, where each event type is indicated by (1
* << NVKMS_EVENT_TYPE_).
*/
NvU32 interestMask;
};
struct NvKmsDeclareEventInterestReply {
NvU32 padding;
};
struct NvKmsDeclareEventInterestParams {
struct NvKmsDeclareEventInterestRequest request; /*! in */
struct NvKmsDeclareEventInterestReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_CLEAR_UNICAST_EVENT
*
* The events generated through NVKMS_IOCTL_DECLARE_EVENT_INTEREST and
* NVKMS_IOCTL_GET_NEXT_EVENT are most useful for system-wide events which
* multiple clients may be interested in. Clients declare their interest in a
* collection of event types, and when they are notified that some number of
* events arrived, they have to query the events from the event queue.
*
* In contrast, "Unicast Events" are for use in cases where a client is only
* interested in a particular type of event on a particular object.
*
* To use a Unicast Event:
*
* - Create an fd through nvKmsOpen().
*
* - Do _not_ use the fd for anything else (the first argument to ioctl(2), the
* fd in any of the granting APIs such as NvKmsGrantSurfaceParams::request:fd,
* etc).
*
* - Pass the fd into an API that allows a unicast event. E.g.,
* NvKmsJoinSwapGroupParams::request::member::unicastEvent::fd
*
* - Clear the unicast event with NVKMS_IOCTL_CLEAR_UNICAST_EVENT.
*
* - Check if the event arrived; if it hasn't, then wait for the event through
* poll(2) or select(2).
*/
struct NvKmsClearUnicastEventRequest {
int unicastEventFd;
};
struct NvKmsClearUnicastEventReply {
NvU32 padding;
};
struct NvKmsClearUnicastEventParams {
struct NvKmsClearUnicastEventRequest request; /*! in */
struct NvKmsClearUnicastEventReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_LAYER_POSITION: Set the position of the layer
* for the specified heads on the specified disps. The layer
* position is in "desktop coordinate space", i.e., relative to the
* upper left corner of the input viewport.
*
* Note that this is only valid if
* NvKmsAllocDeviceReply::layerCaps[layer].supportsWindowMode is TRUE.
*/
struct NvKmsSetLayerPositionRequest {
NvKmsDeviceHandle deviceHandle;
/*!
* The bitmask of which indices within disp[] describe requested
* configuration changes. Any other disps will use their existing
* configuration.
*/
NvU32 requestedDispsBitMask;
struct {
/*!
* The bitmask of which head[] elements to look at on this
* disp; any other head will use its existing configuration.
*/
NvU32 requestedHeadsBitMask;
struct {
struct NvKmsSignedPoint layerPosition[NVKMS_MAX_LAYERS_PER_HEAD];
/*!
* The bitmask of which layerPosition[] elements to look at on this
* head; any other layer will use its existing configuration.
*/
NvU32 requestedLayerBitMask;
} head[NVKMS_MAX_HEADS_PER_DISP];
} disp[NVKMS_MAX_SUBDEVICES];
};
struct NvKmsSetLayerPositionReply {
NvU32 padding;
};
struct NvKmsSetLayerPositionParams {
struct NvKmsSetLayerPositionRequest request; /*! in */
struct NvKmsSetLayerPositionReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_GRAB_OWNERSHIP:
* NVKMS_IOCTL_RELEASE_OWNERSHIP:
*
* NVKMS_IOCTL_GRAB_OWNERSHIP notifies NVKMS that the calling client wants to
* control modesets on the device, and NVKMS_IOCTL_RELEASE_OWNERSHIP indicates
* that the modeset ownership should be released and the VT console mode
* restored.
*
* It is not necessary to call NVKMS_IOCTL_RELEASE_OWNERSHIP during shutdown;
* NVKMS will implicitly clear modeset ownership in nvKmsClose().
*
* Releasing modeset ownership enables console hotplug handling. See the
* explanation in the comment for enableConsoleHotplugHandling above.
*/
struct NvKmsGrabOwnershipRequest {
NvKmsDeviceHandle deviceHandle;
};
struct NvKmsGrabOwnershipReply {
NvU32 padding;
};
struct NvKmsGrabOwnershipParams {
struct NvKmsGrabOwnershipRequest request; /*! in */
struct NvKmsGrabOwnershipReply reply; /*! out */
};
struct NvKmsReleaseOwnershipRequest {
NvKmsDeviceHandle deviceHandle;
};
struct NvKmsReleaseOwnershipReply {
NvU32 padding;
};
struct NvKmsReleaseOwnershipParams {
struct NvKmsReleaseOwnershipRequest request; /*! in */
struct NvKmsReleaseOwnershipReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_GRANT_PERMISSIONS:
* NVKMS_IOCTL_ACQUIRE_PERMISSIONS:
* NVKMS_IOCTL_REVOKE_PERMISSIONS:
*
* By default, only the modeset owning NVKMS client (the one who
* successfully called NVKMS_IOCTL_GRAB_OWNERSHIP) is allowed to flip
* or set modes.
*
* However, the modeset owner can grant various permissions to other
* clients through the following steps:
*
* - The modeset owner should open /dev/nvidia-modeset, and call
* NVKMS_IOCTL_GRANT_PERMISSIONS to define a set of permissions
* associated with the file descriptor.
*
* - The modeset owner should pass the file descriptor over a UNIX
* domain socket to one or more clients who should acquire these
* permissions.
*
* - The modeset owner can optionally close the file descriptor now or
* later.
*
* - The acquiring clients should call NVKMS_IOCTL_ACQUIRE_PERMISSIONS
* and pass in the file descriptor they received, to update their
* client connection to include the permissions specified by the modeset
* owner in the first bullet.
*
* - The acquiring clients can optionally close the file descriptor
* now or later.
*
* - From this point forward, both the modeset owner and the clients
* are allowed to perform the actions allowed by the granted
* permissions.
*
* - The modeset owner can optionally revoke any previously granted
* permissions with NVKMS_IOCTL_REVOKE_PERMISSIONS.
*
* Notes:
*
* - NVKMS_IOCTL_REVOKE_PERMISSIONS has device-scope. It could be
* made finer-grained (e.g., take the file descriptor that was used
* to grant permissions) if that were needed.
*
* - NvKmsPermissions::disp[n] corresponds to the disp named by
* NvKmsAllocDeviceReply::dispHandles[n].
*
* - It is an error to call NVKMS_IOCTL_GRANT_PERMISSIONS more than
* once on a /dev/nvidia-modeset file descriptor, or to use a file
* descriptor other than one created by opening /dev/nvidia-modeset,
* or to use a file descriptor that was previously used as the first
* argument to ioctl(2).
*
* - Calling NVKMS_IOCTL_ACQUIRE_PERMISSIONS more than once on the
* same NVKMS client will cause the new permissions for that client
* to be the union of the previous permissions and the latest
* permissions being acquired.
*/
enum NvKmsPermissionsType {
NV_KMS_PERMISSIONS_TYPE_FLIPPING = 1,
NV_KMS_PERMISSIONS_TYPE_MODESET = 2,
};
struct NvKmsFlipPermissions {
struct {
struct {
/*
* Bitmask of flippable layers, where each layer is
* indicated by '1 << layer'. It is an error for bits
* above NVKMS_MAX_LAYERS_PER_HEAD to be set.
*
* Only applicable when type==FLIPPING.
*/
NvU8 layerMask;
} head[NVKMS_MAX_HEADS_PER_DISP];
} disp[NVKMS_MAX_SUBDEVICES];
};
struct NvKmsModesetPermissions {
struct {
struct {
/*
* A list of dpys which a particular NVKMS client is
* allowed to use when performing a modeset on this head.
*
* If the NVKMS client is not allowed to set a mode on
* this head, this list will be empty.
*
* If an NVKMS client can drive the head without
* restrictions, this will be nvAllDpyIdList().
*
* Only applicable when type==MODESET.
*/
NVDpyIdList dpyIdList;
} head[NVKMS_MAX_HEADS_PER_DISP];
} disp[NVKMS_MAX_SUBDEVICES];
};
struct NvKmsPermissions {
enum NvKmsPermissionsType type;
union {
struct NvKmsFlipPermissions flip;
struct NvKmsModesetPermissions modeset;
};
};
struct NvKmsGrantPermissionsRequest {
int fd;
NvKmsDeviceHandle deviceHandle;
struct NvKmsPermissions permissions;
};
struct NvKmsGrantPermissionsReply {
NvU32 padding;
};
struct NvKmsGrantPermissionsParams {
struct NvKmsGrantPermissionsRequest request; /*! in */
struct NvKmsGrantPermissionsReply reply; /*! out */
};
struct NvKmsAcquirePermissionsRequest {
int fd;
};
struct NvKmsAcquirePermissionsReply {
/*! This client's handle for the device which acquired new permissions */
NvKmsDeviceHandle deviceHandle;
/*!
* The acquired permissions.
*
* If permissions::type == FLIPPING, the new combined flipping
* permissions of the calling client on this device, including
* prior permissions and permissions added by this operation.
*/
struct NvKmsPermissions permissions;
};
struct NvKmsAcquirePermissionsParams {
struct NvKmsAcquirePermissionsRequest request; /*! in */
struct NvKmsAcquirePermissionsReply reply; /*! out */
};
struct NvKmsRevokePermissionsRequest {
NvKmsDeviceHandle deviceHandle;
/*
* A bitmask of permission types to be revoked for this device.
* It should be the bitwise 'or' of one or more
* NVBIT(NV_KMS_PERMISSIONS_TYPE_*) values.
*/
NvU32 permissionsTypeBitmask;
};
struct NvKmsRevokePermissionsReply {
NvU32 padding;
};
struct NvKmsRevokePermissionsParams {
struct NvKmsRevokePermissionsRequest request; /*! in */
struct NvKmsRevokePermissionsReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_QUERY_DPY_CRC32
*
* Query last CRC32 value from the NVKMS disp head specified by the triplet
* (deviceHandle, dispHandle, head).
*/
struct NvKmsQueryDpyCRC32Request {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvU32 head;
};
/*!
* Generic CRC-structure type to represent CRC value obtained and if
* hardware architecture supports collection of the CRC type. If
* the CRC is not supported by hardware, its value is undefined.
*/
struct NvKmsDpyCRC32 {
/*!
* Value of the CRC. If it is not supported, value is undefined.
*/
NvU32 value;
/*!
* Boolean which represents if hardware supports CRC collection
* If this boolean is FALSE, CRC hardware collection is not supported.
*/
NvBool supported;
};
/*!
* Reply structure that contains CRC32 values returned from hardware.
* Supported CRCs obtained are represented by supported boolean in crc struct
* Note- Crcs that are not supported will not be updated and will remain at 0
*/
struct NvKmsQueryDpyCRC32Reply {
/*!
* CRC generated from the Compositor hardware
*/
struct NvKmsDpyCRC32 compositorCrc32;
/*!
* CRC generated from the RG hardware, if head is driving RG/SF.
* Note that if Dithering is enabled, this CRC will vary across reads
* from the same frame.
*/
struct NvKmsDpyCRC32 rasterGeneratorCrc32;
/*!
* Crc value generated from the target SF/OR depending on connector's OR type
* Note that if Dithering is enabled, this CRC will vary across reads
* from the same frame.
*/
struct NvKmsDpyCRC32 outputCrc32;
};
struct NvKmsQueryDpyCRC32Params {
struct NvKmsQueryDpyCRC32Request request; /*! in */
struct NvKmsQueryDpyCRC32Reply reply; /*! out */
};
/*!
* User-space pointers are always passed to NVKMS in an NvU64.
* This user-space address is eventually passed into the platform's
* copyin/copyout functions, in a void* argument.
*
* This utility function converts from a pointer to an NvU64.
*/
static inline NvU64 nvKmsPointerToNvU64(const void *ptr)
{
return (NvU64)(NvUPtr)ptr;
}
/*!
* NVKMS_IOCTL_REGISTER_DEFERRED_REQUEST_FIFO:
* NVKMS_IOCTL_UNREGISTER_DEFERRED_REQUEST_FIFO:
*
* To make a request that is deferred until after a specific point in a client's
* graphics channel, a client should register a surface with NVKMS as a
* "deferred request fifo". The surface is interpreted as having the layout of
* struct NvKmsDeferredRequestFifo.
*
* To make deferred requests, the client should:
*
* - Write the NVKMS_DEFERRED_REQUEST_OPCODE for the desired operation to
* NvKmsDeferredRequestFifo::request[i], where 'i' is the next available
* element in the request[] array. Repeat as necessary.
*
* - Push NV906F_SEMAPHORE[ABCD] methods in its graphics channel to write
* '(i + 1) % NVKMS_MAX_DEFERRED_REQUESTS' to
* NvKmsDeferredRequestFifo::put.
*
* - Push an NV906F_NON_STALL_INTERRUPT method in its graphics channel.
*
* NVKMS will be notified of the non-stall interrupt, and scan all clients'
* deferred request fifos for put != get. NVKMS will then perform the requests
* specified in request[get] through request[put-1]. Finally, NVKMS will update
* get to indicate how much of the fifo it consumed.
*
* Wrapping behaves as expected. In pseudo code:
*
* while (get != put) {
* do(request[get]);
* get = (get + 1) % NVKMS_MAX_DEFERRED_REQUESTS;
* }
*
* The only time it is safe for clients to write to get is when get == put and
* there are no outstanding semaphore releases to gpuPut.
*
* The surface used for the deferred request fifo must be:
*
* - In system memory (NVKMS will create one device-scoped mapping, not one per
* subdevice, as would be needed if the surface were in video memory).
*
* - At least as large as sizeof(NvKmsDeferredRequestFifo).
*
* Some NVKMS_DEFERRED_REQUESTs may need to write to a semaphore after some
* operation is performed (e.g., to indicate that a SwapGroup is ready, or that
* we've reached vblank). The NVKMS_DEFERRED_REQUEST_SEMAPHORE_INDEX field
* within the request specifies a semaphore within the
* NvKmsDeferredRequestFifo::semaphore[] array. The semantics of that semaphore
* index are opcode-specific.
*
* The opcode and semaphore index are in the low 16-bits of the request. The
* upper 16-bits are opcode-specific.
*/
#define NVKMS_MAX_DEFERRED_REQUESTS 128
#define NVKMS_DEFERRED_REQUEST_OPCODE 7:0
#define NVKMS_DEFERRED_REQUEST_SEMAPHORE_INDEX 15:8
#define NVKMS_DEFERRED_REQUEST_OPCODE_NOP 0
/*
* The SWAP_GROUP_READY request means that this NvKmsDeferredRequestFifo is
* ready for the next swap of the SwapGroup (see NVKMS_IOCTL_JOIN_SWAP_GROUP,
* below). NVKMS_DEFERRED_REQUEST_SEMAPHORE_INDEX should specify an element in
* the semaphore[] array which will be released to
*
* NVKMS_DEFERRED_REQUEST_SEMAPHORE_VALUE_SWAP_GROUP_READY
*
* when the SwapGroup actually swaps.
*/
#define NVKMS_DEFERRED_REQUEST_OPCODE_SWAP_GROUP_READY 1
#define NVKMS_DEFERRED_REQUEST_SEMAPHORE_VALUE_SWAP_GROUP_NOT_READY 0x00000000
#define NVKMS_DEFERRED_REQUEST_SEMAPHORE_VALUE_SWAP_GROUP_READY 0xFFFFFFFF
/*
* The SWAP_GROUP_READY_PER_EYE_STEREO field indicates whether this deferred
* request fifo wants the SwapGroup to present new content at every eye boundary
* (PER_EYE), or present new content only when transitioning from the right eye
* to the left eye (PER_PAIR).
*/
#define NVKMS_DEFERRED_REQUEST_SWAP_GROUP_READY_PER_EYE_STEREO 16:16
#define NVKMS_DEFERRED_REQUEST_SWAP_GROUP_READY_PER_EYE_STEREO_PER_PAIR 0
#define NVKMS_DEFERRED_REQUEST_SWAP_GROUP_READY_PER_EYE_STEREO_PER_EYE 1
struct NvKmsDeferredRequestFifo {
NvU32 put;
NvU32 get;
NvU32 request[NVKMS_MAX_DEFERRED_REQUESTS];
NvGpuSemaphore semaphore[NVKMS_MAX_DEFERRED_REQUESTS];
};
struct NvKmsRegisterDeferredRequestFifoRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSurfaceHandle surfaceHandle;
};
struct NvKmsRegisterDeferredRequestFifoReply {
NvKmsDeferredRequestFifoHandle deferredRequestFifoHandle;
};
struct NvKmsRegisterDeferredRequestFifoParams {
struct NvKmsRegisterDeferredRequestFifoRequest request; /*! in */
struct NvKmsRegisterDeferredRequestFifoReply reply; /*! out */
};
struct NvKmsUnregisterDeferredRequestFifoRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDeferredRequestFifoHandle deferredRequestFifoHandle;
};
struct NvKmsUnregisterDeferredRequestFifoReply {
NvU32 padding;
};
struct NvKmsUnregisterDeferredRequestFifoParams {
struct NvKmsUnregisterDeferredRequestFifoRequest request; /*! in */
struct NvKmsUnregisterDeferredRequestFifoReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_ALLOC_SWAP_GROUP
* NVKMS_IOCTL_FREE_SWAP_GROUP
*
* An NVKMS client creates a SwapGroup by calling NVKMS_IOCTL_ALLOC_SWAP_GROUP
* and specifying the heads in the SwapGroup with
* NvKmsAllocSwapGroupRequest::disp[]::headMask.
*
* The SwapGroup can be shared with clients through
* NVKMS_IOCTL_GRANT_SWAP_GROUP, and it is destroyed once all clients that have
* acquired the swap group through NVKMS_IOCTL_ACQUIRE_SWAP_GROUP have released
* it through NVKMS_IOCTL_RELEASE_SWAP_GROUP and when the client that created
* the swap group has called NVKMS_IOCTL_FREE_SWAP_GROUP or freed the device.
*
* The SwapGroup allocation is expected to have a long lifetime (e.g., the X
* driver might call ALLOC_SWAP_GROUP from ScreenInit and FREE_SWAP_GROUP from
* CloseScreen). The point of these requests is to define the head topology of
* the SwapGroup (for X driver purposes, presumably all the heads that are
* assigned to the X screen).
*
* As such:
*
* - Not all heads described in the ALLOC_SWAP_GROUP request need to be active
* (they can come and go with different modesets).
*
* - The SwapGroup persists across modesets.
*
* - SwapGroup allocation is expected to be lightweight: the heavyweight
* operations like allocating and freeing headSurface resources are done when
* the number of SwapGroup members (see {JOIN,LEAVE}_SWAP_GROUP below)
* transitions between 0 and 1.
*
* Only an NVKMS modeset owner can alloc or free a SwapGroup.
*/
struct NvKmsSwapGroupConfig {
struct {
NvU32 headMask;
} disp[NVKMS_MAX_SUBDEVICES];
};
struct NvKmsAllocSwapGroupRequest {
NvKmsDeviceHandle deviceHandle;
struct NvKmsSwapGroupConfig config;
};
struct NvKmsAllocSwapGroupReply {
NvKmsSwapGroupHandle swapGroupHandle;
};
struct NvKmsAllocSwapGroupParams {
struct NvKmsAllocSwapGroupRequest request; /*! in */
struct NvKmsAllocSwapGroupReply reply; /*! out */
};
struct NvKmsFreeSwapGroupRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSwapGroupHandle swapGroupHandle;
};
struct NvKmsFreeSwapGroupReply {
NvU32 padding;
};
struct NvKmsFreeSwapGroupParams {
struct NvKmsFreeSwapGroupRequest request; /*! in */
struct NvKmsFreeSwapGroupReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_JOIN_SWAP_GROUP
* NVKMS_IOCTL_LEAVE_SWAP_GROUP
*
* Clients can join NvKmsDeferredRequestFifos to SwapGroups using
* NVKMS_IOCTL_JOIN_SWAP_GROUP, and remove NvKmsDeferredRequestFifos from
* SwapGroups using NVKMS_IOCTL_LEAVE_SWAP_GROUP (or freeing the
* NvKmsDeferredRequestFifo, or freeing the device).
*
* Once an NvKmsDeferredRequestFifo is joined to a SwapGroup, the SwapGroup will
* not become ready again until the SwapGroup member sends the
* NVKMS_DEFERRED_REQUEST_OPCODE_SWAP_GROUP_READY request through their
* NvKmsDeferredRequestFifo. The NVKMS_DEFERRED_REQUEST_SEMAPHORE_INDEX
* specified as part of the request indicates an index into
* NvKmsDeferredRequestFifo::semaphore[] where NVKMS will write
*
* NVKMS_DEFERRED_REQUEST_SEMAPHORE_VALUE_SWAP_GROUP_READY
*
* when the SwapGroup becomes ready.
*
* If unicastEvent::specified is TRUE, then unicastEvent::fd will be interpreted
* as a unicast event file descriptor. See NVKMS_IOCTL_CLEAR_UNICAST_EVENT for
* details. Whenever SWAP_GROUP_READY is written to a semaphore within
* NvKmsDeferredRequestFifo, the unicastEvent fd will be notified.
*
* An NvKmsDeferredRequestFifo can be joined to at most one SwapGroup at a time.
*
* If one client uses multiple NvKmsDeferredRequestFifos joined to multiple
* SwapGroups and wants to synchronize swaps between these fifos, it should
* bundle all of the (deviceHandle, swapGroupHandle, deferredRequestFifoHandle)
* tuples into a single join/leave request.
*
* If any client joins multiple NvKmsDeferredRequestFifos to multiple
* SwapGroups, all NVKMS_IOCTL_JOIN_SWAP_GROUP requests must specify the same
* set of SwapGroups.
*/
struct NvKmsJoinSwapGroupRequestOneMember {
NvKmsDeviceHandle deviceHandle;
NvKmsSwapGroupHandle swapGroupHandle;
NvKmsDeferredRequestFifoHandle deferredRequestFifoHandle;
struct {
int fd;
NvBool specified;
} unicastEvent;
};
struct NvKmsJoinSwapGroupRequest {
NvU32 numMembers;
struct NvKmsJoinSwapGroupRequestOneMember member[NVKMS_MAX_SWAPGROUPS];
};
struct NvKmsJoinSwapGroupReply {
NvU32 padding;
};
struct NvKmsJoinSwapGroupParams {
struct NvKmsJoinSwapGroupRequest request; /*! in */
struct NvKmsJoinSwapGroupReply reply; /*! out */
};
struct NvKmsLeaveSwapGroupRequestOneMember {
NvKmsDeviceHandle deviceHandle;
NvKmsDeferredRequestFifoHandle deferredRequestFifoHandle;
};
struct NvKmsLeaveSwapGroupRequest {
NvU32 numMembers;
struct NvKmsLeaveSwapGroupRequestOneMember member[NVKMS_MAX_SWAPGROUPS];
};
struct NvKmsLeaveSwapGroupReply {
NvU32 padding;
};
struct NvKmsLeaveSwapGroupParams {
struct NvKmsLeaveSwapGroupRequest request; /*! in */
struct NvKmsLeaveSwapGroupReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SET_SWAP_GROUP_CLIP_LIST
*
* The X driver needs to define which pixels on-screen are owned by the
* SwapGroup. NVKMS will use this to prevent those pixels from updating until
* all SwapGroup members indicate that they are ready.
*
* The clip list is interpreted by NVKMS as relative to the surface specified
* during a flip or modeset. The clip list is intersected with the ViewPortIn
* of the head, described by
*
* NvKmsFlipCommonParams::viewPortIn::point
*
* and
*
* NvKmsSetModeOneHeadRequest::viewPortSizeIn
*
* The clip list is exclusive. I.e., each NvKmsRect is a region outside of the
* SwapGroup. One surface-sized NvKmsRect would mean that there are no
* SwapGroup-owned pixels.
*
* When no clip list is specified, NVKMS behaves as if there were no
* SwapGroup-owned pixels.
*
* Only an NVKMS modeset owner can set the clip list of a SwapGroup.
*/
struct NvKmsSetSwapGroupClipListRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSwapGroupHandle swapGroupHandle;
/*! The number of struct NvKmsRects pointed to by pClipList. */
NvU16 nClips;
/*!
* Pointer to an array of struct NvKmsRects describing the inclusive clip
* list for the SwapGroup. The NvKmsRects are in desktop coordinate space.
*
* Use nvKmsPointerToNvU64() to assign pClipList.
*/
NvU64 pClipList NV_ALIGN_BYTES(8);
};
struct NvKmsSetSwapGroupClipListReply {
NvU32 padding;
};
struct NvKmsSetSwapGroupClipListParams {
struct NvKmsSetSwapGroupClipListRequest request; /*! in */
struct NvKmsSetSwapGroupClipListReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_GRANT_SWAP_GROUP:
* NVKMS_IOCTL_ACQUIRE_SWAP_GROUP:
* NVKMS_IOCTL_RELEASE_SWAP_GROUP:
*
* An NVKMS client can "grant" a swap group that it has allocated through
* NVKMS_IOCTL_ALLOC_SWAP_GROUP to another NVKMS client through the following
* steps:
*
* - The granting NVKMS client should open /dev/nvidia-modeset, and call
* NVKMS_IOCTL_GRANT_SWAP_GROUP to associate an NvKmsSwapGroupHandle
* with the file descriptor.
*
* - The granting NVKMS client should pass the file descriptor over a
* UNIX domain socket to one or more clients who should acquire the
* swap group.
*
* - The granting NVKMS client can optionally close the file
* descriptor now or later.
*
* - Each acquiring client should call NVKMS_IOCTL_ACQUIRE_SWAP_GROUP,
* and pass in the file descriptor it received. This returns an
* NvKmsSwapGroupHandle that the acquiring client can use to refer to
* the swap group in any other NVKMS API call that takes an
* NvKmsSwapGroupHandle.
*
* - The acquiring clients can optionally close the file descriptor
* now or later.
*
* - Each acquiring client should call NVKMS_IOCTL_RELEASE_SWAP_GROUP to
* release it when they are done with the swap group.
*/
struct NvKmsGrantSwapGroupRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSwapGroupHandle swapGroupHandle;
int fd;
};
struct NvKmsGrantSwapGroupReply {
NvU32 padding;
};
struct NvKmsGrantSwapGroupParams {
struct NvKmsGrantSwapGroupRequest request; /*! in */
struct NvKmsGrantSwapGroupReply reply; /*! out */
};
struct NvKmsAcquireSwapGroupRequest {
int fd;
};
struct NvKmsAcquireSwapGroupReply {
NvKmsDeviceHandle deviceHandle;
NvKmsSwapGroupHandle swapGroupHandle;
};
struct NvKmsAcquireSwapGroupParams {
struct NvKmsAcquireSwapGroupRequest request; /*! in */
struct NvKmsAcquireSwapGroupReply reply; /*! out */
};
struct NvKmsReleaseSwapGroupRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsSwapGroupHandle swapGroupHandle;
};
struct NvKmsReleaseSwapGroupReply {
NvU32 padding;
};
struct NvKmsReleaseSwapGroupParams {
struct NvKmsReleaseSwapGroupRequest request; /*! in */
struct NvKmsReleaseSwapGroupReply reply; /*! out */
};
/*!
* NVKMS_IOCTL_SWITCH_MUX:
*
* Switch the mux for the given Dpy in the given direction. The mux switch is
* performed in three stages.
*/
enum NvKmsMuxOperation {
NVKMS_SWITCH_MUX_PRE,
NVKMS_SWITCH_MUX,
NVKMS_SWITCH_MUX_POST,
};
struct NvKmsSwitchMuxRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
enum NvKmsMuxOperation operation;
NvMuxState state;
};
struct NvKmsSwitchMuxReply {
NvU32 padding;
};
struct NvKmsSwitchMuxParams {
struct NvKmsSwitchMuxRequest request;
struct NvKmsSwitchMuxReply reply;
};
struct NvKmsGetMuxStateRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NVDpyId dpyId;
};
struct NvKmsGetMuxStateReply {
NvMuxState state;
};
struct NvKmsGetMuxStateParams {
struct NvKmsGetMuxStateRequest request;
struct NvKmsGetMuxStateReply reply;
};
/*!
* NVKMS_IOCTL_EXPORT_VRR_SEMAPHORE_SURFACE:
*
* Export the VRR semaphore surface onto the provided RM 'memFd'.
* The RM memory FD should be "empty". An empty FD can be allocated by calling
* NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD with 'EMPTY_FD' set.
*/
struct NvKmsExportVrrSemaphoreSurfaceRequest {
NvKmsDeviceHandle deviceHandle;
int memFd;
};
struct NvKmsExportVrrSemaphoreSurfaceReply {
NvU32 padding;
};
struct NvKmsExportVrrSemaphoreSurfaceParams {
struct NvKmsExportVrrSemaphoreSurfaceRequest request;
struct NvKmsExportVrrSemaphoreSurfaceReply reply;
};
/*!
* NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT:
* NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT:
*
* The NVKMS client can use NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT to request a
* vblank syncpt that continuously triggers each time the raster generator
* reaches the start of vblank. NVKMS will return the syncpt id in
* 'NvKmsEnableVblankSyncObjectReply::syncptId'.
*
* The NVKMS client can use NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT to disable
* the vblank syncpt.
*
* If a vblank syncpt is currently enabled on a head, and a modeset request is
* issued to reconfigure that head with a new set of mode timings, NVKMS will
* automatically reenable the vblank syncpt so it continues to trigger with the
* new mode timings.
*
* Clients can use these IOCTLs only if both NvKmsAllocDeviceReply::
* supportsVblankSyncObjects and NvKmsAllocDeviceReply::supportsSyncpts are
* TRUE.
*/
struct NvKmsEnableVblankSyncObjectRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvU32 head;
};
struct NvKmsEnableVblankSyncObjectReply {
/*
* Clients should explicitly disable the vblank sync object to consume the
* handle.
*/
NvKmsVblankSyncObjectHandle vblankHandle;
NvU32 syncptId;
};
struct NvKmsEnableVblankSyncObjectParams {
struct NvKmsEnableVblankSyncObjectRequest request; /*! in */
struct NvKmsEnableVblankSyncObjectReply reply; /*! out */
};
struct NvKmsDisableVblankSyncObjectRequest {
NvKmsDeviceHandle deviceHandle;
NvKmsDispHandle dispHandle;
NvU32 head;
/* This handle is received in NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT. */
NvKmsVblankSyncObjectHandle vblankHandle;
};
struct NvKmsDisableVblankSyncObjectReply {
NvU32 padding;
};
struct NvKmsDisableVblankSyncObjectParams {
struct NvKmsDisableVblankSyncObjectRequest request; /*! in */
struct NvKmsDisableVblankSyncObjectReply reply; /*! out */
};
#endif /* NVKMS_API_H */
07070100000022000081A4000000000000000000000001663926A700000789000000000000000000000000000000000000003F00000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvkms-kapi-private.h/*
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#if !defined(__NVKMS_KAPI_PRIVATE_H__)
#define __NVKMS_KAPI_PRIVATE_H__
#include "nvtypes.h"
#include "nvkms-api.h"
struct NvKmsKapiPrivAllocateChannelEventParams {
NvU32 hClient;
NvU32 hChannel;
};
struct NvKmsKapiPrivSurfaceParams {
enum NvKmsSurfaceMemoryLayout layout;
struct {
struct {
NvU32 x;
NvU32 y;
NvU32 z;
} log2GobsPerBlock;
NvU32 pitchInBlocks;
NvBool genericMemory;
} blockLinear;
};
struct NvKmsKapiPrivImportMemoryParams {
int memFd;
struct NvKmsKapiPrivSurfaceParams surfaceParams;
};
struct NvKmsKapiPrivExportMemoryParams {
int memFd;
};
#endif /* !defined(__NVKMS_KAPI_PRIVATE_H__) */
07070100000023000081A4000000000000000000000001663926A7000006CF000000000000000000000000000000000000003500000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvlimits.h/*
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: nvlimits.finn
//
/*
* This is the maximum number of GPUs supported in a single system.
*/
#define NV_MAX_DEVICES 32
/*
* This is the maximum number of subdevices within a single device.
*/
#define NV_MAX_SUBDEVICES 8
/*
* This is the maximum length of the process name string.
*/
#define NV_PROC_NAME_MAX_LENGTH 100U
/*
* This is the maximum number of heads per GPU.
*/
#define NV_MAX_HEADS 4
07070100000024000081A4000000000000000000000001663926A700009A54000000000000000000000000000000000000003300000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvmisc.h/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* nvmisc.h
*/
#ifndef __NV_MISC_H
#define __NV_MISC_H
#ifdef __cplusplus
extern "C" {
#endif //__cplusplus
#include "nvtypes.h"
#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS)
//
// Miscellaneous macros useful for bit field manipulations
//
// STUPID HACK FOR CL 19434692. Will revert when fix CL is delivered bfm -> chips_a.
#ifndef BIT
#define BIT(b) (1U<<(b))
#endif
#ifndef BIT32
#define BIT32(b) ((NvU32)1U<<(b))
#endif
#ifndef BIT64
#define BIT64(b) ((NvU64)1U<<(b))
#endif
#endif
//
// It is recommended to use the following bit macros to avoid macro name
// collisions with other src code bases.
//
#ifndef NVBIT
#define NVBIT(b) (1U<<(b))
#endif
#ifndef NVBIT_TYPE
#define NVBIT_TYPE(b, t) (((t)1U)<<(b))
#endif
#ifndef NVBIT32
#define NVBIT32(b) NVBIT_TYPE(b, NvU32)
#endif
#ifndef NVBIT64
#define NVBIT64(b) NVBIT_TYPE(b, NvU64)
#endif
// Helper macro's for 32 bit bitmasks
#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3)
#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5)
#define NV_BITMASK32_OFFSET(chId) ((chId) & (0x1F))
#define NV_BITMASK32_SET(pChannelMask, chId) \
(pChannelMask)[NV_BITMASK32_IDX(chId)] |= NVBIT(NV_BITMASK32_OFFSET(chId))
#define NV_BITMASK32_GET(pChannelMask, chId) \
((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId)))
// Index of the 'on' bit (assuming that there is only one).
// Even if multiple bits are 'on', result is in range of 0-31.
#define BIT_IDX_32(n) \
(((((n) & 0xFFFF0000U) != 0U) ? 0x10U: 0U) | \
((((n) & 0xFF00FF00U) != 0U) ? 0x08U: 0U) | \
((((n) & 0xF0F0F0F0U) != 0U) ? 0x04U: 0U) | \
((((n) & 0xCCCCCCCCU) != 0U) ? 0x02U: 0U) | \
((((n) & 0xAAAAAAAAU) != 0U) ? 0x01U: 0U) )
// Index of the 'on' bit (assuming that there is only one).
// Even if multiple bits are 'on', result is in range of 0-63.
#define BIT_IDX_64(n) \
(((((n) & 0xFFFFFFFF00000000ULL) != 0U) ? 0x20U: 0U) | \
((((n) & 0xFFFF0000FFFF0000ULL) != 0U) ? 0x10U: 0U) | \
((((n) & 0xFF00FF00FF00FF00ULL) != 0U) ? 0x08U: 0U) | \
((((n) & 0xF0F0F0F0F0F0F0F0ULL) != 0U) ? 0x04U: 0U) | \
((((n) & 0xCCCCCCCCCCCCCCCCULL) != 0U) ? 0x02U: 0U) | \
((((n) & 0xAAAAAAAAAAAAAAAAULL) != 0U) ? 0x01U: 0U) )
/*!
* DRF MACRO README:
*
* Glossary:
* DRF: Device, Register, Field
* FLD: Field
* REF: Reference
*
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA 0xDEADBEEF
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_GAMMA 27:0
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA 31:28
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ZERO 0x00000000
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ONE 0x00000001
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_TWO 0x00000002
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_THREE 0x00000003
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FOUR 0x00000004
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FIVE 0x00000005
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SIX 0x00000006
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SEVEN 0x00000007
*
*
* Device = _DEVICE_OMEGA
* This is the common "base" that a group of registers in a manual share
*
* Register = _REGISTER_ALPHA
* Register for a given block of defines is the common root for one or more fields and constants
*
* Field(s) = _FIELD_GAMMA, _FIELD_ZETA
* These are the bit ranges for a given field within the register
* Fields are not required to have defined constant values (enumerations)
*
* Constant(s) = _ZERO, _ONE, _TWO, ...
* These are named values (enums) a field can contain; the width of the constants should not be larger than the field width
*
* MACROS:
*
* DRF_SHIFT:
* Bit index of the lower bound of a field
* DRF_SHIFT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 28
*
* DRF_SHIFT_RT:
* Bit index of the higher bound of a field
* DRF_SHIFT_RT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 31
*
* DRF_MASK:
* Produces a mask of 1-s equal to the width of a field
* DRF_MASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF (four 1s starting at bit 0)
*
* DRF_SHIFTMASK:
* Produces a mask of 1s equal to the width of a field at the location of the field
* DRF_SHIFTMASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF0000000
*
* DRF_DEF:
* Shifts a field constant's value to the correct field offset
* DRF_DEF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE) == 0x30000000
*
* DRF_NUM:
* Shifts a number to the location of a particular field
* DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 3) == 0x30000000
* NOTE: If the value passed in is wider than the field, the value's high bits will be truncated
*
* DRF_SIZE:
* Provides the width of the field in bits
* DRF_SIZE(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 4
*
* DRF_VAL:
* Provides the value of an input within the field specified
* DRF_VAL(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xABCD1234) == 0xA
* This is sort of like the inverse of DRF_NUM
*
* DRF_IDX...:
* These macros are similar to the above but for fields that accept an index argumment
*
* FLD_SET_DRF:
* Set the field bits in a given value with the given field constant
* NvU32 x = 0x00001234;
* x = FLD_SET_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, x);
* x == 0x30001234;
*
* FLD_SET_DRF_NUM:
* Same as FLD_SET_DRF but instead of using a field constant a literal/variable is passed in
* NvU32 x = 0x00001234;
* x = FLD_SET_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xF, x);
* x == 0xF0001234;
*
* FLD_IDX...:
* These macros are similar to the above but for fields that accept an index argumment
*
* FLD_TEST_DRF:
* Test if location specified by drf in 'v' has the same value as NV_drfc
* FLD_TEST_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE
*
* FLD_TEST_DRF_NUM:
* Test if locations specified by drf in 'v' have the same value as n
* FLD_TEST_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0x3, 0x3000ABCD) == NV_TRUE
*
* REF_DEF:
* Like DRF_DEF but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
* REF_DEF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE) == 0x30000000
*
* REF_VAL:
* Like DRF_VAL but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
* REF_VAL(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xABCD1234) == 0xA
*
* REF_NUM:
* Like DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
* REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xA) == 0xA00000000
*
* FLD_SET_REF_NUM:
* Like FLD_SET_DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
* NvU32 x = 0x00001234;
* x = FLD_SET_REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xF, x);
* x == 0xF0001234;
*
* FLD_TEST_REF:
* Like FLD_TEST_DRF but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
* FLD_TEST_REF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE
*
* Other macros:
* There a plethora of other macros below that extend the above (notably Multi-Word (MW), 64-bit, and some
* reg read/write variations). I hope these are self explanatory. If you have a need to use them, you
* probably have some knowledge of how they work.
*/
// tegra mobile uses nvmisc_macros.h and can't access nvmisc.h... and sometimes both get included.
#ifndef _NVMISC_MACROS_H
// Use Coverity Annotation to mark issues as false positives/ignore when using single bit defines.
#define DRF_ISBIT(bitval,drf) \
( /* coverity[identical_branches] */ \
(bitval != 0) ? drf )
#define DEVICE_BASE(d) (0?d) // what's up with this name? totally non-parallel to the macros below
#define DEVICE_EXTENT(d) (1?d) // what's up with this name? totally non-parallel to the macros below
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
#ifdef MISRA_14_3
#define DRF_BASE(drf) (drf##_LOW_FIELD)
#define DRF_EXTENT(drf) (drf##_HIGH_FIELD)
#define DRF_SHIFT(drf) ((drf##_LOW_FIELD) % 32U)
#define DRF_SHIFT_RT(drf) ((drf##_HIGH_FIELD) % 32U)
#define DRF_MASK(drf) (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U)))
#else
#define DRF_BASE(drf) (NV_FALSE?drf) // much better
#define DRF_EXTENT(drf) (NV_TRUE?drf) // much better
#define DRF_SHIFT(drf) (((NvU32)DRF_BASE(drf)) % 32U)
#define DRF_SHIFT_RT(drf) (((NvU32)DRF_EXTENT(drf)) % 32U)
#define DRF_MASK(drf) (0xFFFFFFFFU>>(31U - DRF_SHIFT_RT(drf) + DRF_SHIFT(drf)))
#endif
#define DRF_DEF(d,r,f,c) (((NvU32)(NV ## d ## r ## f ## c))<<DRF_SHIFT(NV ## d ## r ## f))
#define DRF_NUM(d,r,f,n) ((((NvU32)(n))&DRF_MASK(NV ## d ## r ## f))<<DRF_SHIFT(NV ## d ## r ## f))
#else
#define DRF_BASE(drf) (0?drf) // much better
#define DRF_EXTENT(drf) (1?drf) // much better
#define DRF_SHIFT(drf) ((DRF_ISBIT(0,drf)) % 32)
#define DRF_SHIFT_RT(drf) ((DRF_ISBIT(1,drf)) % 32)
#define DRF_MASK(drf) (0xFFFFFFFFU>>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32)))
#define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV ## d ## r ## f))
#define DRF_NUM(d,r,f,n) (((n)&DRF_MASK(NV ## d ## r ## f))<<DRF_SHIFT(NV ## d ## r ## f))
#endif
#define DRF_SHIFTMASK(drf) (DRF_MASK(drf)<<(DRF_SHIFT(drf)))
#define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1U)
#define DRF_VAL(d,r,f,v) (((v)>>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f))
#endif
// Signed version of DRF_VAL, which takes care of extending sign bit.
#define DRF_VAL_SIGNED(d,r,f,v) (((DRF_VAL(d,r,f,(v)) ^ (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U)))) - (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U)))
#define DRF_IDX_DEF(d,r,f,i,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV##d##r##f(i)))
#define DRF_IDX_OFFSET_DEF(d,r,f,i,o,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV##d##r##f(i,o)))
#define DRF_IDX_NUM(d,r,f,i,n) (((n)&DRF_MASK(NV##d##r##f(i)))<<DRF_SHIFT(NV##d##r##f(i)))
#define DRF_IDX_VAL(d,r,f,i,v) (((v)>>DRF_SHIFT(NV##d##r##f(i)))&DRF_MASK(NV##d##r##f(i)))
#define DRF_IDX_OFFSET_VAL(d,r,f,i,o,v) (((v)>>DRF_SHIFT(NV##d##r##f(i,o)))&DRF_MASK(NV##d##r##f(i,o)))
// Fractional version of DRF_VAL which reads Fx.y fixed point number (x.y)*z
#define DRF_VAL_FRAC(d,r,x,y,v,z) ((DRF_VAL(d,r,x,(v))*z) + ((DRF_VAL(d,r,y,v)*z) / (1<<DRF_SIZE(NV##d##r##y))))
//
// 64 Bit Versions
//
#define DRF_SHIFT64(drf) ((DRF_ISBIT(0,drf)) % 64)
#define DRF_MASK64(drf) (NV_U64_MAX>>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64)))
#define DRF_SHIFTMASK64(drf) (DRF_MASK64(drf)<<(DRF_SHIFT64(drf)))
#define DRF_DEF64(d,r,f,c) (((NvU64)(NV ## d ## r ## f ## c))<<DRF_SHIFT64(NV ## d ## r ## f))
#define DRF_NUM64(d,r,f,n) ((((NvU64)(n))&DRF_MASK64(NV ## d ## r ## f))<<DRF_SHIFT64(NV ## d ## r ## f))
#define DRF_VAL64(d,r,f,v) ((((NvU64)(v))>>DRF_SHIFT64(NV ## d ## r ## f))&DRF_MASK64(NV ## d ## r ## f))
#define DRF_VAL_SIGNED64(d,r,f,v) (((DRF_VAL64(d,r,f,(v)) ^ (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))) - (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))
#define DRF_IDX_DEF64(d,r,f,i,c) (((NvU64)(NV ## d ## r ## f ## c))<<DRF_SHIFT64(NV##d##r##f(i)))
#define DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c) ((NvU64)(NV ## d ## r ## f ## c)<<DRF_SHIFT64(NV##d##r##f(i,o)))
#define DRF_IDX_NUM64(d,r,f,i,n) ((((NvU64)(n))&DRF_MASK64(NV##d##r##f(i)))<<DRF_SHIFT64(NV##d##r##f(i)))
#define DRF_IDX_VAL64(d,r,f,i,v) ((((NvU64)(v))>>DRF_SHIFT64(NV##d##r##f(i)))&DRF_MASK64(NV##d##r##f(i)))
#define DRF_IDX_OFFSET_VAL64(d,r,f,i,o,v) (((NvU64)(v)>>DRF_SHIFT64(NV##d##r##f(i,o)))&DRF_MASK64(NV##d##r##f(i,o)))
#define FLD_SET_DRF64(d,r,f,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c))
#define FLD_SET_DRF_NUM64(d,r,f,n,v) ((((NvU64)(v)) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_NUM64(d,r,f,n))
#define FLD_IDX_SET_DRF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c))
#define FLD_IDX_OFFSET_SET_DRF64(d,r,f,i,o,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c))
#define FLD_IDX_SET_DRF_DEF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c))
#define FLD_IDX_SET_DRF_NUM64(d,r,f,i,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_NUM64(d,r,f,i,n))
#define FLD_SET_DRF_IDX64(d,r,f,c,i,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c(i)))
#define FLD_TEST_DRF64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) == NV##d##r##f##c)
#define FLD_TEST_DRF_AND64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) & NV##d##r##f##c)
#define FLD_TEST_DRF_NUM64(d,r,f,n,v) (DRF_VAL64(d, r, f, (v)) == (n))
#define FLD_IDX_TEST_DRF64(d,r,f,i,c,v) (DRF_IDX_VAL64(d, r, f, i, (v)) == NV##d##r##f##c)
#define FLD_IDX_OFFSET_TEST_DRF64(d,r,f,i,o,c,v) (DRF_IDX_OFFSET_VAL64(d, r, f, i, o, (v)) == NV##d##r##f##c)
#define REF_DEF64(drf,d) (((drf ## d)&DRF_MASK64(drf))<<DRF_SHIFT64(drf))
#define REF_VAL64(drf,v) (((NvU64)(v)>>DRF_SHIFT64(drf))&DRF_MASK64(drf))
#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3)
#define REF_NUM64(drf,n) (((NvU64)(n)&(0xFFFFFFFFFFFFFFFFU>>(63U-((drf##_HIGH_FIELD) % 63U)+((drf##_LOW_FIELD) % 63U)))) << ((drf##_LOW_FIELD) % 63U))
#else
#define REF_NUM64(drf,n) (((NvU64)(n)&DRF_MASK64(drf))<<DRF_SHIFT64(drf))
#endif
#define FLD_TEST_REF64(drf,c,v) (REF_VAL64(drf, v) == drf##c)
#define FLD_TEST_REF_AND64(drf,c,v) (REF_VAL64(drf, v) & drf##c)
#define FLD_SET_REF_NUM64(drf,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(drf)) | REF_NUM64(drf,n))
//
// 32 Bit Versions
//
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
#define FLD_SET_DRF(d,r,f,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c))
#define FLD_SET_DRF_NUM(d,r,f,n,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_NUM(d,r,f,n))
#define FLD_IDX_SET_DRF(d,r,f,i,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
#define FLD_IDX_OFFSET_SET_DRF(d,r,f,i,o,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF(d,r,f,i,o,c))
#define FLD_IDX_SET_DRF_DEF(d,r,f,i,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
#define FLD_IDX_SET_DRF_NUM(d,r,f,i,n,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_NUM(d,r,f,i,n))
#define FLD_SET_DRF_IDX(d,r,f,c,i,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c(i)))
#define FLD_TEST_DRF(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) == (NvU32)(NV##d##r##f##c)))
#define FLD_TEST_DRF_AND(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) & (NvU32)(NV##d##r##f##c)) != 0U)
#define FLD_TEST_DRF_NUM(d,r,f,n,v) ((DRF_VAL(d, r, f, (v)) == (NvU32)(n)))
#define FLD_IDX_TEST_DRF(d,r,f,i,c,v) ((DRF_IDX_VAL(d, r, f, i, (v)) == (NvU32)(NV##d##r##f##c)))
#define FLD_IDX_OFFSET_TEST_DRF(d,r,f,i,o,c,v) ((DRF_IDX_OFFSET_VAL(d, r, f, i, o, (v)) == (NvU32)(NV##d##r##f##c)))
#else
#define FLD_SET_DRF(d,r,f,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c))
#define FLD_SET_DRF_NUM(d,r,f,n,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_NUM(d,r,f,n))
#define FLD_IDX_SET_DRF(d,r,f,i,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
#define FLD_IDX_OFFSET_SET_DRF(d,r,f,i,o,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF(d,r,f,i,o,c))
#define FLD_IDX_SET_DRF_DEF(d,r,f,i,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
#define FLD_IDX_SET_DRF_NUM(d,r,f,i,n,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_NUM(d,r,f,i,n))
#define FLD_SET_DRF_IDX(d,r,f,c,i,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c(i)))
#define FLD_TEST_DRF(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) == NV##d##r##f##c))
#define FLD_TEST_DRF_AND(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) & NV##d##r##f##c))
#define FLD_TEST_DRF_NUM(d,r,f,n,v) ((DRF_VAL(d, r, f, (v)) == (n)))
#define FLD_IDX_TEST_DRF(d,r,f,i,c,v) ((DRF_IDX_VAL(d, r, f, i, (v)) == NV##d##r##f##c))
#define FLD_IDX_OFFSET_TEST_DRF(d,r,f,i,o,c,v) ((DRF_IDX_OFFSET_VAL(d, r, f, i, o, (v)) == NV##d##r##f##c))
#endif
#define REF_DEF(drf,d) (((drf ## d)&DRF_MASK(drf))<<DRF_SHIFT(drf))
#define REF_VAL(drf,v) (((v)>>DRF_SHIFT(drf))&DRF_MASK(drf))
#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3)
#define REF_NUM(drf,n) (((n)&(0xFFFFFFFFU>>(31U-((drf##_HIGH_FIELD) % 32U)+((drf##_LOW_FIELD) % 32U)))) << ((drf##_LOW_FIELD) % 32U))
#else
#define REF_NUM(drf,n) (((n)&DRF_MASK(drf))<<DRF_SHIFT(drf))
#endif
#define FLD_TEST_REF(drf,c,v) (REF_VAL(drf, (v)) == drf##c)
#define FLD_TEST_REF_AND(drf,c,v) (REF_VAL(drf, (v)) & drf##c)
#define FLD_SET_REF_NUM(drf,n,v) (((v) & ~DRF_SHIFTMASK(drf)) | REF_NUM(drf,n))
#define CR_DRF_DEF(d,r,f,c) ((CR ## d ## r ## f ## c)<<DRF_SHIFT(CR ## d ## r ## f))
#define CR_DRF_NUM(d,r,f,n) (((n)&DRF_MASK(CR ## d ## r ## f))<<DRF_SHIFT(CR ## d ## r ## f))
#define CR_DRF_VAL(d,r,f,v) (((v)>>DRF_SHIFT(CR ## d ## r ## f))&DRF_MASK(CR ## d ## r ## f))
// Multi-word (MW) field manipulations. For multi-word structures (e.g., Fermi SPH),
// fields may have bit numbers beyond 32. To avoid errors using "classic" multi-word macros,
// all the field extents are defined as "MW(X)". For example, MW(127:96) means
// the field is in bits 0-31 of word number 3 of the structure.
//
// DRF_VAL_MW() macro is meant to be used for native endian 32-bit aligned 32-bit word data,
// not for byte stream data.
//
// DRF_VAL_BS() macro is for byte stream data used in fbQueryBIOS_XXX().
//
#define DRF_EXPAND_MW(drf) drf // used to turn "MW(a:b)" into "a:b"
#define DRF_PICK_MW(drf,v) ((v)? DRF_EXPAND_##drf) // picks low or high bits
#define DRF_WORD_MW(drf) (DRF_PICK_MW(drf,0)/32) // which word in a multi-word array
#define DRF_BASE_MW(drf) (DRF_PICK_MW(drf,0)%32) // which start bit in the selected word?
#define DRF_EXTENT_MW(drf) (DRF_PICK_MW(drf,1)%32) // which end bit in the selected word
#define DRF_SHIFT_MW(drf) (DRF_PICK_MW(drf,0)%32)
#define DRF_MASK_MW(drf) (0xFFFFFFFFU>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32))
#define DRF_SHIFTMASK_MW(drf) ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf)))
#define DRF_SIZE_MW(drf) (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1)
#define DRF_DEF_MW(d,r,f,c) ((NV##d##r##f##c) << DRF_SHIFT_MW(NV##d##r##f))
#define DRF_NUM_MW(d,r,f,n) (((n)&DRF_MASK_MW(NV##d##r##f))<<DRF_SHIFT_MW(NV##d##r##f))
//
// DRF_VAL_MW is the ONLY multi-word macro which supports spanning. No other MW macro supports spanning currently
//
#define DRF_VAL_MW_1WORD(d,r,f,v) ((((v)[DRF_WORD_MW(NV##d##r##f)])>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f))
#define DRF_SPANS(drf) ((DRF_PICK_MW(drf,0)/32) != (DRF_PICK_MW(drf,1)/32))
#define DRF_WORD_MW_LOW(drf) (DRF_PICK_MW(drf,0)/32)
#define DRF_WORD_MW_HIGH(drf) (DRF_PICK_MW(drf,1)/32)
#define DRF_MASK_MW_LOW(drf) (0xFFFFFFFFU)
#define DRF_MASK_MW_HIGH(drf) (0xFFFFFFFFU>>(31-(DRF_EXTENT_MW(drf))))
#define DRF_SHIFT_MW_LOW(drf) (DRF_PICK_MW(drf,0)%32)
#define DRF_SHIFT_MW_HIGH(drf) (0)
#define DRF_MERGE_SHIFT(drf) ((32-((DRF_PICK_MW(drf,0)%32)))%32)
#define DRF_VAL_MW_2WORD(d,r,f,v) (((((v)[DRF_WORD_MW_LOW(NV##d##r##f)])>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \
(((((v)[DRF_WORD_MW_HIGH(NV##d##r##f)])>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f)))
#define DRF_VAL_MW(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_MW_2WORD(d,r,f,v) : DRF_VAL_MW_1WORD(d,r,f,v) )
#define DRF_IDX_DEF_MW(d,r,f,i,c) ((NV##d##r##f##c)<<DRF_SHIFT_MW(NV##d##r##f(i)))
#define DRF_IDX_NUM_MW(d,r,f,i,n) (((n)&DRF_MASK_MW(NV##d##r##f(i)))<<DRF_SHIFT_MW(NV##d##r##f(i)))
#define DRF_IDX_VAL_MW(d,r,f,i,v) ((((v)[DRF_WORD_MW(NV##d##r##f(i))])>>DRF_SHIFT_MW(NV##d##r##f(i)))&DRF_MASK_MW(NV##d##r##f(i)))
//
// Logically OR all DRF_DEF constants indexed from zero to s (semiinclusive).
// Caution: Target variable v must be pre-initialized.
//
#define FLD_IDX_OR_DRF_DEF(d,r,f,c,s,v) \
do \
{ NvU32 idx; \
for (idx = 0; idx < (NV ## d ## r ## f ## s); ++idx)\
{ \
v |= DRF_IDX_DEF(d,r,f,idx,c); \
} \
} while(0)
#define FLD_MERGE_MW(drf,n,v) (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n)
#define FLD_ASSIGN_MW(drf,n,v) ((v)[DRF_WORD_MW(drf)] = FLD_MERGE_MW(drf, n, v))
#define FLD_IDX_MERGE_MW(drf,i,n,v) (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n)
#define FLD_IDX_ASSIGN_MW(drf,i,n,v) ((v)[DRF_WORD_MW(drf(i))] = FLD_MERGE_MW(drf(i), n, v))
#define FLD_SET_DRF_MW(d,r,f,c,v) FLD_MERGE_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v)
#define FLD_SET_DRF_NUM_MW(d,r,f,n,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_NUM_MW(d,r,f,n), v)
#define FLD_SET_DRF_DEF_MW(d,r,f,c,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v)
#define FLD_IDX_SET_DRF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v)
#define FLD_IDX_SET_DRF_DEF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v)
#define FLD_IDX_SET_DRF_NUM_MW(d,r,f,i,n,v) FLD_IDX_ASSIGN_MW(NV##d##r##f, i, DRF_IDX_NUM_MW(d,r,f,i,n), v)
#define FLD_TEST_DRF_MW(d,r,f,c,v) ((DRF_VAL_MW(d, r, f, (v)) == NV##d##r##f##c))
#define FLD_TEST_DRF_NUM_MW(d,r,f,n,v) ((DRF_VAL_MW(d, r, f, (v)) == n))
#define FLD_IDX_TEST_DRF_MW(d,r,f,i,c,v) ((DRF_IDX_VAL_MW(d, r, f, i, (v)) == NV##d##r##f##c))
#define DRF_VAL_BS(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_BS_2WORD(d,r,f,(v)) : DRF_VAL_BS_1WORD(d,r,f,(v)) )
//------------------------------------------------------------------------//
// //
// Common defines for engine register reference wrappers //
// //
// New engine addressing can be created like: //
// \#define ENG_REG_PMC(o,d,r) NV##d##r //
// \#define ENG_IDX_REG_CE(o,d,i,r) CE_MAP(o,r,i) //
// //
// See FB_FBPA* for more examples //
//------------------------------------------------------------------------//
#define ENG_RD_REG(g,o,d,r) GPU_REG_RD32(g, ENG_REG##d(o,d,r))
#define ENG_WR_REG(g,o,d,r,v) GPU_REG_WR32(g, ENG_REG##d(o,d,r), (v))
#define ENG_RD_DRF(g,o,d,r,f) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
#define ENG_WR_DRF_DEF(g,o,d,r,f,c) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<<GPU_DRF_SHIFT(NV##d##r##f)))|GPU_DRF_DEF(d,r,f,c))
#define ENG_WR_DRF_NUM(g,o,d,r,f,n) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<<GPU_DRF_SHIFT(NV##d##r##f)))|GPU_DRF_NUM(d,r,f,n))
#define ENG_TEST_DRF_DEF(g,o,d,r,f,c) (ENG_RD_DRF(g, o, d, r, f) == NV##d##r##f##c)
#define ENG_RD_IDX_DRF(g,o,d,r,f,i) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
#define ENG_TEST_IDX_DRF_DEF(g,o,d,r,f,c,i) (ENG_RD_IDX_DRF(g, o, d, r, f, (i)) == NV##d##r##f##c)
#define ENG_IDX_RD_REG(g,o,d,i,r) GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))
#define ENG_IDX_WR_REG(g,o,d,i,r,v) GPU_REG_WR32(g, ENG_IDX_REG##d(o,d,i,r), (v))
#define ENG_IDX_RD_DRF(g,o,d,i,r,f) ((GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
//
// DRF_READ_1WORD_BS() and DRF_READ_1WORD_BS_HIGH() do not read beyond the bytes that contain
// the requested value. Reading beyond the actual data causes a page fault panic when the
// immediately following page happened to be protected or not mapped.
//
#define DRF_VAL_BS_1WORD(d,r,f,v) ((DRF_READ_1WORD_BS(d,r,f,v)>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f))
#define DRF_VAL_BS_2WORD(d,r,f,v) (((DRF_READ_4BYTE_BS(NV##d##r##f,v)>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \
(((DRF_READ_1WORD_BS_HIGH(d,r,f,v)>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f)))
#define DRF_READ_1BYTE_BS(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4]))
#define DRF_READ_2BYTE_BS(drf,v) (DRF_READ_1BYTE_BS(drf,v)| \
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+1])<<8))
#define DRF_READ_3BYTE_BS(drf,v) (DRF_READ_2BYTE_BS(drf,v)| \
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+2])<<16))
#define DRF_READ_4BYTE_BS(drf,v) (DRF_READ_3BYTE_BS(drf,v)| \
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+3])<<24))
#define DRF_READ_1BYTE_BS_HIGH(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4]))
#define DRF_READ_2BYTE_BS_HIGH(drf,v) (DRF_READ_1BYTE_BS_HIGH(drf,v)| \
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+1])<<8))
#define DRF_READ_3BYTE_BS_HIGH(drf,v) (DRF_READ_2BYTE_BS_HIGH(drf,v)| \
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+2])<<16))
#define DRF_READ_4BYTE_BS_HIGH(drf,v) (DRF_READ_3BYTE_BS_HIGH(drf,v)| \
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+3])<<24))
// Calculate 2^n - 1 and avoid shift counter overflow
//
// On Windows amd64, 64 << 64 => 1
//
#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1)
#define DRF_READ_1WORD_BS(d,r,f,v) \
((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \
((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \
((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS(NV##d##r##f,(v)): \
DRF_READ_4BYTE_BS(NV##d##r##f,(v)))))
#define DRF_READ_1WORD_BS_HIGH(d,r,f,v) \
((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS_HIGH(NV##d##r##f,(v)): \
((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS_HIGH(NV##d##r##f,(v)): \
((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS_HIGH(NV##d##r##f,(v)): \
DRF_READ_4BYTE_BS_HIGH(NV##d##r##f,(v)))))
#define LOWESTBIT(x) ( (x) & (((x) - 1U) ^ (x)) )
// Destructive operation on n32
#define HIGHESTBIT(n32) \
{ \
HIGHESTBITIDX_32(n32); \
n32 = NVBIT(n32); \
}
#define ONEBITSET(x) ( ((x) != 0U) && (((x) & ((x) - 1U)) == 0U) )
// Destructive operation on n32
#define NUMSETBITS_32(n32) \
{ \
n32 = n32 - ((n32 >> 1) & 0x55555555); \
n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \
n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \
}
/*!
* Calculate number of bits set in a 32-bit unsigned integer.
* Pure typesafe alternative to @ref NUMSETBITS_32.
*/
static NV_FORCEINLINE NvU32
nvPopCount32(const NvU32 x)
{
NvU32 temp = x;
temp = temp - ((temp >> 1) & 0x55555555U);
temp = (temp & 0x33333333U) + ((temp >> 2) & 0x33333333U);
temp = (((temp + (temp >> 4)) & 0x0F0F0F0FU) * 0x01010101U) >> 24;
return temp;
}
/*!
* Calculate number of bits set in a 64-bit unsigned integer.
*/
static NV_FORCEINLINE NvU32
nvPopCount64(const NvU64 x)
{
NvU64 temp = x;
temp = temp - ((temp >> 1) & 0x5555555555555555ULL);
temp = (temp & 0x3333333333333333ULL) + ((temp >> 2) & 0x3333333333333333ULL);
temp = (temp + (temp >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
temp = (temp * 0x0101010101010101ULL) >> 56;
return (NvU32)temp;
}
/*!
* Determine how many bits are set below a bit index within a mask.
* This assigns a dense ordering to the set bits in the mask.
*
* For example the mask 0xCD contains 5 set bits:
* nvMaskPos32(0xCD, 0) == 0
* nvMaskPos32(0xCD, 2) == 1
* nvMaskPos32(0xCD, 3) == 2
* nvMaskPos32(0xCD, 6) == 3
* nvMaskPos32(0xCD, 7) == 4
*/
static NV_FORCEINLINE NvU32
nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
{
return nvPopCount32(mask & (NVBIT32(bitIdx) - 1U));
}
// Destructive operation on n32
#define LOWESTBITIDX_32(n32) \
{ \
n32 = BIT_IDX_32(LOWESTBIT(n32));\
}
// Destructive operation on n32
#define HIGHESTBITIDX_32(n32) \
{ \
NvU32 count = 0; \
while (n32 >>= 1) \
{ \
count++; \
} \
n32 = count; \
}
// Destructive operation on n32
#define ROUNDUP_POW2(n32) \
{ \
n32--; \
n32 |= n32 >> 1; \
n32 |= n32 >> 2; \
n32 |= n32 >> 4; \
n32 |= n32 >> 8; \
n32 |= n32 >> 16; \
n32++; \
}
/*!
* Round up a 32-bit unsigned integer to the next power of 2.
* Pure typesafe alternative to @ref ROUNDUP_POW2.
*
* param[in] x must be in range [0, 2^31] to avoid overflow.
*/
static NV_FORCEINLINE NvU32
nvNextPow2_U32(const NvU32 x)
{
NvU32 y = x;
y--;
y |= y >> 1;
y |= y >> 2;
y |= y >> 4;
y |= y >> 8;
y |= y >> 16;
y++;
return y;
}
static NV_FORCEINLINE NvU32
nvPrevPow2_U32(const NvU32 x )
{
NvU32 y = x;
y |= (y >> 1);
y |= (y >> 2);
y |= (y >> 4);
y |= (y >> 8);
y |= (y >> 16);
return y - (y >> 1);
}
static NV_FORCEINLINE NvU64
nvPrevPow2_U64(const NvU64 x )
{
NvU64 y = x;
y |= (y >> 1);
y |= (y >> 2);
y |= (y >> 4);
y |= (y >> 8);
y |= (y >> 16);
y |= (y >> 32);
return y - (y >> 1);
}
// Destructive operation on n64
#define ROUNDUP_POW2_U64(n64) \
{ \
n64--; \
n64 |= n64 >> 1; \
n64 |= n64 >> 2; \
n64 |= n64 >> 4; \
n64 |= n64 >> 8; \
n64 |= n64 >> 16; \
n64 |= n64 >> 32; \
n64++; \
}
#define NV_SWAP_U8(a,b) \
{ \
NvU8 temp; \
temp = a; \
a = b; \
b = temp; \
}
#define NV_SWAP_U32(a,b) \
{ \
NvU32 temp; \
temp = a; \
a = b; \
b = temp; \
}
/*!
* @brief Macros allowing simple iteration over bits set in a given mask.
*
* @param[in] maskWidth bit-width of the mask (allowed: 8, 16, 32, 64)
*
* @param[in,out] index lvalue that is used as a bit index in the loop
* (can be declared as any NvU* or NvS* variable)
* @param[in] mask expression, loop will iterate over set bits only
*/
#define FOR_EACH_INDEX_IN_MASK(maskWidth,index,mask) \
{ \
NvU##maskWidth lclMsk = (NvU##maskWidth)(mask); \
for ((index) = 0U; lclMsk != 0U; (index)++, lclMsk >>= 1U)\
{ \
if (((NvU##maskWidth)NVBIT64(0) & lclMsk) == 0U) \
{ \
continue; \
}
#define FOR_EACH_INDEX_IN_MASK_END \
} \
}
//
// Size to use when declaring variable-sized arrays
//
#define NV_ANYSIZE_ARRAY 1
//
// Returns ceil(a/b)
//
#define NV_CEIL(a,b) (((a)+(b)-1)/(b))
// Clearer name for NV_CEIL
#ifndef NV_DIV_AND_CEIL
#define NV_DIV_AND_CEIL(a, b) NV_CEIL(a,b)
#endif
#ifndef NV_MIN
#define NV_MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef NV_MAX
#define NV_MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
//
// Returns absolute value of provided integer expression
//
#define NV_ABS(a) ((a)>=0?(a):(-(a)))
//
// Returns 1 if input number is positive, 0 if 0 and -1 if negative. Avoid
// macro parameter as function call which will have side effects.
//
#define NV_SIGN(s) ((NvS8)(((s) > 0) - ((s) < 0)))
//
// Returns 1 if input number is >= 0 or -1 otherwise. This assumes 0 has a
// positive sign.
//
#define NV_ZERO_SIGN(s) ((NvS8)((((s) >= 0) * 2) - 1))
// Returns the offset (in bytes) of 'member' in struct 'type'.
#ifndef NV_OFFSETOF
#if defined(__GNUC__) && (__GNUC__ > 3)
#define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member))
#else
#define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header.
#endif
#endif
//
// Performs a rounded division of b into a (unsigned). For SIGNED version of
// NV_ROUNDED_DIV() macro check the comments in bug 769777.
//
#define NV_UNSIGNED_ROUNDED_DIV(a,b) (((a) + ((b) / 2U)) / (b))
/*!
* Performs a ceiling division of b into a (unsigned). A "ceiling" division is
* a division is one with rounds up result up if a % b != 0.
*
* @param[in] a Numerator
* @param[in] b Denominator
*
* @return a / b + a % b != 0 ? 1 : 0.
*/
#define NV_UNSIGNED_DIV_CEIL(a, b) (((a) + (b - 1)) / (b))
/*!
* Performs subtraction where a negative difference is raised to zero.
* Can be used to avoid underflowing an unsigned subtraction.
*
* @param[in] a Minuend
* @param[in] b Subtrahend
*
* @return a > b ? a - b : 0.
*/
#define NV_SUBTRACT_NO_UNDERFLOW(a, b) ((a)>(b) ? (a)-(b) : 0)
/*!
* Performs a rounded right-shift of 32-bit unsigned value "a" by "shift" bits.
* Will round result away from zero.
*
* @param[in] a 32-bit unsigned value to shift.
* @param[in] shift Number of bits by which to shift.
*
* @return Resulting shifted value rounded away from zero.
*/
#define NV_RIGHT_SHIFT_ROUNDED(a, shift) \
(((a) >> (shift)) + !!((NVBIT((shift) - 1) & (a)) == NVBIT((shift) - 1)))
//
// Power of 2 alignment.
// (Will give unexpected results if 'gran' is not a power of 2.)
//
#ifndef NV_ALIGN_DOWN
//
// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type.
// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed.
//
#define NV_ALIGN_DOWN(v, gran) ((v) & ~((v) - (v) + (gran) - 1))
#endif
#ifndef NV_ALIGN_UP
//
// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type.
// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed.
//
#define NV_ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1))
#endif
#ifndef NV_ALIGN_DOWN64
#define NV_ALIGN_DOWN64(v, gran) ((v) & ~(((NvU64)gran) - 1))
#endif
#ifndef NV_ALIGN_UP64
#define NV_ALIGN_UP64(v, gran) (((v) + ((gran) - 1)) & ~(((NvU64)gran)-1))
#endif
#ifndef NV_IS_ALIGNED
#define NV_IS_ALIGNED(v, gran) (0U == ((v) & ((gran) - 1U)))
#endif
#ifndef NV_IS_ALIGNED64
#define NV_IS_ALIGNED64(v, gran) (0U == ((v) & (((NvU64)gran) - 1U)))
#endif
#ifndef NVMISC_MEMSET
static NV_FORCEINLINE void *NVMISC_MEMSET(void *s, NvU8 c, NvLength n)
{
NvU8 *b = (NvU8 *) s;
NvLength i;
for (i = 0; i < n; i++)
{
b[i] = c;
}
return s;
}
#endif
#ifndef NVMISC_MEMCPY
static NV_FORCEINLINE void *NVMISC_MEMCPY(void *dest, const void *src, NvLength n)
{
NvU8 *destByte = (NvU8 *) dest;
const NvU8 *srcByte = (const NvU8 *) src;
NvLength i;
for (i = 0; i < n; i++)
{
destByte[i] = srcByte[i];
}
return dest;
}
#endif
static NV_FORCEINLINE char *NVMISC_STRNCPY(char *dest, const char *src, NvLength n)
{
NvLength i;
for (i = 0; i < n; i++)
{
dest[i] = src[i];
if (src[i] == '\0')
{
break;
}
}
for (; i < n; i++)
{
dest[i] = '\0';
}
return dest;
}
/*!
* Convert a void* to an NvUPtr. This is used when MISRA forbids us from doing a direct cast.
*
* @param[in] ptr Pointer to be converted
*
* @return Resulting NvUPtr
*/
static NV_FORCEINLINE NvUPtr NV_PTR_TO_NVUPTR(void *ptr)
{
union
{
NvUPtr v;
void *p;
} uAddr;
uAddr.p = ptr;
return uAddr.v;
}
/*!
* Convert an NvUPtr to a void*. This is used when MISRA forbids us from doing a direct cast.
*
* @param[in] ptr Pointer to be converted
*
* @return Resulting void *
*/
static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
{
union
{
NvUPtr v;
void *p;
} uAddr;
uAddr.v = address;
return uAddr.p;
}
#ifdef __cplusplus
}
#endif //__cplusplus
#endif // __NV_MISC_H
07070100000025000081A4000000000000000000000001663926A7000269BE000000000000000000000000000000000000003100000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvos.h/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/***************************************************************************\
|* *|
|* NV Architecture Interface *|
|* *|
|* <nvos.h> defines the Operating System function and ioctl interfaces to *|
|* NVIDIA's Unified Media Architecture (TM). *|
|* *|
\***************************************************************************/
#ifndef NVOS_INCLUDED
#define NVOS_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "nvstatus.h"
#include "nvgputypes.h"
#include "rs_access.h"
/* local defines here */
#define FILE_DEVICE_NV 0x00008000
#define NV_IOCTL_FCT_BASE 0x00000800
// This is the maximum number of subdevices supported in an SLI
// configuration.
#define NVOS_MAX_SUBDEVICES 8
/* Define to indicate the use of Unified status codes - bug 200043705*/
#define UNIFIED_NV_STATUS 1
/***************************************************************************\
|* NV OS Functions *|
\***************************************************************************/
/*
Result codes for RM APIs, shared for all the APIs
*** IMPORTANT ***
Ensure that no NVOS_STATUS value has the highest bit set. That bit
is used to passthrough the NVOS_STATUS on code expecting an RM_STATUS.
*/
#define NVOS_STATUS NV_STATUS
#define NVOS_STATUS_SUCCESS NV_OK
#define NVOS_STATUS_ERROR_CARD_NOT_PRESENT NV_ERR_CARD_NOT_PRESENT
#define NVOS_STATUS_ERROR_DUAL_LINK_INUSE NV_ERR_DUAL_LINK_INUSE
#define NVOS_STATUS_ERROR_GENERIC NV_ERR_GENERIC
#define NVOS_STATUS_ERROR_GPU_NOT_FULL_POWER NV_ERR_GPU_NOT_FULL_POWER
#define NVOS_STATUS_ERROR_ILLEGAL_ACTION NV_ERR_ILLEGAL_ACTION
#define NVOS_STATUS_ERROR_IN_USE NV_ERR_STATE_IN_USE
#define NVOS_STATUS_ERROR_INSUFFICIENT_RESOURCES NV_ERR_INSUFFICIENT_RESOURCES
#define NVOS_STATUS_ERROR_INVALID_ACCESS_TYPE NV_ERR_INVALID_ACCESS_TYPE
#define NVOS_STATUS_ERROR_INVALID_ARGUMENT NV_ERR_INVALID_ARGUMENT
#define NVOS_STATUS_ERROR_INVALID_BASE NV_ERR_INVALID_BASE
#define NVOS_STATUS_ERROR_INVALID_CHANNEL NV_ERR_INVALID_CHANNEL
#define NVOS_STATUS_ERROR_INVALID_CLASS NV_ERR_INVALID_CLASS
#define NVOS_STATUS_ERROR_INVALID_CLIENT NV_ERR_INVALID_CLIENT
#define NVOS_STATUS_ERROR_INVALID_COMMAND NV_ERR_INVALID_COMMAND
#define NVOS_STATUS_ERROR_INVALID_DATA NV_ERR_INVALID_DATA
#define NVOS_STATUS_ERROR_INVALID_DEVICE NV_ERR_INVALID_DEVICE
#define NVOS_STATUS_ERROR_INVALID_DMA_SPECIFIER NV_ERR_INVALID_DMA_SPECIFIER
#define NVOS_STATUS_ERROR_INVALID_EVENT NV_ERR_INVALID_EVENT
#define NVOS_STATUS_ERROR_INVALID_FLAGS NV_ERR_INVALID_FLAGS
#define NVOS_STATUS_ERROR_INVALID_FUNCTION NV_ERR_INVALID_FUNCTION
#define NVOS_STATUS_ERROR_INVALID_HEAP NV_ERR_INVALID_HEAP
#define NVOS_STATUS_ERROR_INVALID_INDEX NV_ERR_INVALID_INDEX
#define NVOS_STATUS_ERROR_INVALID_LIMIT NV_ERR_INVALID_LIMIT
#define NVOS_STATUS_ERROR_INVALID_METHOD NV_ERR_INVALID_METHOD
#define NVOS_STATUS_ERROR_INVALID_OBJECT_BUFFER NV_ERR_BUFFER_TOO_SMALL
#define NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR NV_ERR_INVALID_OBJECT
#define NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE NV_ERR_INVALID_OBJECT_HANDLE
#define NVOS_STATUS_ERROR_INVALID_OBJECT_NEW NV_ERR_INVALID_OBJECT_NEW
#define NVOS_STATUS_ERROR_INVALID_OBJECT_OLD NV_ERR_INVALID_OBJECT_OLD
#define NVOS_STATUS_ERROR_INVALID_OBJECT_PARENT NV_ERR_INVALID_OBJECT_PARENT
#define NVOS_STATUS_ERROR_INVALID_OFFSET NV_ERR_INVALID_OFFSET
#define NVOS_STATUS_ERROR_INVALID_OWNER NV_ERR_INVALID_OWNER
#define NVOS_STATUS_ERROR_INVALID_PARAM_STRUCT NV_ERR_INVALID_PARAM_STRUCT
#define NVOS_STATUS_ERROR_INVALID_PARAMETER NV_ERR_INVALID_PARAMETER
#define NVOS_STATUS_ERROR_INVALID_POINTER NV_ERR_INVALID_POINTER
#define NVOS_STATUS_ERROR_INVALID_REGISTRY_KEY NV_ERR_INVALID_REGISTRY_KEY
#define NVOS_STATUS_ERROR_INVALID_STATE NV_ERR_INVALID_STATE
#define NVOS_STATUS_ERROR_INVALID_STRING_LENGTH NV_ERR_INVALID_STRING_LENGTH
#define NVOS_STATUS_ERROR_INVALID_XLATE NV_ERR_INVALID_XLATE
#define NVOS_STATUS_ERROR_IRQ_NOT_FIRING NV_ERR_IRQ_NOT_FIRING
#define NVOS_STATUS_ERROR_MULTIPLE_MEMORY_TYPES NV_ERR_MULTIPLE_MEMORY_TYPES
#define NVOS_STATUS_ERROR_NOT_SUPPORTED NV_ERR_NOT_SUPPORTED
#define NVOS_STATUS_ERROR_OPERATING_SYSTEM NV_ERR_OPERATING_SYSTEM
#define NVOS_STATUS_ERROR_LIB_RM_VERSION_MISMATCH NV_ERR_LIB_RM_VERSION_MISMATCH
#define NVOS_STATUS_ERROR_PROTECTION_FAULT NV_ERR_PROTECTION_FAULT
#define NVOS_STATUS_ERROR_TIMEOUT NV_ERR_TIMEOUT
#define NVOS_STATUS_ERROR_TOO_MANY_PRIMARIES NV_ERR_TOO_MANY_PRIMARIES
#define NVOS_STATUS_ERROR_IRQ_EDGE_TRIGGERED NV_ERR_IRQ_EDGE_TRIGGERED
#define NVOS_STATUS_ERROR_INVALID_OPERATION NV_ERR_INVALID_OPERATION
#define NVOS_STATUS_ERROR_NOT_COMPATIBLE NV_ERR_NOT_COMPATIBLE
#define NVOS_STATUS_ERROR_MORE_PROCESSING_REQUIRED NV_WARN_MORE_PROCESSING_REQUIRED
#define NVOS_STATUS_ERROR_INSUFFICIENT_PERMISSIONS NV_ERR_INSUFFICIENT_PERMISSIONS
#define NVOS_STATUS_ERROR_TIMEOUT_RETRY NV_ERR_TIMEOUT_RETRY
#define NVOS_STATUS_ERROR_NOT_READY NV_ERR_NOT_READY
#define NVOS_STATUS_ERROR_GPU_IS_LOST NV_ERR_GPU_IS_LOST
#define NVOS_STATUS_ERROR_IN_FULLCHIP_RESET NV_ERR_GPU_IN_FULLCHIP_RESET
#define NVOS_STATUS_ERROR_INVALID_LOCK_STATE NV_ERR_INVALID_LOCK_STATE
#define NVOS_STATUS_ERROR_INVALID_ADDRESS NV_ERR_INVALID_ADDRESS
#define NVOS_STATUS_ERROR_INVALID_IRQ_LEVEL NV_ERR_INVALID_IRQ_LEVEL
#define NVOS_STATUS_ERROR_MEMORY_TRAINING_FAILED NV_ERR_MEMORY_TRAINING_FAILED
#define NVOS_STATUS_ERROR_BUSY_RETRY NV_ERR_BUSY_RETRY
#define NVOS_STATUS_ERROR_INSUFFICIENT_POWER NV_ERR_INSUFFICIENT_POWER
#define NVOS_STATUS_ERROR_OBJECT_NOT_FOUND NV_ERR_OBJECT_NOT_FOUND
#define NVOS_STATUS_ERROR_RESOURCE_LOST NV_ERR_RESOURCE_LOST
#define NVOS_STATUS_ERROR_BUFFER_TOO_SMALL NV_ERR_BUFFER_TOO_SMALL
#define NVOS_STATUS_ERROR_RESET_REQUIRED NV_ERR_RESET_REQUIRED
#define NVOS_STATUS_ERROR_INVALID_REQUEST NV_ERR_INVALID_REQUEST
#define NVOS_STATUS_ERROR_PRIV_SEC_VIOLATION NV_ERR_PRIV_SEC_VIOLATION
#define NVOS_STATUS_ERROR_GPU_IN_DEBUG_MODE NV_ERR_GPU_IN_DEBUG_MODE
/*
Note:
This version of the architecture has been changed to allow the
RM to return a client handle that will subsequently used to
identify the client. NvAllocRoot() returns the handle. All
other functions must specify this client handle.
*/
/* macro NV01_FREE */
#define NV01_FREE (0x00000000)
/* NT ioctl data structure */
typedef struct
{
NvHandle hRoot;
NvHandle hObjectParent;
NvHandle hObjectOld;
NvV32 status;
} NVOS00_PARAMETERS;
/* valid hClass values. */
#define NV01_ROOT (0x00000000)
//
// Redefining it here to maintain consistency with current code
// This is also defined in class cl0001.h
//
#define NV01_ROOT_NON_PRIV (0x00000001)
// Deprecated, please use NV01_ROOT_CLIENT
#define NV01_ROOT_USER NV01_ROOT_CLIENT
//
// This will eventually replace NV01_ROOT_USER in RM client code. Please use this
// RM client object type for any new RM client object allocations that are being
// added.
//
#define NV01_ROOT_CLIENT (0x00000041)
/* macro NV01_ALLOC_MEMORY */
#define NV01_ALLOC_MEMORY (0x00000002)
/* parameter values */
#define NVOS02_FLAGS_PHYSICALITY 7:4
#define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000)
#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001)
#define NVOS02_FLAGS_LOCATION 11:8
#define NVOS02_FLAGS_LOCATION_PCI (0x00000000)
#define NVOS02_FLAGS_LOCATION_AGP (0x00000001)
#define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002)
#define NVOS02_FLAGS_COHERENCY 15:12
#define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000)
#define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001)
#define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002)
#define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003)
#define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004)
#define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005)
#define NVOS02_FLAGS_ALLOC 17:16
#define NVOS02_FLAGS_ALLOC_NONE (0x00000001)
#define NVOS02_FLAGS_GPU_CACHEABLE 18:18
#define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000)
#define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001)
// If requested, RM will create a kernel mapping of this memory.
// Default is no map.
#define NVOS02_FLAGS_KERNEL_MAPPING 19:19
#define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000)
#define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001)
#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20
#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000)
#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001)
//
// If the flag is set, the RM will only allow read-only CPU user mappings to the
// allocation.
//
#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21
#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000)
#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001)
//
// If the flag is set, the RM will only allow read-only DMA mappings to the
// allocation.
//
#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22
#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000)
#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001)
//
// If the flag is set, the IO memory allocation can be registered with the RM if
// the RM regkey peerMappingOverride is set or the client is privileged.
//
// See Bug 1630288 "[PeerSync] threat related to GPU.." for more details.
//
#define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23
#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000)
#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001)
// If the flag is set RM will assume the memory pages are of type syncpoint.
#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24
#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001)
//
// If _NO_MAP is requested, the RM in supported platforms will not map the
// allocated system or IO memory into user space. The client can later map
// memory through the RmMapMemory() interface.
// If _NEVER_MAP is requested, the RM will never map the allocated system or
// IO memory into user space
//
#define NVOS02_FLAGS_MAPPING 31:30
#define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000)
#define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001)
#define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002)
// -------------------------------------------------------------------------------------
/* parameters */
typedef struct
{
NvHandle hRoot;
NvHandle hObjectParent;
NvHandle hObjectNew;
NvV32 hClass;
NvV32 flags;
NvP64 pMemory NV_ALIGN_BYTES(8);
NvU64 limit NV_ALIGN_BYTES(8);
NvV32 status;
} NVOS02_PARAMETERS;
/* parameter values */
#define NVOS03_FLAGS_ACCESS 1:0
#define NVOS03_FLAGS_ACCESS_READ_WRITE (0x00000000)
#define NVOS03_FLAGS_ACCESS_READ_ONLY (0x00000001)
#define NVOS03_FLAGS_ACCESS_WRITE_ONLY (0x00000002)
#define NVOS03_FLAGS_PREALLOCATE 2:2
#define NVOS03_FLAGS_PREALLOCATE_DISABLE (0x00000000)
#define NVOS03_FLAGS_PREALLOCATE_ENABLE (0x00000001)
#define NVOS03_FLAGS_GPU_MAPPABLE 15:15
#define NVOS03_FLAGS_GPU_MAPPABLE_DISABLE (0x00000000)
#define NVOS03_FLAGS_GPU_MAPPABLE_ENABLE (0x00000001)
// ------------------------------------------------------------------------------------
// This flag is required for a hack to be placed inside DD that allows it to
// access a dummy ctxdma as a block linear surface. Refer bug 1562766 for details.
//
// This flag is deprecated, use NVOS03_FLAGS_PTE_KIND.
//
#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE 16:16
#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_FALSE (0x00000000)
#define NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE_TRUE (0x00000001)
/*
* This field allows to specify the page kind. If the page kind
* is not specified then the page kind associated with the memory will be used.
*
* In tegra display driver stack, the page kind remains unknown at the time
* of memory allocation/import, the page kind can only be known when display
* driver client creates a framebuffer from allocated/imported memory.
*
* This field compatible with NVOS03_FLAGS_PTE_KIND_BL_OVERRIDE flag.
*/
#define NVOS03_FLAGS_PTE_KIND 17:16
#define NVOS03_FLAGS_PTE_KIND_NONE (0x00000000)
#define NVOS03_FLAGS_PTE_KIND_BL (0x00000001)
#define NVOS03_FLAGS_PTE_KIND_PITCH (0x00000002)
#define NVOS03_FLAGS_TYPE 23:20
#define NVOS03_FLAGS_TYPE_NOTIFIER (0x00000001)
/*
* This is an alias into the LSB of the TYPE field which
* actually indicates if a Kernel Mapping should be created.
* If the RM should have access to the memory then Enable this
* flag.
*
* Note that the NV_OS03_FLAGS_MAPPING is an alias to
* the LSB of the NV_OS03_FLAGS_TYPE. And in fact if
* type is NV_OS03_FLAGS_TYPE_NOTIFIER (bit 20 set)
* then it implicitly means that NV_OS03_FLAGS_MAPPING
* is _MAPPING_KERNEL. If the client wants to have a
* Kernel Mapping, it should use the _MAPPING_KERNEL
* flag set and the _TYPE_NOTIFIER should be used only
* with NOTIFIERS.
*/
#define NVOS03_FLAGS_MAPPING 20:20
#define NVOS03_FLAGS_MAPPING_NONE (0x00000000)
#define NVOS03_FLAGS_MAPPING_KERNEL (0x00000001)
#define NVOS03_FLAGS_CACHE_SNOOP 28:28
#define NVOS03_FLAGS_CACHE_SNOOP_ENABLE (0x00000000)
#define NVOS03_FLAGS_CACHE_SNOOP_DISABLE (0x00000001)
// HASH_TABLE:ENABLE means that the context DMA is automatically bound into all
// channels in the client. This can lead to excessive hash table usage.
// HASH_TABLE:DISABLE means that the context DMA must be explicitly bound into
// any channel that needs to use it via NvRmBindContextDma.
// HASH_TABLE:ENABLE is not supported on NV50 and up, and HASH_TABLE:DISABLE should
// be preferred for all new code.
#define NVOS03_FLAGS_HASH_TABLE 29:29
#define NVOS03_FLAGS_HASH_TABLE_ENABLE (0x00000000)
#define NVOS03_FLAGS_HASH_TABLE_DISABLE (0x00000001)
/* macro NV01_ALLOC_OBJECT */
#define NV01_ALLOC_OBJECT (0x00000005)
/* parameters */
typedef struct
{
NvHandle hRoot;
NvHandle hObjectParent;
NvHandle hObjectNew;
NvV32 hClass;
NvV32 status;
} NVOS05_PARAMETERS;
/* Valid values for hClass in Nv01AllocEvent */
/* Note that NV01_EVENT_OS_EVENT is same as NV01_EVENT_WIN32_EVENT */
/* TODO: delete the WIN32 name */
#define NV01_EVENT_KERNEL_CALLBACK (0x00000078)
#define NV01_EVENT_OS_EVENT (0x00000079)
#define NV01_EVENT_WIN32_EVENT NV01_EVENT_OS_EVENT
#define NV01_EVENT_KERNEL_CALLBACK_EX (0x0000007E)
/* NOTE: NV01_EVENT_KERNEL_CALLBACK is deprecated. Please use NV01_EVENT_KERNEL_CALLBACK_EX. */
/* For use with NV01_EVENT_KERNEL_CALLBACK. */
/* NVOS10_EVENT_KERNEL_CALLBACK data structure storage needs to be retained by the caller. */
typedef void (*Callback1ArgVoidReturn)(void *arg);
typedef void (*Callback5ArgVoidReturn)(void *arg1, void *arg2, NvHandle hEvent, NvU32 data, NvU32 status);
/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface
can only be used by other kernel drivers which must share the same ptr-size */
typedef struct
{
Callback1ArgVoidReturn func;
void *arg;
} NVOS10_EVENT_KERNEL_CALLBACK;
/* For use with NV01_EVENT_KERNEL_CALLBACK_EX. */
/* NVOS10_EVENT_KERNEL_CALLBACK_EX data structure storage needs to be retained by the caller. */
/* NOTE: the 'void* arg' below is ok (but unfortunate) since this interface
can only be used by other kernel drivers which must share the same ptr-size */
typedef struct
{
Callback5ArgVoidReturn func;
void *arg;
} NVOS10_EVENT_KERNEL_CALLBACK_EX;
/* Setting this bit in index will set the Event to a Broadcast type */
/* i.e. each subdevice under a device needs to see the Event before it's signaled */
#define NV01_EVENT_BROADCAST (0x80000000)
/* allow non-root resman client to create NV01_EVENT_KERNEL_CALLBACK events */
/* -- this works in debug/develop drivers only (for security reasons)*/
#define NV01_EVENT_PERMIT_NON_ROOT_EVENT_KERNEL_CALLBACK_CREATION (0x40000000)
/* RM event should be triggered only by the specified subdevice; see cl0005.h
* for details re: how to specify subdevice. */
#define NV01_EVENT_SUBDEVICE_SPECIFIC (0x20000000)
/* RM should trigger the event but shouldn't do the book-keeping of data
* associated with that event */
#define NV01_EVENT_WITHOUT_EVENT_DATA (0x10000000)
/* RM event should be triggered only by the non-stall interrupt */
#define NV01_EVENT_NONSTALL_INTR (0x08000000)
/* RM event was allocated from client RM, post events back to client RM */
#define NV01_EVENT_CLIENT_RM (0x04000000)
/* function OS19 */
#define NV04_I2C_ACCESS (0x00000013)
#define NVOS_I2C_ACCESS_MAX_BUFFER_SIZE 2048
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hDevice;
NvU32 paramSize;
NvP64 paramStructPtr NV_ALIGN_BYTES(8);
NvV32 status;
} NVOS_I2C_ACCESS_PARAMS;
/* current values for command */
#define NVOS20_COMMAND_unused0001 0x0001
#define NVOS20_COMMAND_unused0002 0x0002
#define NVOS20_COMMAND_STRING_PRINT 0x0003
/* function OS21 */
#define NV04_ALLOC (0x00000015)
/* parameters */
typedef struct
{
NvHandle hRoot;
NvHandle hObjectParent;
NvHandle hObjectNew;
NvV32 hClass;
NvP64 pAllocParms NV_ALIGN_BYTES(8);
NvV32 status;
} NVOS21_PARAMETERS;
/* New struct with rights requested */
typedef struct
{
NvHandle hRoot; // [IN] client handle
NvHandle hObjectParent; // [IN] parent handle of new object
NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate
NvV32 hClass; // [in] class num of new object
NvP64 pAllocParms NV_ALIGN_BYTES(8); // [IN] class-specific alloc parameters
NvP64 pRightsRequested NV_ALIGN_BYTES(8); // [IN] RS_ACCESS_MASK to request rights, or NULL
NvU32 paramsSize; // [IN] Size of alloc params
NvU32 flags;
NvV32 status; // [OUT] status
} NVOS64_PARAMETERS;
/* RM Alloc header
*
* Replacement for NVOS21/64_PARAMETERS where embedded pointers are not allowed.
* Input layout for RM Alloc user space calls should be
*
* +--- NVOS62_PARAMETERS ---+--- RM Alloc parameters ---+
* +--- NVOS65_PARAMETERS ---+--- Rights Requested ---+--- RM Alloc parameters ---+
*
* NVOS62_PARAMETERS::paramsSize is the size of RM Alloc parameters
* If NVOS65_PARAMETERS::maskSize is 0, Rights Requested will not be present in memory.
*
*/
typedef struct
{
NvHandle hRoot; // [IN] client handle
NvHandle hObjectParent; // [IN] parent handle of the new object
NvHandle hObjectNew; // [IN] new object handle
NvV32 hClass; // [IN] class num of the new object
NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters
NvV32 status; // [OUT] status
} NVOS62_PARAMETERS;
#define NVOS65_PARAMETERS_VERSION_MAGIC 0x77FEF81E
typedef struct
{
NvHandle hRoot; // [IN] client handle
NvHandle hObjectParent; // [IN] parent handle of the new object
NvHandle hObjectNew; // [INOUT] new object handle, 0 to generate
NvV32 hClass; // [IN] class num of the new object
NvU32 paramSize; // [IN] size in bytes of the RM alloc parameters
NvU32 versionMagic; // [IN] NVOS65_PARAMETERS_VERISON_MAGIC
NvU32 maskSize; // [IN] size in bytes of access mask, or 0 if NULL
NvV32 status; // [OUT] status
} NVOS65_PARAMETERS;
/* function OS30 */
#define NV04_IDLE_CHANNELS (0x0000001E)
/* parameter values */
#define NVOS30_FLAGS_BEHAVIOR 3:0
#define NVOS30_FLAGS_BEHAVIOR_SPIN (0x00000000)
#define NVOS30_FLAGS_BEHAVIOR_SLEEP (0x00000001)
#define NVOS30_FLAGS_BEHAVIOR_QUERY (0x00000002)
#define NVOS30_FLAGS_BEHAVIOR_FORCE_BUSY_CHECK (0x00000003)
#define NVOS30_FLAGS_CHANNEL 7:4
#define NVOS30_FLAGS_CHANNEL_LIST (0x00000000)
#define NVOS30_FLAGS_CHANNEL_SINGLE (0x00000001)
#define NVOS30_FLAGS_IDLE 30:8
#define NVOS30_FLAGS_IDLE_PUSH_BUFFER (0x00000001)
#define NVOS30_FLAGS_IDLE_CACHE1 (0x00000002)
#define NVOS30_FLAGS_IDLE_GRAPHICS (0x00000004)
#define NVOS30_FLAGS_IDLE_MPEG (0x00000008)
#define NVOS30_FLAGS_IDLE_MOTION_ESTIMATION (0x00000010)
#define NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR (0x00000020)
#define NVOS30_FLAGS_IDLE_MSPDEC (0x00000020)
#define NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR (0x00000040)
#define NVOS30_FLAGS_IDLE_MSVLD (0x00000040)
#define NVOS30_FLAGS_IDLE_NVDEC0 NVOS30_FLAGS_IDLE_MSVLD
#define NVOS30_FLAGS_IDLE_CIPHER_DMA (0x00000080)
#define NVOS30_FLAGS_IDLE_SEC (0x00000080)
#define NVOS30_FLAGS_IDLE_CALLBACKS (0x00000100)
#define NVOS30_FLAGS_IDLE_MSPPP (0x00000200)
#define NVOS30_FLAGS_IDLE_CE0 (0x00000400)
#define NVOS30_FLAGS_IDLE_CE1 (0x00000800)
#define NVOS30_FLAGS_IDLE_CE2 (0x00001000)
#define NVOS30_FLAGS_IDLE_CE3 (0x00002000)
#define NVOS30_FLAGS_IDLE_CE4 (0x00004000)
#define NVOS30_FLAGS_IDLE_CE5 (0x00008000)
#define NVOS30_FLAGS_IDLE_VIC (0x00010000)
#define NVOS30_FLAGS_IDLE_MSENC (0x00020000)
#define NVOS30_FLAGS_IDLE_NVENC0 NVOS30_FLAGS_IDLE_MSENC
#define NVOS30_FLAGS_IDLE_NVENC1 (0x00040000)
#define NVOS30_FLAGS_IDLE_NVENC2 (0x00080000)
#define NVOS30_FLAGS_IDLE_NVJPG (0x00100000)
#define NVOS30_FLAGS_IDLE_NVDEC1 (0x00200000)
#define NVOS30_FLAGS_IDLE_NVDEC2 (0x00400000)
#define NVOS30_FLAGS_IDLE_ACTIVECHANNELS (0x00800000)
#define NVOS30_FLAGS_IDLE_ALL_ENGINES (NVOS30_FLAGS_IDLE_GRAPHICS | \
NVOS30_FLAGS_IDLE_MPEG | \
NVOS30_FLAGS_IDLE_MOTION_ESTIMATION | \
NVOS30_FLAGS_IDLE_VIDEO_PROCESSOR | \
NVOS30_FLAGS_IDLE_BITSTREAM_PROCESSOR | \
NVOS30_FLAGS_IDLE_CIPHER_DMA | \
NVOS30_FLAGS_IDLE_MSPDEC | \
NVOS30_FLAGS_IDLE_NVDEC0 | \
NVOS30_FLAGS_IDLE_SEC | \
NVOS30_FLAGS_IDLE_MSPPP | \
NVOS30_FLAGS_IDLE_CE0 | \
NVOS30_FLAGS_IDLE_CE1 | \
NVOS30_FLAGS_IDLE_CE2 | \
NVOS30_FLAGS_IDLE_CE3 | \
NVOS30_FLAGS_IDLE_CE4 | \
NVOS30_FLAGS_IDLE_CE5 | \
NVOS30_FLAGS_IDLE_NVENC0 | \
NVOS30_FLAGS_IDLE_NVENC1 | \
NVOS30_FLAGS_IDLE_NVENC2 | \
NVOS30_FLAGS_IDLE_VIC | \
NVOS30_FLAGS_IDLE_NVJPG | \
NVOS30_FLAGS_IDLE_NVDEC1 | \
NVOS30_FLAGS_IDLE_NVDEC2)
#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON 31:31
#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_NO (0x00000000)
#define NVOS30_FLAGS_WAIT_FOR_ELPG_ON_YES (0x00000001)
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hDevice;
NvHandle hChannel;
NvV32 numChannels;
NvP64 phClients NV_ALIGN_BYTES(8);
NvP64 phDevices NV_ALIGN_BYTES(8);
NvP64 phChannels NV_ALIGN_BYTES(8);
NvV32 flags;
NvV32 timeout;
NvV32 status;
} NVOS30_PARAMETERS;
/* function OS32 */
typedef void (*BindResultFunc)(void * pVoid, NvU32 gpuMask, NvU32 bState, NvU32 bResult);
#define NV04_VID_HEAP_CONTROL (0x00000020)
/*************************************************************************
************************ New Heap Interface ******************************
*************************************************************************/
// NVOS32 Descriptor types
//
// NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR: The dma-buf object
// pointer, provided by the linux kernel buffer sharing sub-system.
// This descriptor can only be used by kernel space rm-clients.
//
#define NVOS32_DESCRIPTOR_TYPE_VIRTUAL_ADDRESS 0
#define NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY 1
#define NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY 2
#define NVOS32_DESCRIPTOR_TYPE_OS_PHYS_ADDR 3
#define NVOS32_DESCRIPTOR_TYPE_OS_FILE_HANDLE 4
#define NVOS32_DESCRIPTOR_TYPE_OS_DMA_BUF_PTR 5
#define NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR 6
#define NVOS32_DESCRIPTOR_TYPE_KERNEL_VIRTUAL_ADDRESS 7
// NVOS32 function
#define NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT 1
#define NVOS32_FUNCTION_ALLOC_SIZE 2
#define NVOS32_FUNCTION_FREE 3
// #define NVOS32_FUNCTION_HEAP_PURGE 4
#define NVOS32_FUNCTION_INFO 5
#define NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT 6
// #define NVOS32_FUNCTION_DESTROY 7
// #define NVOS32_FUNCTION_RETAIN 9
// #define NVOS32_FUNCTION_REALLOC 10
#define NVOS32_FUNCTION_DUMP 11
// #define NVOS32_FUNCTION_INFO_TYPE_ALLOC_BLOCKS 12
#define NVOS32_FUNCTION_ALLOC_SIZE_RANGE 14
#define NVOS32_FUNCTION_REACQUIRE_COMPR 15
#define NVOS32_FUNCTION_RELEASE_COMPR 16
// #define NVOS32_FUNCTION_MODIFY_DEFERRED_TILES 17
#define NVOS32_FUNCTION_GET_MEM_ALIGNMENT 18
#define NVOS32_FUNCTION_HW_ALLOC 19
#define NVOS32_FUNCTION_HW_FREE 20
// #define NVOS32_FUNCTION_SET_OFFSET 21
// #define NVOS32_FUNCTION_IS_TILED 22
// #define NVOS32_FUNCTION_ENABLE_RESOURCE 23
// #define NVOS32_FUNCTION_BIND_COMPR 24
#define NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR 27
typedef struct
{
NvP64 sgt NV_ALIGN_BYTES(8);
NvP64 gem NV_ALIGN_BYTES(8);
} NVOS32_DESCRIPTOR_TYPE_OS_SGT_PTR_PARAMETERS;
#define NVOS32_FLAGS_BLOCKINFO_VISIBILITY_CPU (0x00000001)
typedef struct
{
NvU64 startOffset NV_ALIGN_BYTES(8);
NvU64 size NV_ALIGN_BYTES(8);
NvU32 flags;
} NVOS32_BLOCKINFO;
// NVOS32 IVC-heap number delimiting value
#define NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP 0 // When IVC heaps are present,
// IVC-heap number specified
// as part of 'NVOS32_PARAMETERS'
// which is less or equal to this
// constant indicates that allocation
// should not be done on IVC heap.
// Explanation of IVC-heap number is
// under 'AllocSize' structure below.
typedef struct
{
NvHandle hRoot; // [IN] - root object handle
NvHandle hObjectParent; // [IN] - device handle
NvU32 function; // [IN] - heap function, see below FUNCTION* defines
NvHandle hVASpace; // [IN] - VASpace handle
NvS16 ivcHeapNumber; // [IN] - When IVC heaps are present: either 1) number of the IVC heap
// shared between two VMs or 2) number indicating that allocation
// should not be done on an IVC heap. Values greater than constant
// 'NVOS32_IVC_HEAP_NUMBER_DONT_ALLOCATE_ON_IVC_HEAP' define set 1)
// and values less or equal to that constant define set 2).
// When IVC heaps are present, correct IVC-heap number must be specified.
// When IVC heaps are absent, IVC-heap number is diregarded.
// RM provides for each VM a bitmask of heaps with each bit
// specifying the other peer that can use the partition.
// Each bit set to one can be enumerated, such that the bit
// with lowest significance is enumerated with one.
// 'ivcHeapNumber' parameter specifies this enumeration value.
// This value is used to uniquely identify a heap shared between
// two particular VMs.
// Illustration:
// bitmask: 1 1 0 1 0 = 0x1A
// possible 'ivcHeapNumber' values: 3, 2, 1
NvV32 status; // [OUT] - returned NVOS32* status code, see below STATUS* defines
NvU64 total NV_ALIGN_BYTES(8); // [OUT] - returned total size of heap
NvU64 free NV_ALIGN_BYTES(8); // [OUT] - returned free space available in heap
union
{
// NVOS32_FUNCTION_ALLOC_DEPTH_WIDTH_HEIGHT
struct
{
NvU32 owner; // [IN] - memory owner ID
NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated)
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 depth; // [IN] - depth of surface in bits
NvU32 width; // [IN] - width of surface in pixels
NvU32 height; // [IN] - height of surface in pixels
NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 format; // [IN/OUT] - format requested, and format allocated
NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated
NvU32 zcullCovg; // [OUT] - zcull covg allocated
NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses
NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated
NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on
NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset
NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit
NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address
NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range
NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
} AllocDepthWidthHeight;
// NVOS32_FUNCTION_ALLOC_SIZE
struct
{
NvU32 owner; // [IN] - memory owner ID
NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated)
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 format; // [IN/OUT] - format requested, and format allocated
NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated
NvU32 zcullCovg; // [OUT] - zcull covg allocated
NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses
NvU32 width; // [IN] - width "hint" used for zcull region allocations
NvU32 height; // [IN] - height "hint" used for zcull region allocations
NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated
NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on
NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset
NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit
NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address
NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range
NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
} AllocSize;
// NVOS32_FUNCTION_ALLOC_TILED_PITCH_HEIGHT
struct
{
NvU32 owner; // [IN] - memory owner ID
NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated)
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 height; // [IN] - height of surface in pixels
NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated
NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 width; //[IN] - width of surface in pixels
NvU32 format; // [IN/OUT] - format requested, and format allocated
NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated
NvU32 zcullCovg; // [OUT] - zcull covg allocated
NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses
NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated
NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on
NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset
NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit
NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address
NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range
NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
} AllocTiledPitchHeight;
// NVOS32_FUNCTION_FREE
struct
{
NvU32 owner; // [IN] - memory owner ID
NvHandle hMemory; // [IN] - unique memory handle
NvU32 flags; // [IN] - heap free flags (must be NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED)
} Free;
// NVOS32_FUNCTION_RELEASE_COMPR
struct
{
NvU32 owner; // [IN] - memory owner ID
NvU32 flags; // [IN] - must be NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED
NvHandle hMemory; // [IN] - unique memory handle (valid if _RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED
} ReleaseCompr;
// NVOS32_FUNCTION_REACQUIRE_COMPR
struct
{
NvU32 owner; // [IN] - memory owner ID
NvU32 flags; // [IN] - must be NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED
NvHandle hMemory; // [IN] - unique memory handle (valid if _REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED
} ReacquireCompr;
// NVOS32_FUNCTION_INFO
struct
{
NvU32 attr; // [IN] - memory heap attributes requested
NvU64 offset NV_ALIGN_BYTES(8); // [OUT] - base of largest free block
NvU64 size NV_ALIGN_BYTES(8); // [OUT] - size of largest free block
NvU64 base NV_ALIGN_BYTES(8); // [OUT] - returned heap phys base
} Info;
// NVOS32_FUNCTION_DUMP
struct
{
NvU32 flags; // [IN] - see _DUMP_FLAGS
// [IN] - if NULL, numBlocks is the returned number of blocks in
// heap, else returns all blocks in eHeap
// if non-NULL points to a buffer that is at least numBlocks
// * sizeof(NVOS32_HEAP_DUMP_BLOCK) bytes.
NvP64 pBuffer NV_ALIGN_BYTES(8);
// [IN/OUT] - if pBuffer is NULL, will number of blocks in heap
// if pBuffer is non-NULL, is input containing the size of
// pBuffer in units of NVOS32_HEAP_DUMP_BLOCK. This must
// be greater than or equal to the number of blocks in the
// heap.
NvU32 numBlocks;
} Dump;
// NVOS32_FUNCTION_DESTROY - no extra parameters needed
// NVOS32_FUNCTION_ALLOC_SIZE_RANGE
struct
{
NvU32 owner; // [IN] - memory owner ID
NvHandle hMemory; // [IN] - unique memory handle
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 format; // [IN/OUT] - format requested, and format allocated
NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated
NvU32 zcullCovg; // [OUT] - zcull covg allocated
NvU32 partitionStride; // [IN/OUT] - 0 means "RM" chooses
NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated
NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on
NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset
NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit
NvU64 rangeBegin NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range
NvU64 rangeEnd NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvP64 address NV_ALIGN_BYTES(8);// [OUT] - returned address
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
} AllocSizeRange;
// additions for Longhorn
#define NVAL_MAX_BANKS (4)
#define NVAL_MAP_DIRECTION 0:0
#define NVAL_MAP_DIRECTION_DOWN 0x00000000
#define NVAL_MAP_DIRECTION_UP 0x00000001
// NVOS32_FUNCTION_GET_MEM_ALIGNMENT
struct
{
NvU32 alignType; // Input
NvU32 alignAttr;
NvU32 alignInputFlags;
NvU64 alignSize NV_ALIGN_BYTES(8);
NvU32 alignHeight;
NvU32 alignWidth;
NvU32 alignPitch;
NvU32 alignPad;
NvU32 alignMask;
NvU32 alignOutputFlags[NVAL_MAX_BANKS]; // We could compress this information but it is probably not that big of a deal
NvU32 alignBank[NVAL_MAX_BANKS];
NvU32 alignKind;
NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset
NvU32 alignAttr2;
} AllocHintAlignment;
struct
{
NvU32 allocOwner; // [IN] - memory owner ID
NvHandle allochMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated)
NvU32 flags;
NvU32 allocType; // Input
NvU32 allocAttr;
NvU32 allocInputFlags;
NvU64 allocSize NV_ALIGN_BYTES(8);
NvU32 allocHeight;
NvU32 allocWidth;
NvU32 allocPitch;
NvU32 allocMask;
NvU32 allocComprCovg;
NvU32 allocZcullCovg;
NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc
NvP64 pHandle NV_ALIGN_BYTES(8);
NvHandle hResourceHandle; // Handle to RM container
NvU32 retAttr; // Output Indicates the resources that we allocated
NvU32 kind;
NvU64 osDeviceHandle NV_ALIGN_BYTES(8);
NvU32 allocAttr2;
NvU32 retAttr2; // Output Indicates the resources that we allocated
NvU64 allocAddr NV_ALIGN_BYTES(8);
// [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h
struct
{
NvU32 compPageShift;
NvU32 compressedKind;
NvU32 compTagLineMin;
NvU32 compPageIndexLo;
NvU32 compPageIndexHi;
NvU32 compTagLineMultiplier;
} comprInfo;
// [out] fallback uncompressed kind.
NvU32 uncompressedKind;
} HwAlloc;
// NVOS32_FUNCTION_HW_FREE
struct
{
NvHandle hResourceHandle; // Handle to RM Resource Info
NvU32 flags; // Indicate if HW Resources and/or Memory
} HwFree;
// Updated interface check.
#define NV_RM_OS32_ALLOC_OS_DESCRIPTOR_WITH_OS32_ATTR 1
// NVOS32_FUNCTION_ALLOC_OS_DESCRIPTOR
struct
{
NvHandle hMemory; // [IN/OUT] - unique memory handle - IN only if MEMORY_HANDLE_PROVIDED is set (otherwise generated)
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 attr; // [IN] - attributes for memory placement/properties, see below
NvU32 attr2; // [IN] - attributes GPU_CACHEABLE
NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address
NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1
NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle)
} AllocOsDesc;
} data;
} NVOS32_PARAMETERS;
typedef struct
{
NvU32 owner; // owner id - NVOS32_BLOCK_TYPE_FREE or defined by client during heap_alloc
NvU32 format; // arch specific format/kind
NvU64 begin NV_ALIGN_BYTES(8); // start of allocated memory block
NvU64 align NV_ALIGN_BYTES(8); // actual start of usable memory, aligned to chip specific boundary
NvU64 end NV_ALIGN_BYTES(8); // end of usable memory. end - align + 1 = size of block
} NVOS32_HEAP_DUMP_BLOCK;
#define NVOS32_DELETE_RESOURCES_ALL 0
// type field
#define NVOS32_TYPE_IMAGE 0
#define NVOS32_TYPE_DEPTH 1
#define NVOS32_TYPE_TEXTURE 2
#define NVOS32_TYPE_VIDEO 3
#define NVOS32_TYPE_FONT 4
#define NVOS32_TYPE_CURSOR 5
#define NVOS32_TYPE_DMA 6
#define NVOS32_TYPE_INSTANCE 7
#define NVOS32_TYPE_PRIMARY 8
#define NVOS32_TYPE_ZCULL 9
#define NVOS32_TYPE_UNUSED 10
#define NVOS32_TYPE_SHADER_PROGRAM 11
#define NVOS32_TYPE_OWNER_RM 12
#define NVOS32_TYPE_NOTIFIER 13
#define NVOS32_TYPE_RESERVED 14
#define NVOS32_TYPE_PMA 15
#define NVOS32_TYPE_STENCIL 16
#define NVOS32_NUM_MEM_TYPES 17
// Surface attribute field - bitmask of requested attributes the surface
// should have.
// This value is updated to reflect what was actually allocated, and so this
// field must be checked after every allocation to determine what was
// allocated. Pass in the ANY tags to indicate that RM should fall back but
// still succeed the alloc.
// for example, if tiled_any is passed in, but no tile ranges are available,
// RM will allocate normal memory and indicate that in the returned attr field.
// Each returned attribute will have the REQUIRED field set if that attribute
// applies to the allocated surface.
#define NVOS32_ATTR_NONE 0x00000000
#define NVOS32_ATTR_DEPTH 2:0
#define NVOS32_ATTR_DEPTH_UNKNOWN 0x00000000
#define NVOS32_ATTR_DEPTH_8 0x00000001
#define NVOS32_ATTR_DEPTH_16 0x00000002
#define NVOS32_ATTR_DEPTH_24 0x00000003
#define NVOS32_ATTR_DEPTH_32 0x00000004
#define NVOS32_ATTR_DEPTH_64 0x00000005
#define NVOS32_ATTR_DEPTH_128 0x00000006
#define NVOS32_ATTR_COMPR_COVG 3:3
#define NVOS32_ATTR_COMPR_COVG_DEFAULT 0x00000000
#define NVOS32_ATTR_COMPR_COVG_PROVIDED 0x00000001
// Surface description - number of AA samples
// This number should only reflect AA done in hardware, not in software. For
// example, OpenGL's 8x AA mode is a mix of 2x hardware multisample and 2x2
// software supersample.
// OpenGL should specify ATTR_AA_SAMPLES of 2 in this case, not 8, because
// the hardware will be programmed to run in 2x AA mode.
// Note that X_VIRTUAL_Y means X real samples with Y samples total (i.e. Y
// does not indicate the number of virtual samples). For instance, what
// arch and HW describe as NV_PGRAPH_ANTI_ALIAS_SAMPLES_MODE_2X2_VC_12
// corresponds to NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 here.
#define NVOS32_ATTR_AA_SAMPLES 7:4
#define NVOS32_ATTR_AA_SAMPLES_1 0x00000000
#define NVOS32_ATTR_AA_SAMPLES_2 0x00000001
#define NVOS32_ATTR_AA_SAMPLES_4 0x00000002
#define NVOS32_ATTR_AA_SAMPLES_4_ROTATED 0x00000003
#define NVOS32_ATTR_AA_SAMPLES_6 0x00000004
#define NVOS32_ATTR_AA_SAMPLES_8 0x00000005
#define NVOS32_ATTR_AA_SAMPLES_16 0x00000006
#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_8 0x00000007
#define NVOS32_ATTR_AA_SAMPLES_4_VIRTUAL_16 0x00000008
#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_16 0x00000009
#define NVOS32_ATTR_AA_SAMPLES_8_VIRTUAL_32 0x0000000A
// Tiled region
#define NVOS32_ATTR_TILED 9:8
#define NVOS32_ATTR_TILED_NONE 0x00000000
#define NVOS32_ATTR_TILED_REQUIRED 0x00000001
#define NVOS32_ATTR_TILED_ANY 0x00000002
#define NVOS32_ATTR_TILED_DEFERRED 0x00000003
// Zcull region (NV40 and up)
// If ATTR_ZCULL is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the
// allocation will fail.
// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, erroneous rendering
// may result.
#define NVOS32_ATTR_ZCULL 11:10
#define NVOS32_ATTR_ZCULL_NONE 0x00000000
#define NVOS32_ATTR_ZCULL_REQUIRED 0x00000001
#define NVOS32_ATTR_ZCULL_ANY 0x00000002
#define NVOS32_ATTR_ZCULL_SHARED 0x00000003
// Compression (NV20 and up)
// If ATTR_COMPR is REQUIRED or ANY and ATTR_DEPTH is UNKNOWN, the
// allocation will fail.
// If ATTR_DEPTH or ATTR_AA_SAMPLES is not accurate, performance will
// suffer heavily
#define NVOS32_ATTR_COMPR 13:12
#define NVOS32_ATTR_COMPR_NONE 0x00000000
#define NVOS32_ATTR_COMPR_REQUIRED 0x00000001
#define NVOS32_ATTR_COMPR_ANY 0x00000002
#define NVOS32_ATTR_COMPR_PLC_REQUIRED NVOS32_ATTR_COMPR_REQUIRED
#define NVOS32_ATTR_COMPR_PLC_ANY NVOS32_ATTR_COMPR_ANY
#define NVOS32_ATTR_COMPR_DISABLE_PLC_ANY 0x00000003
// Format
// _BLOCK_LINEAR is only available for nv50+.
#define NVOS32_ATTR_FORMAT 17:16
// Macros representing the low/high bits of NVOS32_ATTR_FORMAT
// bit range. These provide direct access to the range limits
// without needing to split the low:high representation via
// ternary operator, thereby avoiding MISRA 14.3 violation.
#define NVOS32_ATTR_FORMAT_LOW_FIELD 16
#define NVOS32_ATTR_FORMAT_HIGH_FIELD 17
#define NVOS32_ATTR_FORMAT_PITCH 0x00000000
#define NVOS32_ATTR_FORMAT_SWIZZLED 0x00000001
#define NVOS32_ATTR_FORMAT_BLOCK_LINEAR 0x00000002
#define NVOS32_ATTR_Z_TYPE 18:18
#define NVOS32_ATTR_Z_TYPE_FIXED 0x00000000
#define NVOS32_ATTR_Z_TYPE_FLOAT 0x00000001
#define NVOS32_ATTR_ZS_PACKING 21:19
#define NVOS32_ATTR_ZS_PACKING_S8 0x00000000 // Z24S8 and S8 share definition
#define NVOS32_ATTR_ZS_PACKING_Z24S8 0x00000000
#define NVOS32_ATTR_ZS_PACKING_S8Z24 0x00000001
#define NVOS32_ATTR_ZS_PACKING_Z32 0x00000002
#define NVOS32_ATTR_ZS_PACKING_Z24X8 0x00000003
#define NVOS32_ATTR_ZS_PACKING_X8Z24 0x00000004
#define NVOS32_ATTR_ZS_PACKING_Z32_X24S8 0x00000005
#define NVOS32_ATTR_ZS_PACKING_X8Z24_X24S8 0x00000006
#define NVOS32_ATTR_ZS_PACKING_Z16 0x00000007
// NOTE: ZS packing and color packing fields are overlaid
#define NVOS32_ATTR_COLOR_PACKING NVOS32_ATTR_ZS_PACKING
#define NVOS32_ATTR_COLOR_PACKING_A8R8G8B8 0x00000000
#define NVOS32_ATTR_COLOR_PACKING_X8R8G8B8 0x00000001
//
// For virtual allocs to choose page size for the region. Specifying
// _DEFAULT will select a virtual page size that allows for a surface
// to be mixed between video and system memory and allow the surface
// to be migrated between video and system memory. For tesla chips,
// 4KB will be used. For fermi chips with dual page tables, a virtual
// address with both page tables will be used.
//
// For physical allocation on chips with page swizzle this field is
// used to select the page swizzle. This later also sets the virtual
// page size, but does not have influence over selecting a migratable
// virtual address. That must be selected when mapping the physical
// memory.
//
// BIG_PAGE = 64 KB on PASCAL
// = 64 KB or 128 KB on pre_PASCAL chips
//
// HUGE_PAGE = 2 MB on PASCAL+
// = 2 MB or 512 MB on AMPERE+
// = not supported on pre_PASCAL chips.
//
// To request for a HUGE page size,
// set NVOS32_ATTR_PAGE_SIZE to _HUGE and NVOS32_ATTR2_PAGE_SIZE_HUGE to
// the desired size.
//
#define NVOS32_ATTR_PAGE_SIZE 24:23
#define NVOS32_ATTR_PAGE_SIZE_DEFAULT 0x00000000
#define NVOS32_ATTR_PAGE_SIZE_4KB 0x00000001
#define NVOS32_ATTR_PAGE_SIZE_BIG 0x00000002
#define NVOS32_ATTR_PAGE_SIZE_HUGE 0x00000003
#define NVOS32_ATTR_LOCATION 26:25
#define NVOS32_ATTR_LOCATION_VIDMEM 0x00000000
#define NVOS32_ATTR_LOCATION_PCI 0x00000001
#define NVOS32_ATTR_LOCATION_AGP 0x00000002
#define NVOS32_ATTR_LOCATION_ANY 0x00000003
//
// _DEFAULT implies _CONTIGUOUS for video memory currently, but
// may be changed to imply _NONCONTIGUOUS in the future.
// _ALLOW_NONCONTIGUOUS enables falling back to the noncontiguous
// vidmem allocator if contig allocation fails.
//
#define NVOS32_ATTR_PHYSICALITY 28:27
#define NVOS32_ATTR_PHYSICALITY_DEFAULT 0x00000000
#define NVOS32_ATTR_PHYSICALITY_NONCONTIGUOUS 0x00000001
#define NVOS32_ATTR_PHYSICALITY_CONTIGUOUS 0x00000002
#define NVOS32_ATTR_PHYSICALITY_ALLOW_NONCONTIGUOUS 0x00000003
#define NVOS32_ATTR_COHERENCY 31:29
#define NVOS32_ATTR_COHERENCY_UNCACHED 0x00000000
#define NVOS32_ATTR_COHERENCY_CACHED 0x00000001
#define NVOS32_ATTR_COHERENCY_WRITE_COMBINE 0x00000002
#define NVOS32_ATTR_COHERENCY_WRITE_THROUGH 0x00000003
#define NVOS32_ATTR_COHERENCY_WRITE_PROTECT 0x00000004
#define NVOS32_ATTR_COHERENCY_WRITE_BACK 0x00000005
// ATTR2 fields
#define NVOS32_ATTR2_NONE 0x00000000
//
// DEFAULT - Let lower level drivers pick optimal page kind.
// PREFER_NO_ZBC - Prefer other types of compression over ZBC when
// selecting page kind.
// PREFER_ZBC - Prefer ZBC over other types of compression when
// selecting page kind.
// REQUIRE_ONLY_ZBC - Require a page kind that enables ZBC but disables
// other types of compression (i.e. 2C page kind).
// INVALID - Aliases REQUIRE_ONLY_ZBC, which is not supported
// by all RM implementations.
//
#define NVOS32_ATTR2_ZBC 1:0
#define NVOS32_ATTR2_ZBC_DEFAULT 0x00000000
#define NVOS32_ATTR2_ZBC_PREFER_NO_ZBC 0x00000001
#define NVOS32_ATTR2_ZBC_PREFER_ZBC 0x00000002
#define NVOS32_ATTR2_ZBC_REQUIRE_ONLY_ZBC 0x00000003
#define NVOS32_ATTR2_ZBC_INVALID 0x00000003
//
// DEFAULT - Highest performance cache policy that is coherent with the highest
// performance CPU mapping. Typically this is gpu cached for video
// memory and gpu uncached for system memory.
// YES - Enable gpu caching if supported on this surface type. For system
// memory this will not be coherent with direct CPU mappings.
// NO - Disable gpu caching if supported on this surface type.
// INVALID - Clients should never set YES and NO simultaneously.
//
#define NVOS32_ATTR2_GPU_CACHEABLE 3:2
#define NVOS32_ATTR2_GPU_CACHEABLE_DEFAULT 0x00000000
#define NVOS32_ATTR2_GPU_CACHEABLE_YES 0x00000001
#define NVOS32_ATTR2_GPU_CACHEABLE_NO 0x00000002
#define NVOS32_ATTR2_GPU_CACHEABLE_INVALID 0x00000003
//
// DEFAULT - GPU-dependent cache policy
// YES - Enable gpu caching for p2p mem
// NO - Disable gpu caching for p2p mem
//
#define NVOS32_ATTR2_P2P_GPU_CACHEABLE 5:4
#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_DEFAULT 0x00000000
#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_YES 0x00000001
#define NVOS32_ATTR2_P2P_GPU_CACHEABLE_NO 0x00000002
// This applies to virtual allocs only. See NVOS46_FLAGS_32BIT_POINTER.
#define NVOS32_ATTR2_32BIT_POINTER 6:6
#define NVOS32_ATTR2_32BIT_POINTER_DISABLE 0x00000000
#define NVOS32_ATTR2_32BIT_POINTER_ENABLE 0x00000001
//
// Indicates address conversion to be used, which affects what
// pitch alignment needs to be used
//
#define NVOS32_ATTR2_TILED_TYPE 7:7
#define NVOS32_ATTR2_TILED_TYPE_LINEAR 0x00000000
#define NVOS32_ATTR2_TILED_TYPE_XY 0x00000001
//
// Force SMMU mapping on GPU physical allocation in Tegra
// SMMU mapping for GPU physical allocation decided internally by RM
// This attribute provide an override to RM policy for verification purposes.
//
#define NVOS32_ATTR2_SMMU_ON_GPU 10:8
#define NVOS32_ATTR2_SMMU_ON_GPU_DEFAULT 0x00000000
#define NVOS32_ATTR2_SMMU_ON_GPU_DISABLE 0x00000001
#define NVOS32_ATTR2_SMMU_ON_GPU_ENABLE 0x00000002
//
// Make comptag allocation aligned to compression cacheline size.
// Specifying this attribute will make RM allocate comptags worth an entire
// comp cacheline. The allocation will be offset aligned to number of comptags/comp cacheline.
//
#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN 11:11
#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF 0x0
#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_ON 0x1
#define NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_DEFAULT \
NVOS32_ATTR2_ALLOC_COMPCACHELINE_ALIGN_OFF
// Allocation preferred in high or low priority memory
#define NVOS32_ATTR2_PRIORITY 13:12
#define NVOS32_ATTR2_PRIORITY_DEFAULT 0x0
#define NVOS32_ATTR2_PRIORITY_HIGH 0x1
#define NVOS32_ATTR2_PRIORITY_LOW 0x2
// PMA: Allocation is an RM internal allocation (RM-only)
#define NVOS32_ATTR2_INTERNAL 14:14
#define NVOS32_ATTR2_INTERNAL_NO 0x0
#define NVOS32_ATTR2_INTERNAL_YES 0x1
// Allocate 2C instead of 2CZ
#define NVOS32_ATTR2_PREFER_2C 15:15
#define NVOS32_ATTR2_PREFER_2C_NO 0x00000000
#define NVOS32_ATTR2_PREFER_2C_YES 0x00000001
// Allocation used by display engine; RM verifies display engine has enough
// address bits or remapper available.
#define NVOS32_ATTR2_NISO_DISPLAY 16:16
#define NVOS32_ATTR2_NISO_DISPLAY_NO 0x00000000
#define NVOS32_ATTR2_NISO_DISPLAY_YES 0x00000001
//
// !!WARNING!!!
//
// This flag is introduced as a temporary WAR to enable color compression
// without ZBC.
//
// This dangerous flag can be used by UMDs to instruct RM to skip the zbc
// table refcounting that RM does today, when the chosen PTE kind has ZBC
// support.
//
// Currently we do not have a safe per process zbc slot management and
// refcounting mechanism between RM and UMD and hence, any process can
// access any other process's zbc entry in the global zbc table (without mask)
// Inorder to flush the ZBC table for slot reuse RM cannot track which
// process is using which zbc slot. Hence RM has a global refcount for the
// zbc table to flush and reuse the entries if the PTE kind supports zbc.
//
// This scheme poses a problem if there are apps that are persistent such as
// the desktop components that can have color compression enabled which will
// always keep the refcount active. Since these apps can live without
// ZBC, UMD can disable ZBC using masks.
//
// In such a case, if UMD so chooses to disable ZBC, this flag should be used
// to skip refcounting as by default RM would refcount the ZBC table.
//
// NOTE: There is no way for RM to enforce/police this, and we totally rely
// on UMD to use a zbc mask in the pushbuffer method to prevent apps from
// accessing the ZBC table.
//
#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT 17:17
#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_NO 0x00000000
#define NVOS32_ATTR2_ZBC_SKIP_ZBCREFCOUNT_YES 0x00000001
// Allocation requires ISO bandwidth guarantees
#define NVOS32_ATTR2_ISO 18:18
#define NVOS32_ATTR2_ISO_NO 0x00000000
#define NVOS32_ATTR2_ISO_YES 0x00000001
//
// Turn off blacklist feature for video memory allocation
// This attribute should be used only by Kernel client (KMD), to mask
// the blacklisted pages for the allocation. This is done so that the clients
// will manage the above masked blacklisted pages after the allocation. It will
// return to RM's pool after the allocation was free-d.RmVidHeapCtrl returns
// NV_ERR_INSUFFICIENT_PERMISSIONS if it is being called by non-kernel clients.
//
// TODO: Project ReLingo - This term is marked for deletion. Use PAGE_OFFLINING.
#define NVOS32_ATTR2_BLACKLIST 19:19
#define NVOS32_ATTR2_BLACKLIST_ON 0x00000000
#define NVOS32_ATTR2_BLACKLIST_OFF 0x00000001
#define NVOS32_ATTR2_PAGE_OFFLINING 19:19
#define NVOS32_ATTR2_PAGE_OFFLINING_ON 0x00000000
#define NVOS32_ATTR2_PAGE_OFFLINING_OFF 0x00000001
//
// For virtual allocs to choose the HUGE page size for the region.
// NVOS32_ATTR_PAGE_SIZE must be set to _HUGE to use this.
// Currently, the default huge page is 2MB, so a request with _DEFAULT
// set will always be interpreted as 2MB.
// Not supported on pre_AMPERE chips.
//
#define NVOS32_ATTR2_PAGE_SIZE_HUGE 21:20
#define NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT 0x00000000
#define NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB 0x00000001
#define NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB 0x00000002
// Allow read-only or read-write user CPU mappings
#define NVOS32_ATTR2_PROTECTION_USER 22:22
#define NVOS32_ATTR2_PROTECTION_USER_READ_WRITE 0x00000000
#define NVOS32_ATTR2_PROTECTION_USER_READ_ONLY 0x00000001
// Allow read-only or read-write device mappings
#define NVOS32_ATTR2_PROTECTION_DEVICE 23:23
#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_WRITE 0x00000000
#define NVOS32_ATTR2_PROTECTION_DEVICE_READ_ONLY 0x00000001
//
// Force the allocation to go to guest subheap.
// This flag is used by vmiop plugin to allocate from GPA
//
#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP 27:27
#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_NO 0x00000000
#define NVOS32_ATTR2_ALLOCATE_FROM_SUBHEAP_YES 0x00000001
/**
* NVOS32 ALLOC_FLAGS
*
* NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT
*
* NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP
*
* NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN
*
* NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE
*
* NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE
*
* NVOS32_ALLOC_FLAGS_BANK_HINT
*
* NVOS32_ALLOC_FLAGS_BANK_FORCE
*
* NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT
*
* NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE
*
* NVOS32_ALLOC_FLAGS_BANK_GROW_UP
* Only relevant if bank_hint or bank_force are set
*
* NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN
* Only relevant if bank_hint or bank_force are set
*
* NVOS32_ALLOC_FLAGS_LAZY
* Lazy allocation (deferred pde, pagetable creation)
*
* NVOS32_ALLOC_FLAGS_NO_SCANOUT
* Set if surface will never be scanned out
*
* NVOS32_ALLOC_FLAGS_PITCH_FORCE
* Fail alloc if supplied pitch is not aligned
*
* NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED
* Memory handle provided to be associated with this allocation
*
* NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED
* By default memory is mapped into the CPU address space
*
* NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM
* Allocate persistent video memory
*
* NVOS32_ALLOC_FLAGS_USE_BEGIN_END
* Use rangeBegin & rangeEnd fields in allocs other than size/range
*
* NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED
* Allocate TurboCipher encrypted region
*
* NVOS32_ALLOC_FLAGS_VIRTUAL
* Allocate virtual memory address space
*
* NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX
* Force allocation internal index
*
* NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED
* This flag is depreciated and allocations will fail.
*
* NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED
* Must be used with NVOS32_ALLOC_FLAGS_VIRTUAL.
* Page tables for this allocation will be managed outside of RM.
*
* NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE
*
* NVOS32_ALLOC_FLAGS_PROTECTED
* Allocate in a protected memory region if available
*
* NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP
* Map kernel os descriptor
*
* NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE
* On WDDM all address spaces are created with MINIMIZE_PTETABLE_SIZE
* to reduce the overhead of private address spaces per application,
* at the cost of holes in the virtual address space.
*
* Shaders have short pointers that are required to be within a
* GPU dependent 32b range.
*
* MAXIMIZE_ADDRESS_SPACE will reverse the MINIMIZE_PTE_TABLE_SIZE
* flag with certain restrictions:
* - This flag only has an effect when the allocation has the side
* effect of creating a new PDE. It does not affect existing PDEs.
* - The first few PDEs of the address space are kept minimum to allow
* small applications to use fewer resources.
* - By default this operations on the 0-4GB address range.
* - If USE_BEGIN_END is specified the setting will apply to the
* specified range instead of the first 4GB.
*
* NVOS32_ALLOC_FLAGS_SPARSE
* Denote that a virtual address range is "sparse". Must be used with
* NVOS32_ALLOC_FLAGS_VIRTUAL. Creation of a "sparse" virtual address range
* denotes that an unmapped virtual address range should "not" fault but simply
* return 0's.
*
* NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED
* This a special flag that can be used only by kernel(root) clients
* to allocate memory out of a protected region of the address space
* If this flag is set by non kernel clients then the allocation will
* fail.
*
* NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC
*
* NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY
* If new pagetable need to be allocated prefer them in sysmem (if supported by the gpu)
*
* NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD
* As per KMD request to eliminate extra allocation
*
* NVOS32_ALLOC_FLAGS_WPR1
* Allocate in a WPR1 region if available
*
* NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X
* If using zcull sharing and this surface is fsaa, then don't allocate an additional non-FSAA region.
*
* NVOS32_ALLOC_FLAGS_WPR2
* Allocate in a WPR1 region if available
*/
#define NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT 0x00000001
#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_UP 0x00000002
#define NVOS32_ALLOC_FLAGS_FORCE_MEM_GROWS_DOWN 0x00000004
#define NVOS32_ALLOC_FLAGS_FORCE_ALIGN_HOST_PAGE 0x00000008
#define NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE 0x00000010
#define NVOS32_ALLOC_FLAGS_BANK_HINT 0x00000020
#define NVOS32_ALLOC_FLAGS_BANK_FORCE 0x00000040
#define NVOS32_ALLOC_FLAGS_ALIGNMENT_HINT 0x00000080
#define NVOS32_ALLOC_FLAGS_ALIGNMENT_FORCE 0x00000100
#define NVOS32_ALLOC_FLAGS_BANK_GROW_UP 0x00000000
#define NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN 0x00000200
#define NVOS32_ALLOC_FLAGS_LAZY 0x00000400
// unused 0x00000800
#define NVOS32_ALLOC_FLAGS_NO_SCANOUT 0x00001000
#define NVOS32_ALLOC_FLAGS_PITCH_FORCE 0x00002000
#define NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED 0x00004000
#define NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED 0x00008000
#define NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM 0x00010000
#define NVOS32_ALLOC_FLAGS_USE_BEGIN_END 0x00020000
#define NVOS32_ALLOC_FLAGS_TURBO_CIPHER_ENCRYPTED 0x00040000
#define NVOS32_ALLOC_FLAGS_VIRTUAL 0x00080000
#define NVOS32_ALLOC_FLAGS_FORCE_INTERNAL_INDEX 0x00100000
#define NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED 0x00200000
#define NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED 0x00400000
#define NVOS32_ALLOC_FLAGS_FORCE_DEDICATED_PDE 0x00800000
#define NVOS32_ALLOC_FLAGS_PROTECTED 0x01000000
#define NVOS32_ALLOC_FLAGS_KERNEL_MAPPING_MAP 0x02000000 // TODO BUG 2488679: fix alloc flag aliasing
#define NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE 0x02000000
#define NVOS32_ALLOC_FLAGS_SPARSE 0x04000000
#define NVOS32_ALLOC_FLAGS_USER_READ_ONLY 0x04000000 // TODO BUG 2488682: remove this after KMD transition
#define NVOS32_ALLOC_FLAGS_DEVICE_READ_ONLY 0x08000000 // TODO BUG 2488682: remove this after KMD transition
#define NVOS32_ALLOC_FLAGS_ALLOCATE_KERNEL_PRIVILEGED 0x08000000
#define NVOS32_ALLOC_FLAGS_SKIP_RESOURCE_ALLOC 0x10000000
#define NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY 0x20000000
#define NVOS32_ALLOC_FLAGS_SKIP_ALIGN_PAD 0x40000000
#define NVOS32_ALLOC_FLAGS_WPR1 0x40000000 // TODO BUG 2488672: fix alloc flag aliasing
#define NVOS32_ALLOC_FLAGS_ZCULL_DONT_ALLOCATE_SHARED_1X 0x80000000
#define NVOS32_ALLOC_FLAGS_WPR2 0x80000000 // TODO BUG 2488672: fix alloc flag aliasing
// Internal flags used for RM's allocation paths
#define NVOS32_ALLOC_INTERNAL_FLAGS_CLIENTALLOC 0x00000001 // RM internal flags - not sure if this should be exposed even. Keeping it here.
#define NVOS32_ALLOC_INTERNAL_FLAGS_SKIP_SCRUB 0x00000004 // RM internal flags - not sure if this should be exposed even. Keeping it here.
#define NVOS32_ALLOC_FLAGS_MAXIMIZE_4GB_ADDRESS_SPACE NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE // Legacy name
//
// Bitmask of flags that are only valid for virtual allocations.
//
#define NVOS32_ALLOC_FLAGS_VIRTUAL_ONLY ( \
NVOS32_ALLOC_FLAGS_VIRTUAL | \
NVOS32_ALLOC_FLAGS_LAZY | \
NVOS32_ALLOC_FLAGS_EXTERNALLY_MANAGED | \
NVOS32_ALLOC_FLAGS_SPARSE | \
NVOS32_ALLOC_FLAGS_MAXIMIZE_ADDRESS_SPACE | \
NVOS32_ALLOC_FLAGS_PREFER_PTES_IN_SYSMEMORY )
// COMPR_COVG_* allows for specification of what compression resources
// are required (_MIN) and necessary (_MAX). Default behavior is for
// RM to provide as much as possible, including none if _ANY is allowed.
// Values for min/max are (0-100, a %) * _COVG_SCALE (so max value is
// 100*100==10000). _START is used to specify the % offset into the
// region to begin the requested coverage.
// _COVG_BITS allows specification of the number of comptags per ROP tile.
// A value of 0 is default and allows RM to choose based upon MMU/FB rules.
// All other values for _COVG_BITS are arch-specific.
// Note: NVOS32_ATTR_COMPR_COVG_PROVIDED must be set for this feature
// to be available (verif-only).
#define NVOS32_ALLOC_COMPR_COVG_SCALE 10
#define NVOS32_ALLOC_COMPR_COVG_BITS 1:0
#define NVOS32_ALLOC_COMPR_COVG_BITS_DEFAULT 0x00000000
#define NVOS32_ALLOC_COMPR_COVG_BITS_1 0x00000001
#define NVOS32_ALLOC_COMPR_COVG_BITS_2 0x00000002
#define NVOS32_ALLOC_COMPR_COVG_BITS_4 0x00000003
#define NVOS32_ALLOC_COMPR_COVG_MAX 11:2
#define NVOS32_ALLOC_COMPR_COVG_MIN 21:12
#define NVOS32_ALLOC_COMPR_COVG_START 31:22
// Note: NVOS32_ALLOC_FLAGS_ZCULL_COVG_SPECIFIED must be set for this feature
// to be enabled.
// If FALLBACK_ALLOW is set, a fallback from LOW_RES_Z or LOW_RES_ZS
// to HIGH_RES_Z is allowed if the surface can't be fully covered.
#define NVOS32_ALLOC_ZCULL_COVG_FORMAT 3:0
#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_Z 0x00000000
#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_HIGH_RES_Z 0x00000002
#define NVOS32_ALLOC_ZCULL_COVG_FORMAT_LOW_RES_ZS 0x00000003
#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK 4:4
#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_DISALLOW 0x00000000
#define NVOS32_ALLOC_ZCULL_COVG_FALLBACK_ALLOW 0x00000001
// _ALLOC_COMPTAG_OFFSET allows the caller to specify the starting
// offset for the comptags for a given surface, primarily for test only.
// To specify an offset, set _USAGE_FIXED or _USAGE_MIN in conjunction
// with _START.
//
// _USAGE_FIXED sets a surface's comptagline to start at the given
// starting value. If the offset has already been assigned, then
// the alloc call fails.
//
// _USAGE_MIN sets a surface's comptagline to start at the given
// starting value or higher, depending on comptagline availability.
// In this case, if the offset has already been assigned, the next
// available comptagline (in increasing order) will be assigned.
//
// For Fermi, up to 2^17 comptags may be allowed, but the actual,
// usable limit depends on the size of the compbit backing store.
//
// For Pascal, up to 2 ^ 18 comptags may be allowed
// From Turing. up to 2 ^ 20 comptags may be allowed
//
// See also field ctagOffset in struct NVOS32_PARAMETERS.
#define NVOS32_ALLOC_COMPTAG_OFFSET_START 19:0
#define NVOS32_ALLOC_COMPTAG_OFFSET_START_DEFAULT 0x00000000
#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE 31:30
#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_DEFAULT 0x00000000
#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_OFF 0x00000000
#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_FIXED 0x00000001
#define NVOS32_ALLOC_COMPTAG_OFFSET_USAGE_MIN 0x00000002
// REALLOC flags field
#define NVOS32_REALLOC_FLAGS_GROW_ALLOCATION 0x00000000
#define NVOS32_REALLOC_FLAGS_SHRINK_ALLOCATION 0x00000001
#define NVOS32_REALLOC_FLAGS_REALLOC_UP 0x00000000 // towards/from high memory addresses
#define NVOS32_REALLOC_FLAGS_REALLOC_DOWN 0x00000002 // towards/from memory address 0
// RELEASE_COMPR, REACQUIRE_COMPR flags field
#define NVOS32_RELEASE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001
#define NVOS32_REACQUIRE_COMPR_FLAGS_MEMORY_HANDLE_PROVIDED 0x000000001
// FREE flags field
#define NVOS32_FREE_FLAGS_MEMORY_HANDLE_PROVIDED 0x00000001
// DUMP flags field
#define NVOS32_DUMP_FLAGS_TYPE 1:0
#define NVOS32_DUMP_FLAGS_TYPE_FB 0x00000000
#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_PD 0x00000001
#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VA 0x00000002
#define NVOS32_DUMP_FLAGS_TYPE_CLIENT_VAPTE 0x00000003
#define NVOS32_BLOCK_TYPE_FREE 0xFFFFFFFF
#define NVOS32_INVALID_BLOCK_FREE_OFFSET 0xFFFFFFFF
#define NVOS32_MEM_TAG_NONE 0x00000000
/*
* NV_CONTEXT_DMA_ALLOCATION_PARAMS - Allocation params to create context dma
through NvRmAlloc.
*/
typedef struct
{
NvHandle hSubDevice;
NvV32 flags;
NvHandle hMemory;
NvU64 offset NV_ALIGN_BYTES(8);
NvU64 limit NV_ALIGN_BYTES(8);
} NV_CONTEXT_DMA_ALLOCATION_PARAMS;
/*
* NV_MEMORY_ALLOCATION_PARAMS - Allocation params to create memory through
* NvRmAlloc. Flags are populated with NVOS32_ defines.
*/
typedef struct
{
NvU32 owner; // [IN] - memory owner ID
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 width; // [IN] - width of surface in pixels
NvU32 height; // [IN] - height of surface in pixels
NvS32 pitch; // [IN/OUT] - desired pitch AND returned actual pitch allocated
NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 format; // [IN/OUT] - format requested, and format allocated
NvU32 comprCovg; // [IN/OUT] - compr covg requested, and allocated
NvU32 zcullCovg; // [OUT] - zcull covg allocated
NvU64 rangeLo NV_ALIGN_BYTES(8); // [IN] - allocated memory will be limited to the range
NvU64 rangeHi NV_ALIGN_BYTES(8); // [IN] - from rangeBegin to rangeEnd, inclusive.
NvU64 size NV_ALIGN_BYTES(8); // [IN/OUT] - size of allocation - also returns the actual size allocated
NvU64 alignment NV_ALIGN_BYTES(8); // [IN] - requested alignment - NVOS32_ALLOC_FLAGS_ALIGNMENT* must be on
NvU64 offset NV_ALIGN_BYTES(8); // [IN/OUT] - desired offset if NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE is on AND returned offset
NvU64 limit NV_ALIGN_BYTES(8); // [OUT] - returned surface limit
NvP64 address NV_ALIGN_BYTES(8); // [OUT] - returned address
NvU32 ctagOffset; // [IN] - comptag offset for this surface (see NVOS32_ALLOC_COMPTAG_OFFSET)
NvHandle hVASpace; // [IN] - VASpace handle. Used when flag is VIRTUAL.
NvU32 internalflags; // [IN] - internal flags to change allocation behaviors from internal paths
NvU32 tag; // [IN] - memory tag used for debugging
} NV_MEMORY_ALLOCATION_PARAMS;
/*
* NV_OS_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create OS
* described memory through NvRmAlloc. Flags are populated with NVOS32_ defines.
*/
typedef struct
{
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 attr; // [IN] - attributes for memory placement/properties, see below
NvU32 attr2; // [IN] - attributes GPU_CACHEABLE
NvP64 descriptor NV_ALIGN_BYTES(8); // [IN] - descriptor address
NvU64 limit NV_ALIGN_BYTES(8); // [IN] - allocated size -1
NvU32 descriptorType; // [IN] - descriptor type(Virtual | nvmap Handle)
NvU32 tag; // [IN] - memory tag used for debugging
} NV_OS_DESC_MEMORY_ALLOCATION_PARAMS;
/*
* NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS - Allocation params to create a memory
* object from user allocated video memory. Flags are populated with NVOS32_*
* defines.
*/
typedef struct
{
NvU32 flags; // [IN] - allocation modifier flags, see NVOS02_FLAGS* defines
NvU64 physAddr NV_ALIGN_BYTES(8); // [IN] - physical address
NvU64 size NV_ALIGN_BYTES(8); // [IN] - mem size
NvU32 tag; // [IN] - memory tag used for debugging
NvBool bGuestAllocated; // [IN] - Set if memory is guest allocated (mapped by VMMU)
} NV_USER_LOCAL_DESC_MEMORY_ALLOCATION_PARAMS;
/*
* NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS - Allocation params to create
* memory HW resources through NvRmAlloc. Flags are populated with NVOS32_
* defines.
*/
typedef struct
{
NvU32 owner; // [IN] - memory owner ID
NvU32 flags; // [IN] - allocation modifier flags, see below ALLOC_FLAGS* defines
NvU32 type; // [IN] - surface type, see below TYPE* defines
NvU32 attr; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 attr2; // [IN/OUT] - surface attributes requested, and surface attributes allocated
NvU32 height;
NvU32 width;
NvU32 pitch;
NvU32 alignment;
NvU32 comprCovg;
NvU32 zcullCovg;
NvU32 kind;
NvP64 bindResultFunc NV_ALIGN_BYTES(8); // BindResultFunc
NvP64 pHandle NV_ALIGN_BYTES(8);
NvU64 osDeviceHandle NV_ALIGN_BYTES(8);
NvU64 size NV_ALIGN_BYTES(8);
NvU64 allocAddr NV_ALIGN_BYTES(8);
// [out] from GMMU_COMPR_INFO in drivers/common/shared/inc/mmu/gmmu_fmt.h
NvU32 compPageShift;
NvU32 compressedKind;
NvU32 compTagLineMin;
NvU32 compPageIndexLo;
NvU32 compPageIndexHi;
NvU32 compTagLineMultiplier;
// [out] fallback uncompressed kind.
NvU32 uncompressedKind;
NvU32 tag; // [IN] - memory tag used for debugging
} NV_MEMORY_HW_RESOURCES_ALLOCATION_PARAMS;
/* function OS33 */
#define NV04_MAP_MEMORY (0x00000021)
// Legacy map and unmap memory flags that don't use DRF_DEF scheme
#define NV04_MAP_MEMORY_FLAGS_NONE (0x00000000)
#define NV04_MAP_MEMORY_FLAGS_USER (0x00004000)
// New map and unmap memory flags. These flags are used for both NvRmMapMemory
// and for NvRmUnmapMemory.
// Mappings can have restricted permissions (read-only, write-only). Some
// RM implementations may choose to ignore these flags, or they may work
// only for certain memory spaces (system, AGP, video memory); in such cases,
// you may get a read/write mapping even if you asked for a read-only or
// write-only mapping.
#define NVOS33_FLAGS_ACCESS 1:0
#define NVOS33_FLAGS_ACCESS_READ_WRITE (0x00000000)
#define NVOS33_FLAGS_ACCESS_READ_ONLY (0x00000001)
#define NVOS33_FLAGS_ACCESS_WRITE_ONLY (0x00000002)
// Persistent mappings are no longer supported
#define NVOS33_FLAGS_PERSISTENT 4:4
#define NVOS33_FLAGS_PERSISTENT_DISABLE (0x00000000)
#define NVOS33_FLAGS_PERSISTENT_ENABLE (0x00000001)
// This flag is a hack to work around bug 150889. It disables the error
// checking in the RM that verifies that the client is not trying to map
// memory past the end of the memory object. This error checking needs to
// be shut off in some cases for a PAE bug workaround in certain kernels.
#define NVOS33_FLAGS_SKIP_SIZE_CHECK 8:8
#define NVOS33_FLAGS_SKIP_SIZE_CHECK_DISABLE (0x00000000)
#define NVOS33_FLAGS_SKIP_SIZE_CHECK_ENABLE (0x00000001)
// Normally, a mapping is created in the same memory space as the client -- in
// kernel space for a kernel RM client, or in user space for a user RM client.
// However, a kernel RM client can specify MEM_SPACE:USER to create a user-space
// mapping in the current RM client.
#define NVOS33_FLAGS_MEM_SPACE 14:14
#define NVOS33_FLAGS_MEM_SPACE_CLIENT (0x00000000)
#define NVOS33_FLAGS_MEM_SPACE_USER (0x00000001)
// The client can ask for direct memory mapping (i.e. no BAR1) if remappers and
// blocklinear are not required. RM can do direct mapping in this case if
// carveout is available.
// DEFAULT: Use direct mapping if available and no address/data translation
// is necessary; reflected otherwise
// DIRECT: Use direct mapping if available, even if some translation is
// necessary (the client is responsible for translation)
// REFLECTED: Always use reflected mapping
#define NVOS33_FLAGS_MAPPING 16:15
#define NVOS33_FLAGS_MAPPING_DEFAULT (0x00000000)
#define NVOS33_FLAGS_MAPPING_DIRECT (0x00000001)
#define NVOS33_FLAGS_MAPPING_REFLECTED (0x00000002)
// The client requests a fifo mapping but doesn't know the offset or length
// DEFAULT: Do error check length and offset
// ENABLE: Don't error check length and offset but have the RM fill them in
#define NVOS33_FLAGS_FIFO_MAPPING 17:17
#define NVOS33_FLAGS_FIFO_MAPPING_DEFAULT (0x00000000)
#define NVOS33_FLAGS_FIFO_MAPPING_ENABLE (0x00000001)
// The client can require that the CPU mapping be to a specific CPU address
// (akin to MAP_FIXED for mmap).
// DISABLED: RM will map the allocation at a CPU VA that RM selects.
// ENABLED: RM will map the allocation at the CPU VA specified by the address
// pass-back parameter to NvRmMapMemory
// NOTES:
// - Used for controlling CPU addresses in CUDA's unified CPU+GPU virtual
// address space
// - Only valid on NvRmMapMemory
// - Only implemented on Linux
#define NVOS33_FLAGS_MAP_FIXED 18:18
#define NVOS33_FLAGS_MAP_FIXED_DISABLE (0x00000000)
#define NVOS33_FLAGS_MAP_FIXED_ENABLE (0x00000001)
// The client can specify to the RM that the CPU virtual address range for an
// allocation should remain reserved after the allocation is unmapped.
// DISABLE: When this mapping is destroyed, RM will unmap the CPU virtual
// address space used by this allocation. On Linux this corresponds
// to calling munmap on the CPU VA region.
// ENABLE: When the map object is freed, RM will leave the CPU virtual
// address space used by allocation reserved. On Linux this means
// that RM will overwrite the previous mapping with an anonymous
// mapping of instead calling munmap.
// NOTES:
// - When combined with MAP_FIXED, this allows the client to exert
// significant control over the CPU heap
// - Used in CUDA's unified CPU+GPU virtual address space
// - Only valid on NvRmMapMemory (specifies RM's behavior whenever the
// mapping is destroyed, regardless of mechanism)
// - Only implemented on Linux
#define NVOS33_FLAGS_RESERVE_ON_UNMAP 19:19
#define NVOS33_FLAGS_RESERVE_ON_UNMAP_DISABLE (0x00000000)
#define NVOS33_FLAGS_RESERVE_ON_UNMAP_ENABLE (0x00000001)
// Systems with a coherent NVLINK2 connection between the CPU and GPU
// have the option of directly mapping video memory over that connection.
// During mapping you may specify a preference.
//
#define NVOS33_FLAGS_BUS 21:20
#define NVOS33_FLAGS_BUS_ANY 0
#define NVOS33_FLAGS_BUS_NVLINK_COHERENT 1
#define NVOS33_FLAGS_BUS_PCIE 2
// Internal use only
#define NVOS33_FLAGS_OS_DESCRIPTOR 22:22
#define NVOS33_FLAGS_OS_DESCRIPTOR_DISABLE (0x00000000)
#define NVOS33_FLAGS_OS_DESCRIPTOR_ENABLE (0x00000001)
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hDevice; // device or sub-device handle
NvHandle hMemory; // handle to memory object if provided -- NULL if not
NvU64 offset NV_ALIGN_BYTES(8);
NvU64 length NV_ALIGN_BYTES(8);
NvP64 pLinearAddress NV_ALIGN_BYTES(8); // pointer for returned address
NvU32 status;
NvU32 flags;
} NVOS33_PARAMETERS;
/* function OS34 */
#define NV04_UNMAP_MEMORY (0x00000022)
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hDevice;
NvHandle hMemory;
NvP64 pLinearAddress NV_ALIGN_BYTES(8); // ptr to virtual address of mapped memory
NvU32 status;
NvU32 flags;
} NVOS34_PARAMETERS;
/* function OS37 */
#define NV04_UPDATE_CONTEXT_DMA (0x00000025)
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hDevice;
NvHandle hDma;
NvHandle hDmaPteArray; // ctx dma for pte's
NvV32 dmaFirstPage; // first page in "real" context dma to update
NvV32 pteArrayOffset; // first pte to use from input pte array
NvV32 pteCount; // count of PTE entries to update
NvHandle hResourceHandle; // bind data handle
NvV32 status;
} NVOS37_PARAMETERS;
/* function OS38 */
#define NV04_ACCESS_REGISTRY (0x00000026)
/* parameter values */
#define NVOS38_ACCESS_TYPE_READ_DWORD 1
#define NVOS38_ACCESS_TYPE_WRITE_DWORD 2
#define NVOS38_ACCESS_TYPE_READ_BINARY 6
#define NVOS38_ACCESS_TYPE_WRITE_BINARY 7
#define NVOS38_MAX_REGISTRY_STRING_LENGTH 256
#define NVOS38_MAX_REGISTRY_BINARY_LENGTH 256
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hObject;
NvV32 AccessType;
NvV32 DevNodeLength;
NvP64 pDevNode NV_ALIGN_BYTES(8);
NvV32 ParmStrLength;
NvP64 pParmStr NV_ALIGN_BYTES(8);
NvV32 BinaryDataLength;
NvP64 pBinaryData NV_ALIGN_BYTES(8);
NvV32 Data;
NvV32 Entry;
NvV32 status;
} NVOS38_PARAMETERS;
#define NV04_ALLOC_CONTEXT_DMA (0x00000027)
/* parameter values are the same as NVOS03 -- not repeated here */
/* parameters */
typedef struct
{
NvHandle hObjectParent;
NvHandle hSubDevice;
NvHandle hObjectNew;
NvV32 hClass;
NvV32 flags;
NvU32 selector;
NvHandle hMemory;
NvU64 offset NV_ALIGN_BYTES(8);
NvU64 limit NV_ALIGN_BYTES(8);
NvV32 status;
} NVOS39_PARAMETERS;
#define NV04_GET_EVENT_DATA (0x00000028)
typedef struct
{
NvHandle hObject;
NvV32 NotifyIndex;
//
// Holds same information as that of nvgputypes.h::NvNotification's
// info32 and info16.
//
NvV32 info32;
NvU16 info16;
} NvUnixEvent;
/* parameters */
typedef struct
{
NvP64 pEvent NV_ALIGN_BYTES(8);
NvV32 MoreEvents;
NvV32 status;
} NVOS41_PARAMETERS;
/* function NVOS43 -- deleted 4/09 */
/* #define NV04_UNIFIED_FREE (0x0000002B) */
#define NVSIM01_BUS_XACT (0x0000002C)
/* parameters */
typedef struct
{
NvHandle hClient; // n/a currently
NvHandle hDevice; // n/a currently
NvU32 offset; // phy bus offset
NvU32 bar; // ~0 := phy addr, {0..2} specify gpu bar
NvU32 bytes; // # of bytes
NvU32 write; // 0 := read request
NvU32 data; // in/out based upon 'write'
NvU32 status;
} NVOS2C_PARAMETERS;
/* function NVOS2D -- deleted 4/09 */
/* #define NVSIM01_BUS_GET_IFACES (0x0000002D) */
/* function OS46 */
#define NV04_MAP_MEMORY_DMA (0x0000002E)
/* parameter values */
#define NVOS46_FLAGS_ACCESS 1:0
#define NVOS46_FLAGS_ACCESS_READ_WRITE (0x00000000)
#define NVOS46_FLAGS_ACCESS_READ_ONLY (0x00000001)
#define NVOS46_FLAGS_ACCESS_WRITE_ONLY (0x00000002)
//
// Compute shaders support both 32b and 64b pointers. This allows mappings
// to be restricted to the bottom 4GB of the address space. How _DISABLE
// is handled is chip specific and may force a pointer above 4GB.
//
#define NVOS46_FLAGS_32BIT_POINTER 2:2
#define NVOS46_FLAGS_32BIT_POINTER_DISABLE (0x00000000)
#define NVOS46_FLAGS_32BIT_POINTER_ENABLE (0x00000001)
#define NVOS46_FLAGS_PAGE_KIND 3:3
#define NVOS46_FLAGS_PAGE_KIND_PHYSICAL (0x00000000)
#define NVOS46_FLAGS_PAGE_KIND_VIRTUAL (0x00000001)
#define NVOS46_FLAGS_CACHE_SNOOP 4:4
#define NVOS46_FLAGS_CACHE_SNOOP_DISABLE (0x00000000)
#define NVOS46_FLAGS_CACHE_SNOOP_ENABLE (0x00000001)
// The client requests a CPU kernel mapping so that SW class could use it
// DEFAULT: Don't map CPU address
// ENABLE: Map CPU address
#define NVOS46_FLAGS_KERNEL_MAPPING 5:5
#define NVOS46_FLAGS_KERNEL_MAPPING_NONE (0x00000000)
#define NVOS46_FLAGS_KERNEL_MAPPING_ENABLE (0x00000001)
//
// Compute shader access control.
// GPUs that support this feature set the NV0080_CTRL_DMA_CAPS_SHADER_ACCESS_SUPPORTED
// property. These were first supported in Kepler. _DEFAULT will match the ACCESS field.
//
#define NVOS46_FLAGS_SHADER_ACCESS 7:6
#define NVOS46_FLAGS_SHADER_ACCESS_DEFAULT (0x00000000)
#define NVOS46_FLAGS_SHADER_ACCESS_READ_ONLY (0x00000001)
#define NVOS46_FLAGS_SHADER_ACCESS_WRITE_ONLY (0x00000002)
#define NVOS46_FLAGS_SHADER_ACCESS_READ_WRITE (0x00000003)
//
// How the PAGE_SIZE field is interpreted is architecture specific.
//
// On Curie chips it is ignored.
//
// On Tesla it is used to guide is used to select which type PDE
// to use. By default the RM will select 4KB for system memory
// and BIG (64KB) for video memory. BOTH is not supported.
//
// Likewise on Fermi this used to select the PDE type. Fermi cannot
// mix page sizes to a single mapping so the page size is determined
// at surface alloation time. 4KB or BIG may be specified but they
// must match the page size selected at allocation time. DEFAULT
// allows the RM to select either a single page size or both PDE,
// while BOTH forces the RM to select a dual page size PDE.
//
// BIG_PAGE = 64 KB on PASCAL
// = 64 KB or 128 KB on pre_PASCAL chips
//
// HUGE_PAGE = 2 MB on PASCAL
// = not supported on pre_PASCAL chips.
//
#define NVOS46_FLAGS_PAGE_SIZE 11:8
#define NVOS46_FLAGS_PAGE_SIZE_DEFAULT (0x00000000)
#define NVOS46_FLAGS_PAGE_SIZE_4KB (0x00000001)
#define NVOS46_FLAGS_PAGE_SIZE_BIG (0x00000002)
#define NVOS46_FLAGS_PAGE_SIZE_BOTH (0x00000003)
#define NVOS46_FLAGS_PAGE_SIZE_HUGE (0x00000004)
// Some systems allow the device to use the system L3 cache when accessing the
// system memory. For example, the iGPU on T19X can allocate from the system L3
// provided the SoC L3 cache is configured for device allocation.
//
// NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT - Use the default L3 allocation
// policy. When using this policy, device memory access will be coherent with
// non-snooping devices such as the display on Tegra.
//
// NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT - Enable L3 allocation if possible.
// When L3 allocation is enabled, device memory access may be cached, and the
// memory access will be coherent only with other snoop-enabled access. This
// flag is a hint and will be ignored if the system does not support L3
// allocation for the device. NVOS46_FLAGS_CACHE_SNOOP_ENABLE must also be set
// for this flag to be effective.
//
// Note: This flag is implemented only by rmapi_tegra. It is not implemented by
// Resman.
//
#define NVOS46_FLAGS_SYSTEM_L3_ALLOC 13:13
#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_DEFAULT (0x00000000)
#define NVOS46_FLAGS_SYSTEM_L3_ALLOC_ENABLE_HINT (0x00000001)
#define NVOS46_FLAGS_DMA_OFFSET_GROWS 14:14
#define NVOS46_FLAGS_DMA_OFFSET_GROWS_UP (0x00000000)
#define NVOS46_FLAGS_DMA_OFFSET_GROWS_DOWN (0x00000001)
//
// DMA_OFFSET_FIXED is overloaded for two purposes.
//
// 1. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_FALSE,
// DMA_OFFSET_FIXED_TRUE indicates to use the dmaOffset parameter
// for a fixed address allocation out of the VA space heap.
// DMA_OFFSET_FIXED_FALSE indicates dmaOffset input will be ignored.
//
// 2. For CTXDMA mappings that use DMA_UNICAST_REUSE_ALLOC_TRUE and
// for *ALL* non-CTXDMA mappings, DMA_OFFSET_FIXED_TRUE indicates
// to treat the input dmaOffset as an absolute virtual address
// instead of an offset relative to the virtual allocation being
// mapped into. Whether relative or absolute, the resulting
// virtual address *must* be contained within the specified
// virtual allocation.
//
// Internally, it is also required that the virtual address be aligned
// to the page size of the mapping (obviously cannot map sub-pages).
// For client flexibility the physical offset does not require page alignment.
// This is handled by adding the physical misalignment
// (internally called pteAdjust) to the returned virtual address.
// The *input* dmaOffset can account for this pteAdjust (or not),
// but the returned virtual address always will.
//
#define NVOS46_FLAGS_DMA_OFFSET_FIXED 15:15
#define NVOS46_FLAGS_DMA_OFFSET_FIXED_FALSE (0x00000000)
#define NVOS46_FLAGS_DMA_OFFSET_FIXED_TRUE (0x00000001)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP 19:16
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_DEFAULT (0x00000000)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_1 (0x00000001)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_2 (0x00000002)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_4 (0x00000003)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_8 (0x00000004)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_16 (0x00000005)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_32 (0x00000006)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_64 (0x00000007)
#define NVOS46_FLAGS_PTE_COALESCE_LEVEL_CAP_128 (0x00000008)
#define NVOS46_FLAGS_P2P 27:20
#define NVOS46_FLAGS_P2P_ENABLE 21:20
#define NVOS46_FLAGS_P2P_ENABLE_NO (0x00000000)
#define NVOS46_FLAGS_P2P_ENABLE_YES (0x00000001)
#define NVOS46_FLAGS_P2P_ENABLE_NONE NVOS46_FLAGS_P2P_ENABLE_NO
#define NVOS46_FLAGS_P2P_ENABLE_SLI NVOS46_FLAGS_P2P_ENABLE_YES
#define NVOS46_FLAGS_P2P_ENABLE_NOSLI (0x00000002)
// Subdevice ID. Reserved 3 bits for the possibility of 8-way SLI
#define NVOS46_FLAGS_P2P_SUBDEVICE_ID 24:22
#define NVOS46_FLAGS_P2P_SUBDEV_ID_SRC NVOS46_FLAGS_P2P_SUBDEVICE_ID
#define NVOS46_FLAGS_P2P_SUBDEV_ID_TGT 27:25
#define NVOS46_FLAGS_TLB_LOCK 28:28
#define NVOS46_FLAGS_TLB_LOCK_DISABLE (0x00000000)
#define NVOS46_FLAGS_TLB_LOCK_ENABLE (0x00000001)
#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC 29:29
#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_FALSE (0x00000000)
#define NVOS46_FLAGS_DMA_UNICAST_REUSE_ALLOC_TRUE (0x00000001)
#define NVOS46_FLAGS_DR_SURF 30:30
#define NVOS46_FLAGS_DR_SURF_FALSE (0x00000000)
#define NVOS46_FLAGS_DR_SURF_TRUE (0x00000001)
//
// This flag must be used with caution. Improper use can leave stale entries in the TLB,
// and allow access to memory no longer owned by the RM client or cause page faults.
// Also see corresponding flag for NvUnmapMemoryDma.
//
#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION 31:31
#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000)
#define NVOS46_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001)
/* parameters */
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hDevice; // [IN] device handle for mapping
NvHandle hDma; // [IN] dma handle for mapping
NvHandle hMemory; // [IN] memory handle for mapping
NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region
NvU64 length NV_ALIGN_BYTES(8); // [IN] limit of region
NvV32 flags; // [IN] flags
NvU64 dmaOffset NV_ALIGN_BYTES(8); // [OUT] offset of mapping
// [IN] if FLAGS_DMA_OFFSET_FIXED_TRUE
// *OR* hDma is NOT a CTXDMA handle
// (see NVOS46_FLAGS_DMA_OFFSET_FIXED)
NvV32 status; // [OUT] status
} NVOS46_PARAMETERS;
/* function OS47 */
#define NV04_UNMAP_MEMORY_DMA (0x0000002F)
#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION 0:0
#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_FALSE (0x00000000)
#define NVOS47_FLAGS_DEFER_TLB_INVALIDATION_TRUE (0x00000001)
/* parameters */
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hDevice; // [IN] device handle for mapping
NvHandle hDma; // [IN] dma handle for mapping
NvHandle hMemory; // [IN] memory handle for mapping
NvV32 flags; // [IN] flags
NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dma offset from NV04_MAP_MEMORY_DMA
NvV32 status; // [OUT] status
} NVOS47_PARAMETERS;
#define NV04_BIND_CONTEXT_DMA (0x00000031)
/* parameters */
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hChannel; // [IN] channel handle for binding
NvHandle hCtxDma; // [IN] ctx dma handle for binding
NvV32 status; // [OUT] status
} NVOS49_PARAMETERS;
/* function OS54 */
#define NV04_CONTROL (0x00000036)
#define NVOS54_FLAGS_NONE (0x00000000)
#define NVOS54_FLAGS_IRQL_RAISED (0x00000001)
#define NVOS54_FLAGS_LOCK_BYPASS (0x00000002)
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hObject;
NvV32 cmd;
NvU32 flags;
NvP64 params NV_ALIGN_BYTES(8);
NvU32 paramsSize;
NvV32 status;
} NVOS54_PARAMETERS;
/* RM Control header
*
* Replacement for NVOS54_PARAMETERS where embedded pointers are not allowed.
* Input layout for user space RM Control calls should be:
*
* +--- NVOS63_PARAMETERS ---+--- RM Control parameters ---+
*
* NVOS63_PARAMETERS::paramsSize is the size of RM Control parameters
*
*/
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hObject; // [IN] object handle
NvV32 cmd; // [IN] control command ID
NvU32 paramsSize; // [IN] size in bytes of the RM Control parameters
NvV32 status; // [OUT] status
} NVOS63_PARAMETERS;
/* function OS55 */
#define NV04_DUP_OBJECT (0x00000037)
/* parameters */
typedef struct
{
NvHandle hClient; // [IN] destination client handle
NvHandle hParent; // [IN] parent of new object
NvHandle hObject; // [INOUT] destination (new) object handle
NvHandle hClientSrc; // [IN] source client handle
NvHandle hObjectSrc; // [IN] source (old) object handle
NvU32 flags; // [IN] flags
NvU32 status; // [OUT] status
} NVOS55_PARAMETERS;
#define NV04_DUP_HANDLE_FLAGS_NONE (0x00000000)
#define NV04_DUP_HANDLE_FLAGS_REJECT_KERNEL_DUP_PRIVILEGE (0x00000001) // If set, prevents an RM kernel client from duping unconditionally
// NOTE: Do not declare a NV04_DUP_HANDLE_FLAGS_* value of 0x00000008
// until Bug 2859347 is resolved! This is due to conflicting usage
// of RS_RES_DUP_PARAMS_INTERNAL.flags to pass
// NVOS32_ALLOC_INTERNAL_FLAGS_FLA_MEMORY to an object constructor.
/* function OS56 */
#define NV04_UPDATE_DEVICE_MAPPING_INFO (0x00000038)
/* parameters */
typedef struct
{
NvHandle hClient;
NvHandle hDevice;
NvHandle hMemory;
NvP64 pOldCpuAddress NV_ALIGN_BYTES(8);
NvP64 pNewCpuAddress NV_ALIGN_BYTES(8);
NvV32 status;
} NVOS56_PARAMETERS;
/* function OS57 */
#define NV04_SHARE (0x0000003E)
/* parameters */
typedef struct
{
NvHandle hClient; // [IN] owner client handle
NvHandle hObject; // [IN] resource to share
RS_SHARE_POLICY sharePolicy; // [IN] share policy entry
NvU32 status; // [OUT] status
} NVOS57_PARAMETERS;
/* parameters */
typedef struct
{
NvU32 deviceReference;
NvU32 head;
NvU32 state;
NvU8 forceMonitorState;
NvU8 bForcePerfBiosLevel;
NvU8 bIsD3HotTransition; // [OUT] To tell client if it's a D3Hot transition
NvU32 fastBootPowerState;
} NVPOWERSTATE_PARAMETERS, *PNVPOWERSTATE_PARAMETERS;
/***************************************************************************\
|* Object Allocation Parameters *|
\***************************************************************************/
// GR engine creation parameters
typedef struct {
NvU32 version; // set to 0x2
NvU32 flags; // input param from a rm client (no flags are currently defined)
NvU32 size; // sizeof(NV_GR_ALLOCATION_PARAMETERS)
NvU32 caps; // output param for a rm client - class dependent
} NV_GR_ALLOCATION_PARAMETERS;
//
// NvAlloc parameters for NV03_DEVICE_XX class
// hClientShare
// For NV50+ this can be set to virtual address space for this
// device. On previous chips this field is ignored. There are
// three possible settings
// NV01_NULL_OBJECT - Use the default global VA space
// Handle to current client - Create a new private address space
// Handle to another client - Attach to other clients address space
// flags
// MAP_PTE_GLOBALLY Deprecated.
// MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page
// tables. Depending on allocation pattern
// this may actually use more instance memory.
// RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This
// is now enabled by default.
// VASPACE_SIZE Honor vaSpaceSize field.
//
// MAP_PTE Deprecated.
//
// VASPACE_IS_MIRRORED This flag will tell RM to create a mirrored
// kernel PDB for the address space associated
// with this device. When this flag is set
// the address space covered by the top PDE
// is restricted and cannot be allocated out of.
//
//
// VASPACE_BIG_PAGE_SIZE_64k ***Warning this flag will be deprecated do not use*****
// VASPACE_BIG_PAGE_SIZE_128k This flag will choose the big page size of the VASPace
// to 64K/128k if the system supports a configurable size.
// If the system does not support a configurable size then
// defaults will be chosen.
// If the user sets both these bits then this API will fail.
//
// SHARED_MANAGEMENT
// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. ***
//
//
// hTargetClient/hTargetDevice
// Deprecated. Can be deleted once client code has removed references.
//
// vaBase
// *** Warning: This will be deprecated - see NV_VASPACE_ALLOCATION_PARAMETERS. ***
//
// vaSpaceSize
// Set the size of the VA space used for this client if allocating
// a new private address space. Is expressed as a size such as
// (1<<32) for a 32b address space. Reducing the size of the address
// space allows the dma chip specific code to reduce the instance memory
// used for page tables.
//
// vaMode
// The vaspace allocation mode. There are three modes supported:
// 1. SINGLE_VASPACE
// An old abstraction that provides a single VA space under a
// device and it's allocated implicityly when an object requires a VA
// space. Typically, this VA space is also shared across clients.
//
// 2. OPTIONAL_MULTIPLE_VASPACES
// Global + multiple private va spaces. In this mode, the old abstraction,
// a single vaspace under a device that is allocated implicitly is still
// being supported. A private VA space is an entity under a device, which/
// cannot be shared with other clients, but multiple channels under the
// same device can still share a private VA space.
// Private VA spaces (class:90f1,FERMI_VASPACE_A) can be allocated as
// objects through RM APIs. This mode requires the users to know what they
// are doing in terms of using VA spaces. Page fault can easily occur if
// one is not careful with a mixed of an implicit VA space and multiple
// VA spaces.
//
// 3. MULTIPLE_VASPACES
// In this mode, all VA spaces have to be allocated explicitly through RM
// APIs and users have to specify which VA space to use for each object.
// This case prevents users to use context dma, which is not supported and
// can be misleading if used. Therefore, it's more a safeguard mode to
// prevent people making mistakes that are hard to debug.
//
// DEFAULT MODE: 2. OPTIONAL_MULTIPLE_VASPACES
//
// See NV0080_ALLOC_PARAMETERS for allocation parameter structure.
//
#define NV_DEVICE_ALLOCATION_SZNAME_MAXLEN 128
#define NV_DEVICE_ALLOCATION_FLAGS_NONE (0x00000000)
#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE_GLOBALLY (0x00000001)
#define NV_DEVICE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE (0x00000002)
#define NV_DEVICE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS (0x00000004)
#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SIZE (0x00000008)
#define NV_DEVICE_ALLOCATION_FLAGS_MAP_PTE (0x00000010)
#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_TARGET (0x00000020)
#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_SHARED_MANAGEMENT (0x00000100)
#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_64k (0x00000200)
#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_BIG_PAGE_SIZE_128k (0x00000400)
#define NV_DEVICE_ALLOCATION_FLAGS_RESTRICT_RESERVED_VALIMITS (0x00000800)
/*
*TODO: Delete this flag once CUDA moves to the ctrl call
*/
#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_IS_MIRRORED (0x00000040)
// XXX NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED should not
// should not be exposed to clients. It should be the default RM
// behavior.
//
// Until it is made the default, certain clients such as OpenGL
// might still need PTABLE allocations to go through PMA, so this
// flag has been temporary exposed.
//
// See bug 1880192
#define NV_DEVICE_ALLOCATION_FLAGS_VASPACE_PTABLE_PMA_MANAGED (0x00001000)
//
// Indicates this device is being created by guest and requires a
// HostVgpuDeviceKernel creation in client.
//
#define NV_DEVICE_ALLOCATION_FLAGS_HOST_VGPU_DEVICE (0x00002000)
//
// Indicates this device is being created for VGPU plugin use.
// Requires a HostVgpuDevice handle to indicate the guest on which
// this plugin operates.
//
#define NV_DEVICE_ALLOCATION_FLAGS_PLUGIN_CONTEXT (0x00004000)
#define NV_DEVICE_ALLOCATION_VAMODE_OPTIONAL_MULTIPLE_VASPACES (0x00000000)
#define NV_DEVICE_ALLOCATION_VAMODE_SINGLE_VASPACE (0x00000001)
#define NV_DEVICE_ALLOCATION_VAMODE_MULTIPLE_VASPACES (0x00000002)
/*
* NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS.flags values.
*
* These flags may apply to all channel types: PIO, DMA, and GPFIFO.
* They are also designed so that zero is always the correct default.
*
* NVOS04_FLAGS_CHANNEL_TYPE:
* This flag specifies the type of channel to allocate. Legal values
* for this flag include:
*
* NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL:
* This flag specifies that a physical channel is to be allocated.
*
* NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL:
* OBSOLETE - NOT SUPPORTED
*
* NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL:
* OBSOLETE - NOT SUPPORTED
*/
/* valid NVOS04_FLAGS_CHANNEL_TYPE values */
#define NVOS04_FLAGS_CHANNEL_TYPE 1:0
#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL 0x00000000
#define NVOS04_FLAGS_CHANNEL_TYPE_VIRTUAL 0x00000001 // OBSOLETE
#define NVOS04_FLAGS_CHANNEL_TYPE_PHYSICAL_FOR_VIRTUAL 0x00000002 // OBSOLETE
/*
* NVOS04_FLAGS_VPR:
* This flag specifies if channel is intended for work with
* Video Protected Regions (VPR)
*
* NVOS04_FLAGS_VPR_TRUE:
* The channel will only write to protected memory regions.
*
* NVOS04_FLAGS_VPR_FALSE:
* The channel will never read from protected memory regions.
*/
#define NVOS04_FLAGS_VPR 2:2
#define NVOS04_FLAGS_VPR_FALSE 0x00000000
#define NVOS04_FLAGS_VPR_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING:
* This flag specifies if the channel can skip refcounting of potentially
* accessed mappings on job kickoff. This flag is only meaningful for
* kernel drivers which perform refcounting of memory mappings.
*
* NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE:
* The channel cannot not skip refcounting of memory mappings
*
* NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE:
* The channel can skip refcounting of memory mappings
*/
#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING 3:3
#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_SKIP_MAP_REFCOUNTING_TRUE 0x00000001
/*
* NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE:
* This flag specifies which "runqueue" the allocated channel will be
* executed on in a TSG. Channels on different runqueues within a TSG
* may be able to feed methods into the engine simultaneously.
* Non-default values are only supported on GP10x and later and only for
* channels within a TSG.
*/
#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE 4:4
#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_DEFAULT 0x00000000
#define NVOS04_FLAGS_GROUP_CHANNEL_RUNQUEUE_ONE 0x00000001
/*
* NVOS04_FLAGS_PRIVILEGED_CHANNEL:
* This flag tells RM whether to give the channel admin privilege. This
* flag will only take effect if the client is GSP-vGPU plugin. It is
* needed so that guest can update page tables in physical mode and do
* scrubbing.
*/
#define NVOS04_FLAGS_PRIVILEGED_CHANNEL 5:5
#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_FALSE 0x00000000
#define NVOS04_FLAGS_PRIVILEGED_CHANNEL_TRUE 0x00000001
/*
* NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING:
* This flags tells RM not to schedule a newly created channel within a
* channel group immediately even if channel group is currently scheduled.
* Channel will not be scheduled until NVA06F_CTRL_GPFIFO_SCHEDULE is
* invoked. This is used eg. for CUDA which needs to do additional
* initialization before starting up a channel.
* Default is FALSE.
*/
#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING 6:6
#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_FALSE 0x00000000
#define NVOS04_FLAGS_DELAY_CHANNEL_SCHEDULING_TRUE 0x00000001
/*
* NVOS04_FLAGS_DENY_PHYSICAL_MODE_CE:
* This flag specifies whether or not to deny access to the physical
* mode of CopyEngine regardless of whether or not the client handle
* is admin. If set to true, this channel allocation will always result
* in an unprivileged channel. If set to false, the privilege of the channel
* will depend on the privilege level of the client handle.
* This is primarily meant for vGPU since all client handles
* granted to guests are admin.
*/
#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE 7:7
#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_DENY_PHYSICAL_MODE_CE_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE
*
* This flag specifies the channel offset in terms of within a page of
* USERD. For example, value 3 means the 4th channel within a USERD page.
* Given the USERD size is 512B, we will have 8 channels total, so 3 bits
* are reserved.
*
* When _USERD_INDEX_FIXED_TRUE is set but INDEX_PAGE_FIXED_FALSE is set,
* it will ask for a new USERD page.
*
*/
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_VALUE 10:8
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED 11:11
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_FIXED_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE
*
* This flag specifies the channel offset in terms of USERD page. When
* this PAGE_FIXED_TRUE is set, the INDEX_FIXED_FALSE bit should also
* be set, otherwise INVALID_STATE will be returned.
*
* And the field _USERD_INDEX_VALUE will be used to request the specific
* offset within a USERD page.
*/
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_VALUE 20:12
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED 21:21
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_USERD_INDEX_PAGE_FIXED_TRUE 0x00000001
/*
* NVOS04_FLAGS_DENY_AUTH_LEVEL_PRIV
* This flag specifies whether or not to deny access to the privileged
* host methods TLB_INVALIDATE and ACCESS_COUNTER_CLR
*/
#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV 22:22
#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_DENY_AUTH_LEVEL_PRIV_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER
*
* This flag specifies scrubbing should be skipped for any internal
* allocations made for this channel from PMA using ctx buf pools.
* Only kernel clients are allowed to use this setting.
*/
#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER 23:23
#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_SKIP_SCRUBBER_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO
*
* This flag specifies that the client is expected to map USERD themselves
* and RM need not do so.
*/
#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO 24:24
#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_CLIENT_MAP_FIFO_TRUE 0x00000001
/*
* NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL
*/
#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL 25:25
#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_FALSE 0x00000000
#define NVOS04_FLAGS_SET_EVICT_LAST_CE_PREFETCH_CHANNEL_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT
*
* This flag specifies whether the channel calling context is from CPU
* VGPU plugin.
*/
#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT 26:26
#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_VGPU_PLUGIN_CONTEXT_TRUE 0x00000001
/*
* NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT
*
* This flag specifies the channel PBDMA ACQUIRE timeout option.
* _FALSE to disable it, _TRUE to enable it.
* When this flag is enabled, if a host semaphore acquire does not
* complete in about 2 sec, it will time out and trigger a RC error.
*/
#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT 27:27
#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_FALSE 0x00000000
#define NVOS04_FLAGS_CHANNEL_PBDMA_ACQUIRE_TIMEOUT_TRUE 0x00000001
/*
* NVOS04_FLAGS_GROUP_CHANNEL_THREAD:
* This flags specifies the thread id in which an allocated channel
* will be executed in a TSG. The relationship between the thread id
* in A TSG and respective definitions are implementation specific.
* Also, not all classes will be supported at thread > 0.
* This field cannot be used on non-TSG channels and must be set to
* the default value (0) in that case. If thread > 0 on a non-TSG
* channel, the allocation will fail
*/
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD 29:28
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_DEFAULT 0x00000000
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_ONE 0x00000001
#define NVOS04_FLAGS_GROUP_CHANNEL_THREAD_TWO 0x00000002
#define NVOS04_FLAGS_MAP_CHANNEL 30:30
#define NVOS04_FLAGS_MAP_CHANNEL_FALSE 0x00000000
#define NVOS04_FLAGS_MAP_CHANNEL_TRUE 0x00000001
#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC 31:31
#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE 0x00000000
#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE 0x00000001
typedef struct
{
NvU64 base NV_ALIGN_BYTES(8);
NvU64 size NV_ALIGN_BYTES(8);
NvU32 addressSpace;
NvU32 cacheAttrib;
} NV_MEMORY_DESC_PARAMS;
typedef struct
{
NvHandle hObjectError; // error context DMA
NvHandle hObjectBuffer; // no longer used
NvU64 gpFifoOffset NV_ALIGN_BYTES(8); // offset to beginning of GP FIFO
NvU32 gpFifoEntries; // number of GP FIFO entries
NvU32 flags;
NvHandle hContextShare; // context share handle
NvHandle hVASpace; // VASpace for the channel
NvHandle hUserdMemory[NVOS_MAX_SUBDEVICES]; // handle to UserD memory object for channel, ignored if hUserdMemory[0]=0
NvU64 userdOffset[NVOS_MAX_SUBDEVICES] NV_ALIGN_BYTES(8); // offset to beginning of UserD within hUserdMemory[x]
NvU32 engineType; // engine type(NV2080_ENGINE_TYPE_*) with which this channel is associated
NvU32 cid; // Channel identifier that is unique for the duration of a RM session
NvU32 subDeviceId; // One-hot encoded bitmask to match SET_SUBDEVICE_MASK methods
NvHandle hObjectEccError; // ECC error context DMA
NV_MEMORY_DESC_PARAMS instanceMem;
NV_MEMORY_DESC_PARAMS userdMem;
NV_MEMORY_DESC_PARAMS ramfcMem;
NV_MEMORY_DESC_PARAMS mthdbufMem;
NvHandle hPhysChannelGroup; // reserved
NvU32 internalFlags; // reserved
NV_MEMORY_DESC_PARAMS errorNotifierMem; // reserved
NV_MEMORY_DESC_PARAMS eccErrorNotifierMem; // reserved
NvU32 ProcessID; // reserved
NvU32 SubProcessID; // reserved
} NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS;
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_ERROR 0x00000000
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE_WORK_SUBMIT_TOKEN 0x00000001
#define NV_CHANNELGPFIFO_NOTIFICATION_TYPE__SIZE_1 2
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_VALUE 14:0
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS 15:15
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_TRUE 0x1
#define NV_CHANNELGPFIFO_NOTIFICATION_STATUS_IN_PROGRESS_FALSE 0x0
typedef struct
{
NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS gpfifoAllocationParams;
NvHandle hKernelChannel;
} NV_PHYSICALCHANNEL_ALLOC_PARAMS;
typedef struct
{
NvHandle hRunlistBase; // Handle to physmem runlist base
NvU32 engineID; // Engine associated with the runlist
} NV_CHANNELRUNLIST_ALLOCATION_PARAMETERS;
typedef struct
{
NvV32 channelInstance; // One of the n channel instances of a given channel type.
// Note that core channel has only one instance
// while all others have two (one per head).
NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer
NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications
NvU32 offset; // Initial offset for put/get, usually zero.
NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs
NvU32 flags;
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001
} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS;
typedef struct
{
NvV32 channelInstance; // One of the n channel instances of a given channel type.
// All PIO channels have two instances (one per head).
NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors.
NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel
} NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS;
// Used for allocating a channel group
typedef struct
{
NvHandle hObjectError; // Error notifier for TSG
NvHandle hObjectEccError; // ECC Error notifier for TSG
NvHandle hVASpace; // VA space handle for TSG
NvU32 engineType; // Engine to which all channels in this TSG are associated with
NvBool bIsCallingContextVgpuPlugin;
} NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS;
/*
* @params:
* @engineId : Engine to which the software runlist be associated with.
* @maxTSGs : Maximum number of TSG entries that will be submitted in this software runlist
* The size of the runlist buffer will be determined by
* 2 * // double buffer
* maxTSGs * // determined by KMD
* maxChannelPerTSG * // Determined by RM
* sizeof(RunlistEntry) // Determined by HW format
* @qosIntrEnableMask: QOS Interrupt bitmask that needs to be enabled for the SW runlist defined below.
*/
typedef struct
{
NvU32 engineId; //(IN)
NvU32 maxTSGs; //(IN) // Size of the RM could return error if the request cannot be accommodated.
NvU32 qosIntrEnableMask; //(IN) // Bitmask for QOS interrupts that needs to be enabled
} NV_SWRUNLIST_ALLOCATION_PARAMS;
#define NV_SWRUNLIST_QOS_INTR_NONE 0x00000000
#define NV_SWRUNLIST_QOS_INTR_RUNLIST_AND_ENG_IDLE_ENABLE NVBIT32(0)
#define NV_SWRUNLIST_QOS_INTR_RUNLIST_IDLE_ENABLE NVBIT32(1)
#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_ENABLE NVBIT32(2)
#define NV_SWRUNLIST_QOS_INTR_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLE NVBIT32(3)
typedef struct
{
NvU32 size;
NvU32 caps;
} NV_ME_ALLOCATION_PARAMETERS;
typedef struct
{
NvU32 size;
NvU32 prohibitMultipleInstances;
NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2
} NV_BSP_ALLOCATION_PARAMETERS;
//
// These are referenced by mdiag mods tests, but do not appear to be used during
// in the RM any longer
//
#define NV_VP_ALLOCATION_FLAGS_STANDARD_UCODE (0x00000000)
#define NV_VP_ALLOCATION_FLAGS_STATIC_UCODE (0x00000001)
#define NV_VP_ALLOCATION_FLAGS_DYNAMIC_UCODE (0x00000002)
//
// NV_VP_ALLOCATION_PARAMETERS.flags
//
// NV_VP_ALLOCATION_FLAGS_AVP_CLIENT are used by Tegra to specify if
// the current allocation with be used by Video or Audio
//
#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_VIDEO (0x00000000)
#define NV_VP_ALLOCATION_FLAGS_AVP_CLIENT_AUDIO (0x00000001)
typedef struct
{
NvU32 size;
NvU32 caps;
NvU32 flags;
NvU32 altUcode;
NvP64 rawUcode NV_ALIGN_BYTES(8);
NvU32 rawUcodeSize;
NvU32 numSubClasses;
NvU32 numSubSets;
NvP64 subClasses NV_ALIGN_BYTES(8);
NvU32 prohibitMultipleInstances;
NvP64 pControl NV_ALIGN_BYTES(8); // Used by Tegra to return a mapping to NvE276Control
NvHandle hMemoryCmdBuffer NV_ALIGN_BYTES(8); // Used by Tegra to specify cmd buffer
NvU64 offset NV_ALIGN_BYTES(8); // Used by Tegra to specify an offset into the cmd buffer
} NV_VP_ALLOCATION_PARAMETERS;
typedef struct
{
NvU32 size;
NvU32 prohibitMultipleInstances;
} NV_PPP_ALLOCATION_PARAMETERS;
typedef struct
{
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC?
NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2
} NV_MSENC_ALLOCATION_PARAMETERS;
typedef struct
{
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of SEC2?
} NV_SEC2_ALLOCATION_PARAMETERS;
typedef struct
{
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG?
NvU32 engineInstance;
} NV_NVJPG_ALLOCATION_PARAMETERS;
typedef struct
{
NvU32 size;
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA?
} NV_OFA_ALLOCATION_PARAMETERS;
#define NV04_BIND_ARBITRARY_CONTEXT_DMA (0x00000039)
/* parameters */
#define NV04_GET_MEMORY_INFO (0x0000003A)
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hDevice; // [IN] device handle for mapping
NvHandle hMemory; // [IN] memory handle for mapping
NvU64 offset NV_ALIGN_BYTES(8); // [IN] offset of region
NvU64 physAddr NV_ALIGN_BYTES(8); // [OUT] Physical Addr
NvV32 status; // [OUT] status
} NVOS58_PARAMETERS;
/* function OS59 */
#define NV04_MAP_MEMORY_DMA_OFFSET (0x0000003B)
/* parameters */
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hDevice; // [IN] device handle for mapping
NvHandle hDma; // [IN] dma handle for mapping
NvU32 dmaFirstPage; // [IN] numPages
NvU32 numPages; // [IN] numPages
NvV32 flags; // [IN] flags
NvU64 offset NV_ALIGN_BYTES(8); // [IN] Dma Offset
NvHandle hDmaPteArray; // ctx dma for pte's
NvV32 status; // [OUT] status
} NVOS59_PARAMETERS;
/* function OS60 */
#define NV04_UNMAP_MEMORY_DMA_OFFSET (0x0000003C)
/* parameters */
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hDevice; // [IN] device handle for mapping
NvHandle hDma; // [IN] dma handle for mapping
NvU32 numPages; // [IN] numPages
NvU64 dmaOffset NV_ALIGN_BYTES(8); // [IN] dmaOffset
NvV32 status; // [OUT] status
} NVOS60_PARAMETERS;
#define NV04_ADD_VBLANK_CALLBACK (0x0000003D)
#include "class/cl9010.h" // for OSVBLANKCALLBACKPROC
/* parameters */
/* NOTE: the "void* pParm's" below are ok (but unfortunate) since this interface
can only be used by other kernel drivers which must share the same ptr-size */
typedef struct
{
NvHandle hClient; // [IN] client handle
NvHandle hDevice; // [IN] device handle for mapping
NvHandle hVblank; // [IN] Vblank handle for control
OSVBLANKCALLBACKPROC pProc; // Routine to call at vblank time
NvV32 LogicalHead; // Logical Head
void *pParm1;
void *pParm2;
NvU32 bAdd; // Add or Delete
NvV32 status; // [OUT] status
} NVOS61_PARAMETERS;
/**
* @brief NvAlloc parameters for VASPACE classes
*
* Used to create a new private virtual address space.
*
* index
* Tegra: With TEGRA_VASPACE_A, index specifies the IOMMU
* virtual address space to be created. Based on the
* index, RM/NVMEM will decide the HW ASID to be used with
* this VA Space. "index" takes values from the
* NVMEM_CLIENT_* defines in
* "drivers/common/inc/tegra/memory/ioctl.h".
*
* Big GPU: With FERMI_VASPACE_A, see NV_VASPACE_ALLOCATION_INDEX_GPU_*.
*
* flags
* MINIMIZE_PTETABLE_SIZE Pass hint to DMA HAL to use partial page tables.
* Depending on allocation pattern this may actually
* use more instance memory.
*
* RETRY_PTE_ALLOC_IN_SYS Fallback to PTEs allocation in sysmem. This is now
* enabled by default.
*
* SHARED_MANAGEMENT
* Indicates management of the VA space is shared with another
* component (e.g. driver layer, OS, etc.).
*
* The initial VA range from vaBase (inclusive) through vaSize (exclusive)
* is managed by RM. The range must be aligned to a top-level PDE's VA
* coverage since backing page table levels for this range are managed by RM.
* All normal RM virtual memory management APIs work within this range.
*
* An external component can manage the remaining VA ranges,
* from 0 (inclusive) to vaBase (exclusive) and from vaSize (inclusive) up to the
* maximum VA limit supported by HW.
* Management of these ranges includes VA sub-allocation and the
* backing lower page table levels.
*
* The top-level page directory is special since it is a shared resource.
* Management of the page directory is as follows:
* 1. Initially RM allocates a page directory for RM-managed PDEs.
* 2. The external component may create a full page directory and commit it
* with NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY.
* This will copy the RM-managed PDEs from the RM-managed page directory
* into the external page directory and commit channels to the external page directory.
* After this point RM will update the external page directory directly for
* operations that modify RM-managed PDEs.
* 3. The external component may use NV0080_CTRL_CMD_DMA_SET_PAGE_DIRECTORY repeatedly
* if it needs to update the page directory again (e.g. to resize or migrate).
* This will copy the RM-managed PDEs from the old external page directory
* into the new external page directory and commit channels to the new page directory.
* 4. The external component may restore management of the page directory back to
* RM with NV0080_CTRL_CMD_DMA_UNSET_PAGE_DIRECTORY.
* This will copy the RM-managed PDEs from the external page directory
* into the RM-managed page directory and commit channels to the RM-managed page directory.
* After this point RM will update the RM-managed page directory for
* operations that modify RM-managed PDEs.
* Note that operations (2) and (4) are symmetric - the RM perspective of management is identical
* before and after a sequence of SET => ... => UNSET.
*
* IS_MIRRORED <to be deprecated once CUDA uses EXTERNALLY_MANAGED>
* This flag will tell RM to create a mirrored
* kernel PDB for the address space associated
* with this device. When this flag is set
* the address space covered by the top PDE
* is restricted and cannot be allocated out of.
* ENABLE_PAGE_FAULTING
* Enable page faulting if the architecture supports it.
* As of now page faulting is only supported for compute on pascal+.
* IS_EXTERNALLY_OWNED
* This vaspace that has been allocated will be managed by
* an external driver. RM will not own the pagetables for this vaspace.
*
* ENABLE_NVLINK_ATS
* Enables VA translation for this address space using NVLINK ATS.
* Note, the GMMU page tables still exist and take priority over NVLINK ATS.
* VA space object creation will fail if:
* - hardware support is not available (NV_ERR_NOT_SUPPORTED)
* - incompatible options IS_MIRRORED or IS_EXTERNALLY_OWNED are set (NV_ERR_INVALID_ARGUMENT)
* IS_FLA
* Sets FLA flag for this VASPACE
*
* ALLOW_ZERO_ADDRESS
* Allows VASPACE Range to start from zero
* SKIP_SCRUB_MEMPOOL
* Skip scrubbing in MemPool
*
* vaBase [in, out]
* On input, the lowest usable base address of the VA space.
* If 0, RM will pick a default value - 0 is always reserved to respresent NULL pointers.
* The value must be aligned to the largest page size of the VA space.
* Larger values aid in debug since offsets added to NULL pointers will still fault.
*
* On output, the actual usable base address is returned.
*
* vaSize [in,out]
* On input, requested size of the virtual address space in bytes.
* Requesting a smaller size reduces the memory required for the initial
* page directory, but the VAS may be resized later (NV0080_CTRL_DMA_SET_VA_SPACE_SIZE).
* If 0, the default VA space size will be used.
*
* On output, the actual size of the VAS in bytes.
* NOTE: This corresponds to the VA_LIMIT + 1, so the usable size is (vaSize - vaBase).
*
* bigPageSIze
* Set the size of the big page in this address space object. Current HW supports
* either 64k or 128k as the size of the big page. HW that support multiple big
* page size per address space will use this size. Hw that do not support this feature
* will override to the default big page size that is supported by the system.
* If the big page size value is set to ZERO then we will pick the default page size
* of the system.
**/
typedef struct
{
NvU32 index;
NvV32 flags;
NvU64 vaSize NV_ALIGN_BYTES(8);
NvU64 vaStartInternal NV_ALIGN_BYTES(8);
NvU64 vaLimitInternal NV_ALIGN_BYTES(8);
NvU32 bigPageSize;
NvU64 vaBase NV_ALIGN_BYTES(8);
} NV_VASPACE_ALLOCATION_PARAMETERS;
#define NV_VASPACE_ALLOCATION_FLAGS_NONE (0x00000000)
#define NV_VASPACE_ALLOCATION_FLAGS_MINIMIZE_PTETABLE_SIZE BIT(0)
#define NV_VASPACE_ALLOCATION_FLAGS_RETRY_PTE_ALLOC_IN_SYS BIT(1)
#define NV_VASPACE_ALLOCATION_FLAGS_SHARED_MANAGEMENT BIT(2)
#define NV_VASPACE_ALLOCATION_FLAGS_IS_EXTERNALLY_OWNED BIT(3)
#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_NVLINK_ATS BIT(4)
#define NV_VASPACE_ALLOCATION_FLAGS_IS_MIRRORED BIT(5)
#define NV_VASPACE_ALLOCATION_FLAGS_ENABLE_PAGE_FAULTING BIT(6)
#define NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT BIT(7)
#define NV_VASPACE_ALLOCATION_FLAGS_ALLOW_ZERO_ADDRESS BIT(8)
#define NV_VASPACE_ALLOCATION_FLAGS_IS_FLA BIT(9)
#define NV_VASPACE_ALLOCATION_FLAGS_SKIP_SCRUB_MEMPOOL BIT(10)
#define NV_VASPACE_ALLOCATION_FLAGS_OPTIMIZE_PTETABLE_MEMPOOL_USAGE BIT(11)
#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default
#define NV_VASPACE_ALLOCATION_INDEX_GPU_HOST 0x01 //<! Acquire reference to BAR1 VAS.
#define NV_VASPACE_ALLOCATION_INDEX_GPU_GLOBAL 0x02 //<! Acquire reference to global VAS.
#define NV_VASPACE_ALLOCATION_INDEX_GPU_DEVICE 0x03 //<! Acquire reference to device vaspace
#define NV_VASPACE_ALLOCATION_INDEX_GPU_FLA 0x04 //<! Acquire reference to FLA VAS.
#define NV_VASPACE_ALLOCATION_INDEX_GPU_MAX 0x05 //<! Increment this on adding index entries
#define NV_VASPACE_BIG_PAGE_SIZE_64K (64 * 1024)
#define NV_VASPACE_BIG_PAGE_SIZE_128K (128 * 1024)
/**
* @brief NvAlloc parameters for FERMI_CONTEXT_SHARE_A class
*
* Used to create a new context share object for use by a TSG channel.
* Context share is now used to represent a subcontext within a TSG.
* Refer subcontexts-rm-design.docx for more details.
*
* hVASpace
* Handle of VA Space object associated with the context share.
* All channels using the same using the context share the same va space.
*
* flags
* Options for the context share allocation.
*
* NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT
* Used to specify the subcontext slot
* SYNC
* Use synchronous graphics & compute subcontext
* In VOLTA+ chips, this represent VEID 0
* In pre-VOLTA chips, this represent SCG type 0
* ASYNC
* Use asynchronous compute subcontext
* In VOLTA+ chips, this represent a VEID greater than 0
* In pre-VOLTA chips, this represent SCG type 1
* SPECIFIED
* Force the VEID specified in the subctxId parameter.
* This flag is intended for verif. i.e testing VEID reuse etc.
*
* subctxId
* As input, it is used to specify the subcontext ID, when the _SPECIFIED flag is set.
* As output, it is used to return the subcontext ID allocated by RM.
* This field is intended for verif.
**/
typedef struct
{
NvHandle hVASpace;
NvU32 flags;
NvU32 subctxId;
} NV_CTXSHARE_ALLOCATION_PARAMETERS;
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT 1:0
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SYNC (0x00000000)
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC (0x00000001)
#define NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_SPECIFIED (0x00000002)
/**
* @brief RmTimeoutControl parameters
*
* Used to set various timeout-related features in RM.
*
* cmd
* The timeout-related command to issue to RM.
*
* value
* Used by command, such as the timeout to be set, in milliseconds.
**/
typedef struct
{
NvU32 cmd;
NvU32 timeoutInMs;
NvU32 deviceInstance;
} NV_TIMEOUT_CONTROL_PARAMETERS;
#define NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT (0x00000002)
#define NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT (0x00000003)
// NV_TIMEOUT_CONTROL_CMD_SET_DEVICE_TIMEOUT sets a maximum timeout value for
// any RM call on a specific device on any thread. It uses 'timeoutInMs'
// as the target timeout and 'deviceInstance' as the target device.
// NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT resets the device timeout to its
// default value. It uses 'deviceInstance' as the target device.
/**
* @brief GspTestGetRpcMessageData parameters
*
* This API is used by the user-mode GSP firmware RM to get RPC message data
* from the kernel-mode GSP client RM.
*
* This API is only supported in the GSP testbed environment.
*
* blockNum
* Specifies block number of message data to return. A value of 0
* indicates that the (default) message header and body should be returned
* in the buffer. If additional RPC-specific data is required it can
* be read by continually incrementing the block number and reading the
* next block in sequence.
* msgBufferSize
* Size (in bytes) of buffer pointed to by pMsgBuffer.
* pMsgBuffer
* Address of user-buffer into which RPC message data will be copied.
* status
* Returns status of call.
**/
typedef struct
{
NvU32 blockNum; // [IN] block # of data to get
NvU32 bufferSize; // [IN] size of pBuffer
NvP64 pBuffer NV_ALIGN_BYTES(8); // [OUT] buffer returning data
NvV32 status; // [OUT] status of call
} NV_GSP_TEST_GET_MSG_BLOCK_PARAMETERS;
/**
* @brief GspTestSendRpcMessageResponse parameters
*
* This API is used to by the user-mode GSP firmware RM to send an RPC message
* response to the kernel-mode GSP client RM.
*
* This API is only supported in the GSP testbed environment.
*
* bufferSize
* Size (in bytes) of buffer pointed to by pBuffer.
* pBuffer
* Address of user-buffer from which RPC response data will be copied.
* status
* Returns status of call.
**/
typedef struct
{
NvU32 bufferSize; // [IN] size of response data buffer
NvP64 pBuffer NV_ALIGN_BYTES(8); // [IN] response data buffer
NvV32 status; // [OUT] status of call
} NV_GSP_TEST_SEND_MSG_RESPONSE_PARAMETERS;
/**
* @brief GspTestSendEventNotification parameters
*
* This API is used by the user-mode GSP firmware RM to send an event
* notification to the kernel-mode GSP client RM.
*
* This API is only supported in the GSP testbed environment.
*
* hParentClient
* Specifies handle of client that owns object associated with event.
* hSrcResource
* Specifies handle of object associated with event.
* hClass
* Specifies class number (type) of event.
* notifyIndex
* Specifies notifier index associated with event.
* status
* Returns status of call.
**/
typedef struct
{
NvHandle hParentClient; // [IN] handle of client
NvHandle hSrcResource; // [IN] handle of object
NvU32 hClass; // [IN] class number of event
NvU32 notifyIndex; // [IN] notifier index
NvV32 status; // [OUT] status of call
} NV_GSP_TEST_SEND_EVENT_NOTIFICATION_PARAMETERS;
#ifdef __cplusplus
};
#endif
#endif /* NVOS_INCLUDED */
07070100000026000081A4000000000000000000000001663926A700001306000000000000000000000000000000000000003500000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvstatus.h/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_NVSTATUS_H
#define SDK_NVSTATUS_H
/* XAPIGEN - this file is not suitable for (nor needed by) xapigen. */
/* Rather than #ifdef out every such include in every sdk */
/* file, punt here. */
#if !defined(XAPIGEN) /* rest of file */
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
typedef NvU32 NV_STATUS;
#define NV_STATUS_CODE( name, code, string ) name = (code),
enum
{
#include "nvstatuscodes.h"
};
#undef NV_STATUS_CODE
/*!
* @def NV_STATUS_LEVEL_OK
* @see NV_STATUS_LEVEL
* @brief Success: No error or special condition
*/
#define NV_STATUS_LEVEL_OK 0
/*!
* @def NV_STATUS_LEVEL_WARN
* @see NV_STATUS_LEVEL
* @brief Success, but there is an special condition
*
* @details In general, NV_STATUS_LEVEL_WARN status codes are handled the
* same as NV_STATUS_LEVEL_OK, but are usefil to indicate that
* there is a condition that may be specially handled.
*
* Therefore, in most cases, client function should test for
* status <= NV_STATUS_LEVEL_WARN or status > NV_STATUS_LEVEL_WARN
* to determine success v. failure of a call.
*/
#define NV_STATUS_LEVEL_WARN 1
/*!
* @def NV_STATUS_LEVEL_ERR
* @see NV_STATUS_LEVEL
* @brief Unrecoverable error condition
*/
#define NV_STATUS_LEVEL_ERR 3
/*!
* @def NV_STATUS_LEVEL
* @see NV_STATUS_LEVEL_OK
* @see NV_STATUS_LEVEL_WARN
* @see NV_STATUS_LEVEL_ERR
* @brief Level of the status code
*
* @warning IMPORTANT: When comparing NV_STATUS_LEVEL(_S) against one of
* these constants, it is important to use '<=' or '>' (rather
* than '<' or '>=').
*
* For example. do:
* if (NV_STATUS_LEVEL(status) <= NV_STATUS_LEVEL_WARN)
* rather than:
* if (NV_STATUS_LEVEL(status) < NV_STATUS_LEVEL_ERR)
*
* By being consistent in this manner, it is easier to systematically
* add additional level constants. New levels are likely to lower
* (rather than raise) the severity of _ERR codes. For example,
* if we were to add NV_STATUS_LEVEL_RETRY to indicate hardware
* failures that may be recoverable (e.g. RM_ERR_TIMEOUT_RETRY
* or RM_ERR_BUSY_RETRY), it would be less severe than
* NV_STATUS_LEVEL_ERR the level to which these status codes now
* belong. Using '<=' and '>' ensures your code is not broken in
* cases like this.
*/
#define NV_STATUS_LEVEL(_S) \
((_S) == NV_OK? NV_STATUS_LEVEL_OK: \
((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? NV_STATUS_LEVEL_WARN: \
NV_STATUS_LEVEL_ERR))
/*!
* @def NV_STATUS_LEVEL
* @see NV_STATUS_LEVEL_OK
* @see NV_STATUS_LEVEL_WARN
* @see NV_STATUS_LEVEL_ERR
* @brief Character representing status code level
*/
#define NV_STATUS_LEVEL_CHAR(_S) \
((_S) == NV_OK? '0': \
((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? 'W': \
'E'))
// Function definitions
const char *nvstatusToString(NV_STATUS nvStatusIn);
#ifdef __cplusplus
}
#endif
#endif // XAPIGEN
#endif /* SDK_NVSTATUS_H */
07070100000027000081A4000000000000000000000001663926A7000038CA000000000000000000000000000000000000003A00000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvstatuscodes.h/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef SDK_NVSTATUSCODES_H
#define SDK_NVSTATUSCODES_H
/* XAPIGEN - this file is not suitable for (nor needed by) xapigen. */
/* Rather than #ifdef out every such include in every sdk */
/* file, punt here. */
#if !defined(XAPIGEN) /* rest of file */
NV_STATUS_CODE(NV_OK, 0x00000000, "Success")
NV_STATUS_CODE(NV_ERR_GENERIC, 0x0000FFFF, "Failure: Generic Error")
NV_STATUS_CODE(NV_ERR_BROKEN_FB, 0x00000001, "Frame-Buffer broken")
NV_STATUS_CODE(NV_ERR_BUFFER_TOO_SMALL, 0x00000002, "Buffer passed in is too small")
NV_STATUS_CODE(NV_ERR_BUSY_RETRY, 0x00000003, "System is busy, retry later")
NV_STATUS_CODE(NV_ERR_CALLBACK_NOT_SCHEDULED, 0x00000004, "The requested callback API not scheduled")
NV_STATUS_CODE(NV_ERR_CARD_NOT_PRESENT, 0x00000005, "Card not detected")
NV_STATUS_CODE(NV_ERR_CYCLE_DETECTED, 0x00000006, "Call cycle detected")
NV_STATUS_CODE(NV_ERR_DMA_IN_USE, 0x00000007, "Requested DMA is in use")
NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_LOCKED, 0x00000008, "Requested DMA memory is not locked")
NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_UNLOCKED, 0x00000009, "Requested DMA memory is not unlocked")
NV_STATUS_CODE(NV_ERR_DUAL_LINK_INUSE, 0x0000000A, "Dual-Link is in use")
NV_STATUS_CODE(NV_ERR_ECC_ERROR, 0x0000000B, "Generic ECC error")
NV_STATUS_CODE(NV_ERR_FIFO_BAD_ACCESS, 0x0000000C, "FIFO: Invalid access")
NV_STATUS_CODE(NV_ERR_FREQ_NOT_SUPPORTED, 0x0000000D, "Requested frequency is not supported")
NV_STATUS_CODE(NV_ERR_GPU_DMA_NOT_INITIALIZED, 0x0000000E, "Requested DMA not initialized")
NV_STATUS_CODE(NV_ERR_GPU_IS_LOST, 0x0000000F, "GPU lost from the bus")
NV_STATUS_CODE(NV_ERR_GPU_IN_FULLCHIP_RESET, 0x00000010, "GPU currently in full-chip reset")
NV_STATUS_CODE(NV_ERR_GPU_NOT_FULL_POWER, 0x00000011, "GPU not in full power")
NV_STATUS_CODE(NV_ERR_GPU_UUID_NOT_FOUND, 0x00000012, "GPU UUID not found")
NV_STATUS_CODE(NV_ERR_HOT_SWITCH, 0x00000013, "System in hot switch")
NV_STATUS_CODE(NV_ERR_I2C_ERROR, 0x00000014, "I2C Error")
NV_STATUS_CODE(NV_ERR_I2C_SPEED_TOO_HIGH, 0x00000015, "I2C Error: Speed too high")
NV_STATUS_CODE(NV_ERR_ILLEGAL_ACTION, 0x00000016, "Current action is not allowed")
NV_STATUS_CODE(NV_ERR_IN_USE, 0x00000017, "Generic busy error")
NV_STATUS_CODE(NV_ERR_INFLATE_COMPRESSED_DATA_FAILED, 0x00000018, "Failed to inflate compressed data")
NV_STATUS_CODE(NV_ERR_INSERT_DUPLICATE_NAME, 0x00000019, "Found a duplicate entry in the requested btree")
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_RESOURCES, 0x0000001A, "Ran out of a critical resource, other than memory")
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_PERMISSIONS, 0x0000001B, "The requester does not have sufficient permissions")
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_POWER, 0x0000001C, "Generic Error: Low power")
NV_STATUS_CODE(NV_ERR_INVALID_ACCESS_TYPE, 0x0000001D, "This type of access is not allowed")
NV_STATUS_CODE(NV_ERR_INVALID_ADDRESS, 0x0000001E, "Address not valid")
NV_STATUS_CODE(NV_ERR_INVALID_ARGUMENT, 0x0000001F, "Invalid argument to call")
NV_STATUS_CODE(NV_ERR_INVALID_BASE, 0x00000020, "Invalid base")
NV_STATUS_CODE(NV_ERR_INVALID_CHANNEL, 0x00000021, "Given channel-id not valid")
NV_STATUS_CODE(NV_ERR_INVALID_CLASS, 0x00000022, "Given class-id not valid")
NV_STATUS_CODE(NV_ERR_INVALID_CLIENT, 0x00000023, "Given client not valid")
NV_STATUS_CODE(NV_ERR_INVALID_COMMAND, 0x00000024, "Command passed is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_DATA, 0x00000025, "Invalid data passed")
NV_STATUS_CODE(NV_ERR_INVALID_DEVICE, 0x00000026, "Current device is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_DMA_SPECIFIER, 0x00000027, "The requested DMA specifier is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_EVENT, 0x00000028, "Invalid event occurred")
NV_STATUS_CODE(NV_ERR_INVALID_FLAGS, 0x00000029, "Invalid flags passed")
NV_STATUS_CODE(NV_ERR_INVALID_FUNCTION, 0x0000002A, "Called function is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_HEAP, 0x0000002B, "Heap corrupted")
NV_STATUS_CODE(NV_ERR_INVALID_INDEX, 0x0000002C, "Index invalid")
NV_STATUS_CODE(NV_ERR_INVALID_IRQ_LEVEL, 0x0000002D, "Requested IRQ level is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_LIMIT, 0x0000002E, "Generic Error: Invalid limit")
NV_STATUS_CODE(NV_ERR_INVALID_LOCK_STATE, 0x0000002F, "Requested lock state not valid")
NV_STATUS_CODE(NV_ERR_INVALID_METHOD, 0x00000030, "Requested method not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT, 0x00000031, "Object not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_BUFFER, 0x00000032, "Object buffer passed is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_HANDLE, 0x00000033, "Object handle is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_NEW, 0x00000034, "New object is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_OLD, 0x00000035, "Old object is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_PARENT, 0x00000036, "Object parent is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OFFSET, 0x00000037, "The offset passed is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OPERATION, 0x00000038, "Requested operation is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_OWNER, 0x00000039, "Owner not valid")
NV_STATUS_CODE(NV_ERR_INVALID_PARAM_STRUCT, 0x0000003A, "Invalid structure parameter")
NV_STATUS_CODE(NV_ERR_INVALID_PARAMETER, 0x0000003B, "At least one of the parameters passed is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_PATH, 0x0000003C, "The requested path is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_POINTER, 0x0000003D, "Pointer not valid")
NV_STATUS_CODE(NV_ERR_INVALID_REGISTRY_KEY, 0x0000003E, "Found an invalid registry key")
NV_STATUS_CODE(NV_ERR_INVALID_REQUEST, 0x0000003F, "Generic Error: Invalid request")
NV_STATUS_CODE(NV_ERR_INVALID_STATE, 0x00000040, "Generic Error: Invalid state")
NV_STATUS_CODE(NV_ERR_INVALID_STRING_LENGTH, 0x00000041, "The string length is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_READ, 0x00000042, "The requested read operation is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_WRITE, 0x00000043, "The requested write operation is not valid")
NV_STATUS_CODE(NV_ERR_INVALID_XLATE, 0x00000044, "The requested translate operation is not valid")
NV_STATUS_CODE(NV_ERR_IRQ_NOT_FIRING, 0x00000045, "Requested IRQ is not firing")
NV_STATUS_CODE(NV_ERR_IRQ_EDGE_TRIGGERED, 0x00000046, "IRQ is edge triggered")
NV_STATUS_CODE(NV_ERR_MEMORY_TRAINING_FAILED, 0x00000047, "Failed memory training sequence")
NV_STATUS_CODE(NV_ERR_MISMATCHED_SLAVE, 0x00000048, "Slave mismatch")
NV_STATUS_CODE(NV_ERR_MISMATCHED_TARGET, 0x00000049, "Target mismatch")
NV_STATUS_CODE(NV_ERR_MISSING_TABLE_ENTRY, 0x0000004A, "Requested entry missing not found in the table")
NV_STATUS_CODE(NV_ERR_MODULE_LOAD_FAILED, 0x0000004B, "Failed to load the requested module")
NV_STATUS_CODE(NV_ERR_MORE_DATA_AVAILABLE, 0x0000004C, "There is more data available")
NV_STATUS_CODE(NV_ERR_MORE_PROCESSING_REQUIRED, 0x0000004D, "More processing required for the given call")
NV_STATUS_CODE(NV_ERR_MULTIPLE_MEMORY_TYPES, 0x0000004E, "Multiple memory types found")
NV_STATUS_CODE(NV_ERR_NO_FREE_FIFOS, 0x0000004F, "No more free FIFOs found")
NV_STATUS_CODE(NV_ERR_NO_INTR_PENDING, 0x00000050, "No interrupt pending")
NV_STATUS_CODE(NV_ERR_NO_MEMORY, 0x00000051, "Out of memory")
NV_STATUS_CODE(NV_ERR_NO_SUCH_DOMAIN, 0x00000052, "Requested domain does not exist")
NV_STATUS_CODE(NV_ERR_NO_VALID_PATH, 0x00000053, "Caller did not specify a valid path")
NV_STATUS_CODE(NV_ERR_NOT_COMPATIBLE, 0x00000054, "Generic Error: Incompatible types")
NV_STATUS_CODE(NV_ERR_NOT_READY, 0x00000055, "Generic Error: Not ready")
NV_STATUS_CODE(NV_ERR_NOT_SUPPORTED, 0x00000056, "Call not supported")
NV_STATUS_CODE(NV_ERR_OBJECT_NOT_FOUND, 0x00000057, "Requested object not found")
NV_STATUS_CODE(NV_ERR_OBJECT_TYPE_MISMATCH, 0x00000058, "Specified objects do not match")
NV_STATUS_CODE(NV_ERR_OPERATING_SYSTEM, 0x00000059, "Generic operating system error")
NV_STATUS_CODE(NV_ERR_OTHER_DEVICE_FOUND, 0x0000005A, "Found other device instead of the requested one")
NV_STATUS_CODE(NV_ERR_OUT_OF_RANGE, 0x0000005B, "The specified value is out of bounds")
NV_STATUS_CODE(NV_ERR_OVERLAPPING_UVM_COMMIT, 0x0000005C, "Overlapping unified virtual memory commit")
NV_STATUS_CODE(NV_ERR_PAGE_TABLE_NOT_AVAIL, 0x0000005D, "Requested page table not available")
NV_STATUS_CODE(NV_ERR_PID_NOT_FOUND, 0x0000005E, "Process-Id not found")
NV_STATUS_CODE(NV_ERR_PROTECTION_FAULT, 0x0000005F, "Protection fault")
NV_STATUS_CODE(NV_ERR_RC_ERROR, 0x00000060, "Generic RC error")
NV_STATUS_CODE(NV_ERR_REJECTED_VBIOS, 0x00000061, "Given Video BIOS rejected/invalid")
NV_STATUS_CODE(NV_ERR_RESET_REQUIRED, 0x00000062, "Reset required")
NV_STATUS_CODE(NV_ERR_STATE_IN_USE, 0x00000063, "State in use")
NV_STATUS_CODE(NV_ERR_SIGNAL_PENDING, 0x00000064, "Signal pending")
NV_STATUS_CODE(NV_ERR_TIMEOUT, 0x00000065, "Call timed out")
NV_STATUS_CODE(NV_ERR_TIMEOUT_RETRY, 0x00000066, "Call timed out, please retry later")
NV_STATUS_CODE(NV_ERR_TOO_MANY_PRIMARIES, 0x00000067, "Too many primaries")
NV_STATUS_CODE(NV_ERR_UVM_ADDRESS_IN_USE, 0x00000068, "Unified virtual memory requested address already in use")
NV_STATUS_CODE(NV_ERR_MAX_SESSION_LIMIT_REACHED, 0x00000069, "Maximum number of sessions reached")
NV_STATUS_CODE(NV_ERR_LIB_RM_VERSION_MISMATCH, 0x0000006A, "Library version doesn't match driver version") //Contained within the RMAPI library
NV_STATUS_CODE(NV_ERR_PRIV_SEC_VIOLATION, 0x0000006B, "Priv security violation")
NV_STATUS_CODE(NV_ERR_GPU_IN_DEBUG_MODE, 0x0000006C, "GPU currently in debug mode")
NV_STATUS_CODE(NV_ERR_FEATURE_NOT_ENABLED, 0x0000006D, "Requested Feature functionality is not enabled")
NV_STATUS_CODE(NV_ERR_RESOURCE_LOST, 0x0000006E, "Requested resource has been destroyed")
NV_STATUS_CODE(NV_ERR_PMU_NOT_READY, 0x0000006F, "PMU is not ready or has not yet been initialized")
NV_STATUS_CODE(NV_ERR_FLCN_ERROR, 0x00000070, "Generic falcon assert or halt")
NV_STATUS_CODE(NV_ERR_FATAL_ERROR, 0x00000071, "Fatal/unrecoverable error")
NV_STATUS_CODE(NV_ERR_MEMORY_ERROR, 0x00000072, "Generic memory error")
NV_STATUS_CODE(NV_ERR_INVALID_LICENSE, 0x00000073, "License provided is rejected or invalid")
NV_STATUS_CODE(NV_ERR_NVLINK_INIT_ERROR, 0x00000074, "Nvlink Init Error")
NV_STATUS_CODE(NV_ERR_NVLINK_MINION_ERROR, 0x00000075, "Nvlink Minion Error")
NV_STATUS_CODE(NV_ERR_NVLINK_CLOCK_ERROR, 0x00000076, "Nvlink Clock Error")
NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Training Error")
NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error")
NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")
NV_STATUS_CODE(NV_WARN_INCORRECT_PERFMON_DATA, 0x00010002, "WARNING Incorrect performance monitor data")
NV_STATUS_CODE(NV_WARN_MISMATCHED_SLAVE, 0x00010003, "WARNING Slave mismatch")
NV_STATUS_CODE(NV_WARN_MISMATCHED_TARGET, 0x00010004, "WARNING Target mismatch")
NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More processing required for the call")
NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do")
NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found")
NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range")
#endif // XAPIGEN
#endif /* SDK_NVSTATUSCODES_H */
07070100000028000081A4000000000000000000000001663926A7000063A4000000000000000000000000000000000000003400000000nvidia-vaapi-driver-0.0.12/nvidia-include/nvtypes.h/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVTYPES_INCLUDED
#define NVTYPES_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "cpuopsys.h"
#ifndef NVTYPES_USE_STDINT
#define NVTYPES_USE_STDINT 0
#endif
#if NVTYPES_USE_STDINT
#ifdef __cplusplus
#include <cstdint>
#include <cinttypes>
#else
#include <stdint.h>
#include <inttypes.h>
#endif // __cplusplus
#endif // NVTYPES_USE_STDINT
#ifndef __cplusplus
// Header includes to make sure wchar_t is defined for C-file compilation
// (C++ is not affected as it is a fundamental type there)
// _MSC_VER is a hack to avoid failures for old setup of UEFI builds which are
// currently set to msvc100 but do not properly set the include paths
#endif // __cplusplus
#if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__)
// ensure or force 8-bytes alignment of NV 64-bit types
#define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8)))
#else
// nothing needed
#define OPTIONAL_ALIGN8_ATTR
#endif // MAKE_NV64TYPES_8BYTES_ALIGNED && i386
/***************************************************************************\
|* Typedefs *|
\***************************************************************************/
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
//Typedefs for MISRA COMPLIANCE
typedef unsigned long long UInt64;
typedef signed long long Int64;
typedef unsigned int UInt32;
typedef signed int Int32;
typedef unsigned short UInt16;
typedef signed short Int16;
typedef unsigned char UInt8 ;
typedef signed char Int8 ;
typedef void Void;
typedef float float32_t;
typedef double float64_t;
#endif
// Floating point types
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
typedef float32_t NvF32; /* IEEE Single Precision (S1E8M23) */
typedef float64_t NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */
#else
typedef float NvF32; /* IEEE Single Precision (S1E8M23) */
typedef double NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */
#endif
// 8-bit: 'char' is the only 8-bit in the C89 standard and after.
#if NVTYPES_USE_STDINT
typedef uint8_t NvV8; /* "void": enumerated or multiple fields */
typedef uint8_t NvU8; /* 0 to 255 */
typedef int8_t NvS8; /* -128 to 127 */
#else
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
typedef UInt8 NvV8; /* "void": enumerated or multiple fields */
typedef UInt8 NvU8; /* 0 to 255 */
typedef Int8 NvS8; /* -128 to 127 */
#else
typedef unsigned char NvV8; /* "void": enumerated or multiple fields */
typedef unsigned char NvU8; /* 0 to 255 */
typedef signed char NvS8; /* -128 to 127 */
#endif
#endif // NVTYPES_USE_STDINT
#if NVTYPES_USE_STDINT
typedef uint16_t NvV16; /* "void": enumerated or multiple fields */
typedef uint16_t NvU16; /* 0 to 65535 */
typedef int16_t NvS16; /* -32768 to 32767 */
#else
// 16-bit: If the compiler tells us what we can use, then use it.
#ifdef __INT16_TYPE__
typedef unsigned __INT16_TYPE__ NvV16; /* "void": enumerated or multiple fields */
typedef unsigned __INT16_TYPE__ NvU16; /* 0 to 65535 */
typedef signed __INT16_TYPE__ NvS16; /* -32768 to 32767 */
// The minimal standard for C89 and after
#else // __INT16_TYPE__
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
typedef UInt16 NvV16; /* "void": enumerated or multiple fields */
typedef UInt16 NvU16; /* 0 to 65535 */
typedef Int16 NvS16; /* -32768 to 32767 */
#else
typedef unsigned short NvV16; /* "void": enumerated or multiple fields */
typedef unsigned short NvU16; /* 0 to 65535 */
typedef signed short NvS16; /* -32768 to 32767 */
#endif
#endif // __INT16_TYPE__
#endif // NVTYPES_USE_STDINT
// wchar type (fixed size types consistent across Linux/Windows boundaries)
#if defined(NV_HAS_WCHAR_T_TYPEDEF)
typedef wchar_t NvWchar;
#else
typedef NvV16 NvWchar;
#endif
// Macro to build an NvU32 from four bytes, listed from msb to lsb
#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
#if NVTYPES_USE_STDINT
typedef uint32_t NvV32; /* "void": enumerated or multiple fields */
typedef uint32_t NvU32; /* 0 to 4294967295 */
typedef int32_t NvS32; /* -2147483648 to 2147483647 */
#else
// 32-bit: If the compiler tells us what we can use, then use it.
#ifdef __INT32_TYPE__
typedef unsigned __INT32_TYPE__ NvV32; /* "void": enumerated or multiple fields */
typedef unsigned __INT32_TYPE__ NvU32; /* 0 to 4294967295 */
typedef signed __INT32_TYPE__ NvS32; /* -2147483648 to 2147483647 */
// Older compilers
#else // __INT32_TYPE__
// For historical reasons, NvU32/NvV32 are defined to different base intrinsic
// types than NvS32 on some platforms.
// Mainly for 64-bit linux, where long is 64 bits and win9x, where int is 16 bit.
#if (defined(NV_UNIX) || defined(vxworks) || defined(NV_WINDOWS_CE) || \
defined(__arm) || defined(__IAR_SYSTEMS_ICC__) || defined(NV_QNX) || \
defined(NV_INTEGRITY) || defined(NV_MODS) || \
defined(__GNUC__) || defined(__clang__) || defined(NV_MACINTOSH_64)) && \
(!defined(NV_MACINTOSH) || defined(NV_MACINTOSH_64))
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
typedef UInt32 NvV32; /* "void": enumerated or multiple fields */
typedef UInt32 NvU32; /* 0 to 4294967295 */
#else
typedef unsigned int NvV32; /* "void": enumerated or multiple fields */
typedef unsigned int NvU32; /* 0 to 4294967295 */
#endif
// The minimal standard for C89 and after
#else // (defined(NV_UNIX) || defined(vxworks) || ...
typedef unsigned long NvV32; /* "void": enumerated or multiple fields */
typedef unsigned long NvU32; /* 0 to 4294967295 */
#endif // (defined(NV_UNIX) || defined(vxworks) || ...
// Mac OS 32-bit still needs this
#if defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64)
typedef signed long NvS32; /* -2147483648 to 2147483647 */
#else
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
typedef Int32 NvS32; /* -2147483648 to 2147483647 */
#else
typedef signed int NvS32; /* -2147483648 to 2147483647 */
#endif
#endif // defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64)
#endif // __INT32_TYPE__
#endif // NVTYPES_USE_STDINT
#if NVTYPES_USE_STDINT
typedef uint64_t NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
typedef int64_t NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
#define NvU64_fmtX PRIX64
#define NvU64_fmtx PRIx64
#define NvU64_fmtu PRIu64
#define NvU64_fmto PRIo64
#define NvS64_fmtd PRId64
#define NvS64_fmti PRIi64
#else
// 64-bit types for compilers that support them, plus some obsolete variants
#if defined(__GNUC__) || defined(__clang__) || defined(__arm) || \
defined(__IAR_SYSTEMS_ICC__) || defined(__ghs__) || defined(_WIN64) || \
defined(__SUNPRO_C) || defined(__SUNPRO_CC) || defined (__xlC__)
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
typedef UInt64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
typedef Int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
#else
typedef unsigned long long NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
typedef long long NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
#endif
#define NvU64_fmtX "llX"
#define NvU64_fmtx "llx"
#define NvU64_fmtu "llu"
#define NvU64_fmto "llo"
#define NvS64_fmtd "lld"
#define NvS64_fmti "lli"
// Microsoft since 2003 -- https://msdn.microsoft.com/en-us/library/29dh1w7z.aspx
#else
typedef unsigned __int64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
typedef __int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
#define NvU64_fmtX "I64X"
#define NvU64_fmtx "I64x"
#define NvU64_fmtu "I64u"
#define NvU64_fmto "I64o"
#define NvS64_fmtd "I64d"
#define NvS64_fmti "I64i"
#endif
#endif // NVTYPES_USE_STDINT
#ifdef NV_TYPESAFE_HANDLES
/*
* Can't use opaque pointer as clients might be compiled with mismatched
* pointer sizes. TYPESAFE check will eventually be removed once all clients
* have transistioned safely to NvHandle.
* The plan is to then eventually scale up the handle to be 64-bits.
*/
typedef struct
{
NvU32 val;
} NvHandle;
#else
/*
* For compatibility with modules that haven't moved typesafe handles.
*/
typedef NvU32 NvHandle;
#endif // NV_TYPESAFE_HANDLES
/* Boolean type */
typedef NvU8 NvBool;
#define NV_TRUE ((NvBool)(0 == 0))
#define NV_FALSE ((NvBool)(0 != 0))
/* Tristate type: NV_TRISTATE_FALSE, NV_TRISTATE_TRUE, NV_TRISTATE_INDETERMINATE */
typedef NvU8 NvTristate;
#define NV_TRISTATE_FALSE ((NvTristate) 0)
#define NV_TRISTATE_TRUE ((NvTristate) 1)
#define NV_TRISTATE_INDETERMINATE ((NvTristate) 2)
/* Macros to extract the low and high parts of a 64-bit unsigned integer */
/* Also designed to work if someone happens to pass in a 32-bit integer */
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffffU))
#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffffU))
#else
#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffff))
#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffff))
#endif
#define NvU40_HI32(n) ((NvU32)((((NvU64)(n)) >> 8) & 0xffffffffU))
#define NvU40_HI24of32(n) ((NvU32)( (NvU64)(n) & 0xffffff00U))
/* Macros to get the MSB and LSB of a 32 bit unsigned number */
#define NvU32_HI16(n) ((NvU16)((((NvU32)(n)) >> 16) & 0xffffU))
#define NvU32_LO16(n) ((NvU16)(( (NvU32)(n)) & 0xffffU))
/***************************************************************************\
|* *|
|* 64 bit type definitions for use in interface structures. *|
|* *|
\***************************************************************************/
#if defined(NV_64_BITS)
typedef void* NvP64; /* 64 bit void pointer */
typedef NvU64 NvUPtr; /* pointer sized unsigned int */
typedef NvS64 NvSPtr; /* pointer sized signed int */
typedef NvU64 NvLength; /* length to agree with sizeof */
#define NvP64_VALUE(n) (n)
#define NvP64_fmt "%p"
#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(v))
#define NvP64_PLUS_OFFSET(p,o) (NvP64)((NvU64)(p) + (NvU64)(o))
#define NvUPtr_fmtX NvU64_fmtX
#define NvUPtr_fmtx NvU64_fmtx
#define NvUPtr_fmtu NvU64_fmtu
#define NvUPtr_fmto NvU64_fmto
#define NvSPtr_fmtd NvS64_fmtd
#define NvSPtr_fmti NvS64_fmti
#else
typedef NvU64 NvP64; /* 64 bit void pointer */
typedef NvU32 NvUPtr; /* pointer sized unsigned int */
typedef NvS32 NvSPtr; /* pointer sized signed int */
typedef NvU32 NvLength; /* length to agree with sizeof */
#define NvP64_VALUE(n) ((void *)(NvUPtr)(n))
#define NvP64_fmt "0x%llx"
#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(NvUPtr)(v))
#define NvP64_PLUS_OFFSET(p,o) ((p) + (NvU64)(o))
#define NvUPtr_fmtX "X"
#define NvUPtr_fmtx "x"
#define NvUPtr_fmtu "u"
#define NvUPtr_fmto "o"
#define NvSPtr_fmtd "d"
#define NvSPtr_fmti "i"
#endif
#define NvP64_NULL (NvP64)0
/*!
* Helper macro to pack an @ref NvU64_ALIGN32 structure from a @ref NvU64.
*
* @param[out] pDst Pointer to NvU64_ALIGN32 structure to pack
* @param[in] pSrc Pointer to NvU64 with which to pack
*/
#define NvU64_ALIGN32_PACK(pDst, pSrc) \
do { \
(pDst)->lo = NvU64_LO32(*(pSrc)); \
(pDst)->hi = NvU64_HI32(*(pSrc)); \
} while (NV_FALSE)
/*!
* Helper macro to unpack a @ref NvU64_ALIGN32 structure into a @ref NvU64.
*
* @param[out] pDst Pointer to NvU64 in which to unpack
* @param[in] pSrc Pointer to NvU64_ALIGN32 structure from which to unpack
*/
#define NvU64_ALIGN32_UNPACK(pDst, pSrc) \
do { \
(*(pDst)) = NvU64_ALIGN32_VAL(pSrc); \
} while (NV_FALSE)
/*!
* Helper macro to unpack a @ref NvU64_ALIGN32 structure as a @ref NvU64.
*
* @param[in] pSrc Pointer to NvU64_ALIGN32 structure to unpack
*/
#define NvU64_ALIGN32_VAL(pSrc) \
((NvU64) ((NvU64)((pSrc)->lo) | (((NvU64)(pSrc)->hi) << 32U)))
/*!
* Helper macro to check whether the 32 bit aligned 64 bit number is zero.
*
* @param[in] _pU64 Pointer to NvU64_ALIGN32 structure.
*
* @return
* NV_TRUE _pU64 is zero.
* NV_FALSE otherwise.
*/
#define NvU64_ALIGN32_IS_ZERO(_pU64) \
(((_pU64)->lo == 0U) && ((_pU64)->hi == 0U))
/*!
* Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor.
*
* @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure.
* @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure.
* @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure.
*/
#define NvU64_ALIGN32_ADD(pDst, pSrc1, pSrc2) \
do { \
NvU64 __dst, __src1, __scr2; \
\
NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \
NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \
__dst = __src1 + __scr2; \
NvU64_ALIGN32_PACK((pDst), &__dst); \
} while (NV_FALSE)
/*!
* Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor.
*
* @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure.
* @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure.
* @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure.
*/
#define NvU64_ALIGN32_SUB(pDst, pSrc1, pSrc2) \
do { \
NvU64 __dst, __src1, __scr2; \
\
NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \
NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \
__dst = __src1 - __scr2; \
NvU64_ALIGN32_PACK((pDst), &__dst); \
} while (NV_FALSE)
/*!
* Structure for representing 32 bit aligned NvU64 (64-bit unsigned integer)
* structures. This structure must be used because the 32 bit processor and
* 64 bit processor compilers will pack/align NvU64 differently.
*
* One use case is RM being 64 bit proc whereas PMU being 32 bit proc, this
* alignment difference will result in corrupted transactions between the RM
* and PMU.
*
* See the @ref NvU64_ALIGN32_PACK and @ref NvU64_ALIGN32_UNPACK macros for
* packing and unpacking these structures.
*
* @note The intention of this structure is to provide a datatype which will
* packed/aligned consistently and efficiently across all platforms.
* We don't want to use "NV_DECLARE_ALIGNED(NvU64, 8)" because that
* leads to memory waste on our 32-bit uprocessors (e.g. FALCONs) where
* DMEM efficiency is vital.
*/
typedef struct
{
/*!
* Low 32 bits.
*/
NvU32 lo;
/*!
* High 32 bits.
*/
NvU32 hi;
} NvU64_ALIGN32;
/* Useful macro to hide required double cast */
#define NV_PTR_TO_NvP64(n) (NvP64)(NvUPtr)(n)
#define NV_SIGN_EXT_PTR_TO_NvP64(p) ((NvP64)(NvS64)(NvSPtr)(p))
#define KERNEL_POINTER_TO_NvP64(p) ((NvP64)(uintptr_t)(p))
/***************************************************************************\
|* *|
|* Limits for common types. *|
|* *|
\***************************************************************************/
/* Explanation of the current form of these limits:
*
* - Decimal is used, as hex values are by default positive.
* - Casts are not used, as usage in the preprocessor itself (#if) ends poorly.
* - The subtraction of 1 for some MIN values is used to get around the fact
* that the C syntax actually treats -x as NEGATE(x) instead of a distinct
* number. Since 214748648 isn't a valid positive 32-bit signed value, we
* take the largest valid positive signed number, negate it, and subtract 1.
*/
#define NV_S8_MIN (-128)
#define NV_S8_MAX (+127)
#define NV_U8_MIN (0U)
#define NV_U8_MAX (+255U)
#define NV_S16_MIN (-32768)
#define NV_S16_MAX (+32767)
#define NV_U16_MIN (0U)
#define NV_U16_MAX (+65535U)
#define NV_S32_MIN (-2147483647 - 1)
#define NV_S32_MAX (+2147483647)
#define NV_U32_MIN (0U)
#define NV_U32_MAX (+4294967295U)
#define NV_S64_MIN (-9223372036854775807LL - 1LL)
#define NV_S64_MAX (+9223372036854775807LL)
#define NV_U64_MIN (0ULL)
#define NV_U64_MAX (+18446744073709551615ULL)
/* Aligns fields in structs so they match up between 32 and 64 bit builds */
#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX)
#define NV_ALIGN_BYTES(size) __attribute__ ((aligned (size)))
#elif defined(__arm)
#define NV_ALIGN_BYTES(size) __align(ALIGN)
#else
// XXX This is dangerously nonportable! We really shouldn't provide a default
// version of this that doesn't do anything.
#define NV_ALIGN_BYTES(size)
#endif
// NV_DECLARE_ALIGNED() can be used on all platforms.
// This macro form accounts for the fact that __declspec on Windows is required
// before the variable type,
// and NV_ALIGN_BYTES is required after the variable name.
#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX)
#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) TYPE_VAR __attribute__ ((aligned (ALIGN)))
#elif defined(__arm)
#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __align(ALIGN) TYPE_VAR
#endif
/***************************************************************************\
|* Function Declaration Types *|
\***************************************************************************/
// stretching the meaning of "nvtypes", but this seems to least offensive
// place to re-locate these from nvos.h which cannot be included by a number
// of builds that need them
#if defined(__GNUC__)
#if (__GNUC__ > 3) || \
((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) && (__GNUC_PATCHLEVEL__ >= 1))
#define NV_NOINLINE __attribute__((__noinline__))
#endif
#elif defined(__clang__)
#if __has_attribute(noinline)
#define NV_NOINLINE __attribute__((__noinline__))
#endif
#elif defined(__arm) && (__ARMCC_VERSION >= 300000)
#define NV_NOINLINE __attribute__((__noinline__))
#elif (defined(__SUNPRO_C) && (__SUNPRO_C >= 0x590)) ||\
(defined(__SUNPRO_CC) && (__SUNPRO_CC >= 0x590))
#define NV_NOINLINE __attribute__((__noinline__))
#elif defined (__INTEL_COMPILER)
#define NV_NOINLINE __attribute__((__noinline__))
#endif
#if !defined(NV_NOINLINE)
#define NV_NOINLINE
#endif
/* GreenHills compiler defines __GNUC__, but doesn't support
* __inline__ keyword. */
#if defined(__ghs__)
#define NV_INLINE inline
#elif defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
#define NV_INLINE __inline__
#elif defined (macintosh) || defined(__SUNPRO_C) || defined(__SUNPRO_CC)
#define NV_INLINE inline
#elif defined(__arm)
#define NV_INLINE __inline
#else
#define NV_INLINE
#endif
/* Don't force inline on DEBUG builds -- it's annoying for debuggers. */
#if !defined(DEBUG)
/* GreenHills compiler defines __GNUC__, but doesn't support
* __attribute__ or __inline__ keyword. */
#if defined(__ghs__)
#define NV_FORCEINLINE inline
#elif defined(__GNUC__)
// GCC 3.1 and beyond support the always_inline function attribute.
#if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1))
#define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__
#else
#define NV_FORCEINLINE __inline__
#endif
#elif defined(__clang__)
#if __has_attribute(always_inline)
#define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__
#else
#define NV_FORCEINLINE __inline__
#endif
#elif defined(__arm) && (__ARMCC_VERSION >= 220000)
// RVDS 2.2 also supports forceinline, but ADS 1.2 does not
#define NV_FORCEINLINE __forceinline
#else /* defined(__GNUC__) */
#define NV_FORCEINLINE NV_INLINE
#endif
#else
#define NV_FORCEINLINE NV_INLINE
#endif
#define NV_APIENTRY
#define NV_FASTCALL
#define NV_CDECLCALL
#define NV_STDCALL
/*
* The 'warn_unused_result' function attribute prompts GCC to issue a
* warning if the result of a function tagged with this attribute
* is ignored by a caller. In combination with '-Werror', it can be
* used to enforce result checking in RM code; at this point, this
* is only done on UNIX.
*/
#if defined(__GNUC__) && defined(NV_UNIX)
#if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 4))
#define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__))
#else
#define NV_FORCERESULTCHECK
#endif
#elif defined(__clang__)
#if __has_attribute(warn_unused_result)
#define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__))
#else
#define NV_FORCERESULTCHECK
#endif
#else /* defined(__GNUC__) */
#define NV_FORCERESULTCHECK
#endif
#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
#define NV_ATTRIBUTE_UNUSED __attribute__((__unused__))
#else
#define NV_ATTRIBUTE_UNUSED
#endif
/*
* Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at
* parameter number 'f' and variadic arguments start at parameter number 'a'.
* (Note that for C++ methods, there is an implicit 'this' parameter so
* explicit parameters are numbered from 2.)
*/
#if defined(__GNUC__)
#define NV_FORMAT_PRINTF(_f, _a) __attribute__((format(printf, _f, _a)))
#else
#define NV_FORMAT_PRINTF(_f, _a)
#endif
#ifdef __cplusplus
}
#endif
#endif /* NVTYPES_INCLUDED */
07070100000029000081A4000000000000000000000001663926A700002534000000000000000000000000000000000000003600000000nvidia-vaapi-driver-0.0.12/nvidia-include/rs_access.h/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: rs_access.finn
//
#include "nvtypes.h"
#include "nvmisc.h"
/****************************************************************************/
/* Access right definitions */
/****************************************************************************/
//
// The meaning of each access right is documented in
// resman/docs/rmapi/resource_server/rm_capabilities.adoc
//
// RS_ACCESS_COUNT is the number of access rights that have been defined
// and are in use. All integers in the range [0, RS_ACCESS_COUNT) should
// represent valid access rights.
//
// When adding a new access right, don't forget to update
// 1) The descriptions in the resman/docs/rmapi/resource_server/rm_capabilities.adoc
// 2) RS_ACCESS_COUNT, defined below
// 3) The declaration of g_rsAccessMetadata in rs_access_rights.c
// 4) The list of access rights in drivers/common/chip-config/Chipcontrols.pm
// 5) Any relevant access right callbacks
//
#define RS_ACCESS_DUP_OBJECT 0U
#define RS_ACCESS_NICE 1U
#define RS_ACCESS_DEBUG 2U
#define RS_ACCESS_COUNT 3U
/****************************************************************************/
/* Access right data structures */
/****************************************************************************/
/*!
* @brief A type that can be used to represent any access right.
*/
typedef NvU16 RsAccessRight;
/*!
* @brief An internal type used to represent one limb in an access right mask.
*/
typedef NvU32 RsAccessLimb;
#define SDK_RS_ACCESS_LIMB_BITS 32
/*!
* @brief The number of limbs in the RS_ACCESS_MASK struct.
*/
#define SDK_RS_ACCESS_MAX_LIMBS 1
/*!
* @brief The maximum number of possible access rights supported by the
* current data structure definition.
*
* You probably want RS_ACCESS_COUNT instead, which is the number of actual
* access rights defined.
*/
#define SDK_RS_ACCESS_MAX_COUNT (0x20) /* finn: Evaluated from "(SDK_RS_ACCESS_LIMB_BITS * SDK_RS_ACCESS_MAX_LIMBS)" */
/**
* @brief A struct representing a set of access rights.
*
* Note that the values of bit positions larger than RS_ACCESS_COUNT is
* undefined, and should not be assumed to be 0 (see RS_ACCESS_MASK_FILL).
*/
typedef struct RS_ACCESS_MASK {
RsAccessLimb limbs[SDK_RS_ACCESS_MAX_LIMBS];
} RS_ACCESS_MASK;
/**
* @brief A struct representing auxiliary information about each access right.
*/
typedef struct RS_ACCESS_INFO {
NvU32 flags;
} RS_ACCESS_INFO;
/****************************************************************************/
/* Access right macros */
/****************************************************************************/
#define SDK_RS_ACCESS_LIMB_INDEX(index) ((index) / SDK_RS_ACCESS_LIMB_BITS)
#define SDK_RS_ACCESS_LIMB_POS(index) ((index) % SDK_RS_ACCESS_LIMB_BITS)
#define SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) \
((pAccessMask)->limbs[SDK_RS_ACCESS_LIMB_INDEX(index)])
#define SDK_RS_ACCESS_OFFSET_MASK(index) \
NVBIT_TYPE(SDK_RS_ACCESS_LIMB_POS(index), RsAccessLimb)
/*!
* @brief Checks that accessRight represents a valid access right.
*
* The valid range of access rights is [0, RS_ACCESS_COUNT).
*
* @param[in] accessRight The access right value to check
*
* @return true if accessRight is valid
* @return false otherwise
*/
#define RS_ACCESS_BOUNDS_CHECK(accessRight) \
(accessRight < RS_ACCESS_COUNT)
/*!
* @brief Test whether an access right is present in a set
*
* @param[in] pAccessMask The set of access rights to read
* @param[in] index The access right to examine
*
* @return NV_TRUE if the access right specified by index was present in the set,
* and NV_FALSE otherwise
*/
#define RS_ACCESS_MASK_TEST(pAccessMask, index) \
(RS_ACCESS_BOUNDS_CHECK(index) && \
(SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) & SDK_RS_ACCESS_OFFSET_MASK(index)) != 0)
/*!
* @brief Add an access right to a mask
*
* @param[in] pAccessMask The set of access rights to modify
* @param[in] index The access right to set
*/
#define RS_ACCESS_MASK_ADD(pAccessMask, index) \
do \
{ \
if (RS_ACCESS_BOUNDS_CHECK(index)) { \
SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) |= SDK_RS_ACCESS_OFFSET_MASK(index); \
} \
} while (NV_FALSE)
/*!
* @brief Remove an access right from a mask
*
* @param[in] pAccessMask The set of access rights to modify
* @param[in] index The access right to unset
*/
#define RS_ACCESS_MASK_REMOVE(pAccessMask, index) \
do \
{ \
if (RS_ACCESS_BOUNDS_CHECK(index)) { \
SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) &= ~SDK_RS_ACCESS_OFFSET_MASK(index); \
} \
} while (NV_FALSE)
/*!
* @brief Performs an in-place union between two access right masks
*
* @param[in,out] pMaskOut The access rights mask to be updated
* @param[in] pMaskIn The set of access rights to be added to pMaskOut
*/
#define RS_ACCESS_MASK_UNION(pMaskOut, pMaskIn) \
do \
{ \
NvLength limb; \
for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \
{ \
SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) |= SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \
} \
} while (NV_FALSE)
/*!
* @brief Performs an in-place subtract of one mask's rights from another
*
* @param[in,out] pMaskOut The access rights mask to be updated
* @param[in] pMaskIn The set of access rights to be removed from pMaskOut
*/
#define RS_ACCESS_MASK_SUBTRACT(pMaskOut, pMaskIn) \
do \
{ \
NvLength limb; \
for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \
{ \
SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) &= ~SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \
} \
} while (NV_FALSE)
/*!
* @brief Removes all rights from an access rights mask
*
* @param[in,out] pAccessMask The access rights mask to be updated
*/
#define RS_ACCESS_MASK_CLEAR(pAccessMask) \
do \
{ \
portMemSet(pAccessMask, 0, sizeof(*pAccessMask)); \
} while (NV_FALSE)
/*!
* @brief Adds all rights to an access rights mask
*
* @param[in,out] pAccessMask The access rights mask to be updated
*/
#define RS_ACCESS_MASK_FILL(pAccessMask) \
do \
{ \
portMemSet(pAccessMask, 0xff, sizeof(*pAccessMask)); \
} while (NV_FALSE)
/****************************************************************************/
/* Share definitions */
/****************************************************************************/
//
// The usage of Share Policy and the meaning of each share type is documented in
// resman/docs/rmapi/resource_server/rm_capabilities.adoc
//
#define RS_SHARE_TYPE_NONE (0U)
#define RS_SHARE_TYPE_ALL (1U)
#define RS_SHARE_TYPE_OS_SECURITY_TOKEN (2U)
#define RS_SHARE_TYPE_CLIENT (3U)
#define RS_SHARE_TYPE_PID (4U)
#define RS_SHARE_TYPE_SMC_PARTITION (5U)
#define RS_SHARE_TYPE_GPU (6U)
#define RS_SHARE_TYPE_FM_CLIENT (7U)
// Must be last. Update when a new SHARE_TYPE is added
#define RS_SHARE_TYPE_MAX (8U)
//
// Use Revoke to remove an existing policy from the list.
// Allow is based on OR logic, Require is based on AND logic.
// To share a right, at least one Allow (non-Require) must match, and all Require must pass.
// If Compose is specified, policies will be added to the list. Otherwise, they will replace the list.
//
#define RS_SHARE_ACTION_FLAG_REVOKE NVBIT(0)
#define RS_SHARE_ACTION_FLAG_REQUIRE NVBIT(1)
#define RS_SHARE_ACTION_FLAG_COMPOSE NVBIT(2)
/****************************************************************************/
/* Share flag data structures */
/****************************************************************************/
typedef struct RS_SHARE_POLICY {
NvU32 target;
RS_ACCESS_MASK accessMask;
NvU16 type; ///< RS_SHARE_TYPE_
NvU8 action; ///< RS_SHARE_ACTION_
} RS_SHARE_POLICY;
0707010000002A000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000002300000000nvidia-vaapi-driver-0.0.12/samples0707010000002B000081ED000000000000000000000001663926A700000595000000000000000000000000000000000000003100000000nvidia-vaapi-driver-0.0.12/samples/gensamples.sh#!/bin/sh
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 smptebars_h264.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v libx265 -crf 26 -preset fast smptebars_hevc_8bit.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v libx265 -crf 26 -preset fast -pix_fmt yuv420p10le smptebars_hevc_10bit.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v libx265 -crf 26 -preset fast -pix_fmt yuv420p12le smptebars_hevc_12bit.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v libx265 -crf 26 -preset fast -pix_fmt yuv422 smptebars_hevc_422_8bit.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v libx265 -crf 26 -preset fast -pix_fmt yuv422p10le smptebars_hevc_422_10bit.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v libx265 -crf 26 -preset fast -pix_fmt yuv422p12le smptebars_hevc_422_12bit.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v mpeg4 smptebars_mpeg4.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v vp9 smptebars_vp9.mp4
#this one didn't work on my ffmpeg, complained about a mismatched ABI
#ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v av1 smptebars_av1.mp4
ffmpeg -f lavfi -i smptebars=duration=10:size=640x360:rate=30 -c:v libsvtav1 smptebars_av1.mp4
#TODO need mpeg2, vc1, vp8, perhaps h264 with different levels
0707010000002C000081A4000000000000000000000001663926A700000090000000000000000000000000000000000000002E00000000nvidia-vaapi-driver-0.0.12/samples/index.html<html>
<div>
<p>VP9:</p>
<video loop width="640" height="360" src="smptebars_vp9.mp4" controls/>
</div>
</html>
0707010000002D000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000001F00000000nvidia-vaapi-driver-0.0.12/src0707010000002E000081A4000000000000000000000001663926A7000040F6000000000000000000000000000000000000002500000000nvidia-vaapi-driver-0.0.12/src/av1.c#include "vabackend.h"
#include <sys/param.h>
//TODO incomplete as no hardware to test with
static int get_relative_dist(CUVIDAV1PICPARAMS *pps, int ref_hint, int order_hint) {
if (!pps->enable_order_hint) {
return 0;
}
int diff = ref_hint - order_hint;
int m = 1 << pps->order_hint_bits_minus1;
return (diff & (m - 1)) - (diff & m);
}
static void copyAV1PicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams) {
static const int bit_depth_map[] = {0, 2, 4}; //8-bpc, 10-bpc, 12-bpc
VADecPictureParameterBufferAV1* buf = (VADecPictureParameterBufferAV1*) buffer->ptr;
CUVIDAV1PICPARAMS *pps = &picParams->CodecSpecific.av1;
picParams->PicWidthInMbs = (ctx->width + 15)/16;
picParams->FrameHeightInMbs = (ctx->height + 15)/16;
picParams->intra_pic_flag = buf->pic_info_fields.bits.frame_type == 0 || //Key
buf->pic_info_fields.bits.frame_type == 2; //Intra-Only
//TODO if it's not a key or switch frame type, it still *might* be a ref_pic
picParams->ref_pic_flag = buf->pic_info_fields.bits.frame_type == 0 ||
(buf->pic_info_fields.bits.frame_type == 3 && buf->pic_info_fields.bits.show_frame);
pps->width = ctx->width;
pps->height = ctx->height;
pps->frame_offset = buf->order_hint;
pps->decodePicIdx = picParams->CurrPicIdx; //TODO not sure about this
pps->profile = buf->profile;
pps->use_128x128_superblock = buf->seq_info_fields.fields.use_128x128_superblock;
pps->subsampling_x = buf->seq_info_fields.fields.subsampling_x;
pps->subsampling_y = buf->seq_info_fields.fields.subsampling_y;
pps->mono_chrome = buf->seq_info_fields.fields.mono_chrome;
pps->bit_depth_minus8 = bit_depth_map[buf->bit_depth_idx];
pps->enable_filter_intra = buf->seq_info_fields.fields.enable_filter_intra;
pps->enable_intra_edge_filter = buf->seq_info_fields.fields.enable_intra_edge_filter;
pps->enable_interintra_compound = buf->seq_info_fields.fields.enable_interintra_compound;
pps->enable_masked_compound = buf->seq_info_fields.fields.enable_masked_compound;
pps->enable_dual_filter = buf->seq_info_fields.fields.enable_dual_filter;
pps->enable_order_hint = buf->seq_info_fields.fields.enable_order_hint;
pps->order_hint_bits_minus1 = buf->order_hint_bits_minus_1;
pps->enable_jnt_comp = buf->seq_info_fields.fields.enable_jnt_comp;
//TODO not quite correct, use_superres can be 0, and enable_superres can be 1
pps->enable_superres = buf->pic_info_fields.bits.use_superres;
pps->enable_cdef = buf->seq_info_fields.fields.enable_cdef;
//TODO this flag just seems to be missing from libva, however we should be able to recover it from the lr_type fields
pps->enable_restoration = buf->loop_restoration_fields.bits.yframe_restoration_type != 0 ||
buf->loop_restoration_fields.bits.cbframe_restoration_type != 0 ||
buf->loop_restoration_fields.bits.crframe_restoration_type != 0;
pps->enable_fgs = buf->seq_info_fields.fields.film_grain_params_present;
pps->frame_type = buf->pic_info_fields.bits.frame_type;
pps->show_frame = buf->pic_info_fields.bits.show_frame;
pps->disable_cdf_update = buf->pic_info_fields.bits.disable_cdf_update;
pps->allow_screen_content_tools = buf->pic_info_fields.bits.allow_screen_content_tools;
pps->force_integer_mv = buf->pic_info_fields.bits.force_integer_mv || picParams->intra_pic_flag;
pps->coded_denom = buf->superres_scale_denominator;
pps->allow_intrabc = buf->pic_info_fields.bits.allow_intrabc;
pps->allow_high_precision_mv = buf->pic_info_fields.bits.allow_high_precision_mv;
pps->interp_filter = buf->interp_filter;
pps->switchable_motion_mode = buf->pic_info_fields.bits.is_motion_mode_switchable;
pps->use_ref_frame_mvs = buf->pic_info_fields.bits.use_ref_frame_mvs;
pps->disable_frame_end_update_cdf = buf->pic_info_fields.bits.disable_frame_end_update_cdf;
pps->delta_q_present = buf->mode_control_fields.bits.delta_q_present_flag;
pps->delta_q_res = buf->mode_control_fields.bits.log2_delta_q_res;
pps->using_qmatrix = buf->qmatrix_fields.bits.using_qmatrix;
pps->use_superres = buf->pic_info_fields.bits.use_superres;
pps->tx_mode = buf->mode_control_fields.bits.tx_mode;
pps->reference_mode = buf->mode_control_fields.bits.reference_select;
pps->allow_warped_motion = buf->pic_info_fields.bits.allow_warped_motion;
pps->reduced_tx_set = buf->mode_control_fields.bits.reduced_tx_set_used;
pps->skip_mode = buf->mode_control_fields.bits.skip_mode_present;
pps->num_tile_cols = buf->tile_cols;
pps->num_tile_rows = buf->tile_rows;
pps->context_update_tile_id = buf->context_update_tile_id;
picParams->nNumSlices = pps->num_tile_cols * pps->num_tile_rows;
pps->cdef_damping_minus_3 = buf->cdef_damping_minus_3;
pps->cdef_bits = buf->cdef_bits;
pps->SkipModeFrame0 = 0;
pps->SkipModeFrame1 = 0;
//we'll need this value in a future frame
ctx->renderTarget->order_hint = pps->frame_offset;
if (pps->skip_mode) {
int forwardIdx = -1;
int backwardIdx = -1;
int forwardHint = 0;
int backwardHint = 0;
int RefOrderHint[8] = {0};
for (int i = 0; i < 8; i++) {
NVSurface *surf = nvSurfaceFromSurfaceId(ctx->drv, buf->ref_frame_map[i]);
if (surf != NULL && surf->pictureIdx != -1) {
RefOrderHint[i] = surf->order_hint;
}
}
for (int i = 0; i < 7; i++ ) {
int refHint = RefOrderHint[ buf->ref_frame_idx[ i ] ];
if ( get_relative_dist( pps, refHint, buf->order_hint ) < 0 ) {
if ( forwardIdx < 0 || get_relative_dist( pps, refHint, forwardHint) > 0 ) {
forwardIdx = i;
forwardHint = refHint;
}
} else if ( get_relative_dist( pps, refHint, buf->order_hint) > 0 ) {
if ( backwardIdx < 0 || get_relative_dist( pps, refHint, backwardHint) < 0 ) {
backwardIdx = i;
backwardHint = refHint;
}
}
}
if ( forwardIdx < 0 ) {
//skipModeAllowed = 0
} else if ( backwardIdx >= 0 ) {
//skipModeAllowed = 1
pps->SkipModeFrame0 = MIN(forwardIdx, backwardIdx) + 1;
pps->SkipModeFrame1 = MAX(forwardIdx, backwardIdx) + 1;
} else {
int secondForwardIdx = -1;
int secondForwardHint = 0;
for (int i = 0; i < 7; i++ ) {
int refHint = RefOrderHint[ buf->ref_frame_idx[ i ] ];
if ( get_relative_dist( pps, refHint, forwardHint ) < 0 ) {
if ( secondForwardIdx < 0 || get_relative_dist( pps, refHint, secondForwardHint ) > 0 ) {
secondForwardIdx = i;
secondForwardHint = refHint;
}
}
}
if ( secondForwardIdx < 0 ) {
//skipModeAllowed = 0
} else {
//skipModeAllowed = 1
pps->SkipModeFrame0 = MIN(forwardIdx, secondForwardIdx) + 1;
pps->SkipModeFrame1 = MAX(forwardIdx, secondForwardIdx) + 1;
}
}
}
for (int i = 0; i < 8; i++) { //MAX_REF_FRAMES
pps->loop_filter_ref_deltas[i] = buf->ref_deltas[i];
pps->ref_frame_map[i] = pictureIdxFromSurfaceId(ctx->drv, buf->ref_frame_map[i]);
}
pps->base_qindex = buf->base_qindex;
pps->qp_y_dc_delta_q = buf->y_dc_delta_q;
pps->qp_u_dc_delta_q = buf->u_dc_delta_q;
pps->qp_v_dc_delta_q = buf->v_dc_delta_q;
pps->qp_u_ac_delta_q = buf->u_ac_delta_q;
pps->qp_v_ac_delta_q = buf->v_ac_delta_q;
pps->qm_y = buf->qmatrix_fields.bits.qm_y;
pps->qm_u = buf->qmatrix_fields.bits.qm_u;
pps->qm_v = buf->qmatrix_fields.bits.qm_v;
pps->segmentation_enabled = buf->seg_info.segment_info_fields.bits.enabled;
pps->segmentation_update_map = buf->seg_info.segment_info_fields.bits.update_map;
pps->segmentation_update_data = buf->seg_info.segment_info_fields.bits.update_data;
pps->segmentation_temporal_update = buf->seg_info.segment_info_fields.bits.temporal_update;
pps->loop_filter_level[0] = buf->filter_level[0];
pps->loop_filter_level[1] = buf->filter_level[1];
pps->loop_filter_level_u = buf->filter_level_u;
pps->loop_filter_level_v = buf->filter_level_v;
pps->loop_filter_sharpness = buf->loop_filter_info_fields.bits.sharpness_level;
pps->loop_filter_delta_enabled = buf->loop_filter_info_fields.bits.mode_ref_delta_enabled;
pps->loop_filter_delta_update = buf->loop_filter_info_fields.bits.mode_ref_delta_update;
pps->loop_filter_mode_deltas[0] = buf->mode_deltas[0];
pps->loop_filter_mode_deltas[1] = buf->mode_deltas[1];
pps->delta_lf_present = buf->mode_control_fields.bits.delta_lf_present_flag;
pps->delta_lf_res = buf->mode_control_fields.bits.log2_delta_lf_res;
pps->delta_lf_multi = buf->mode_control_fields.bits.delta_lf_multi;
pps->lr_type[0] = buf->loop_restoration_fields.bits.yframe_restoration_type;
pps->lr_type[1] = buf->loop_restoration_fields.bits.cbframe_restoration_type;
pps->lr_type[2] = buf->loop_restoration_fields.bits.crframe_restoration_type;
pps->lr_unit_size[0] = 1 + buf->loop_restoration_fields.bits.lr_unit_shift;
pps->lr_unit_size[1] = 1 + buf->loop_restoration_fields.bits.lr_unit_shift - buf->loop_restoration_fields.bits.lr_uv_shift;
pps->lr_unit_size[2] = pps->lr_unit_size[1];
//TODO looks like these need to be derived from the frame itself? They're part of an extension, might just be able to set them to 0
//pps->temporal_layer_id = buf->;
//pps->spatial_layer_id = buf->;
pps->apply_grain = buf->film_grain_info.film_grain_info_fields.bits.apply_grain;
pps->overlap_flag = buf->film_grain_info.film_grain_info_fields.bits.overlap_flag;
pps->scaling_shift_minus8 = buf->film_grain_info.film_grain_info_fields.bits.grain_scaling_minus_8;
pps->chroma_scaling_from_luma = buf->film_grain_info.film_grain_info_fields.bits.chroma_scaling_from_luma;
pps->ar_coeff_lag = buf->film_grain_info.film_grain_info_fields.bits.ar_coeff_lag;
pps->ar_coeff_shift_minus6 = buf->film_grain_info.film_grain_info_fields.bits.ar_coeff_shift_minus_6;
pps->grain_scale_shift = buf->film_grain_info.film_grain_info_fields.bits.grain_scale_shift;
pps->clip_to_restricted_range = buf->film_grain_info.film_grain_info_fields.bits.clip_to_restricted_range;
pps->num_y_points = buf->film_grain_info.num_y_points;
pps->num_cb_points = buf->film_grain_info.num_cb_points;
pps->num_cr_points = buf->film_grain_info.num_cr_points;
pps->random_seed = buf->film_grain_info.grain_seed;
pps->cb_mult = buf->film_grain_info.cb_mult;
pps->cb_luma_mult = buf->film_grain_info.cb_luma_mult;
pps->cb_offset = buf->film_grain_info.cb_offset;
pps->cr_mult = buf->film_grain_info.cr_mult;
pps->cr_luma_mult = buf->film_grain_info.cr_luma_mult;
pps->cr_offset = buf->film_grain_info.cr_offset;
for (int i = 0; i < pps->num_tile_cols; i++) {
pps->tile_widths[i] = 1 + buf->width_in_sbs_minus_1[i];
}
for (int i = 0; i < pps->num_tile_rows; i++) {
pps->tile_heights[i] = 1 + buf->height_in_sbs_minus_1[i];
}
for (int i = 0; i < (1<<pps->cdef_bits); i++) {
pps->cdef_y_strength[i] = ((buf->cdef_y_strengths[i] >> 2) & 0x0f) |
((buf->cdef_y_strengths[i] & 0x03) << 4);
pps->cdef_uv_strength[i] = ((buf->cdef_uv_strengths[i] >> 2) & 0x0f) |
((buf->cdef_uv_strengths[i] & 0x03) << 4);
}
//TODO replace with memcpy?
for (int i = 0; i < 8; i++) { //MAX_SEGMENTS
pps->segmentation_feature_mask[i] = buf->seg_info.feature_mask[i];
for (int j = 0; j < 8; j++) { //MAX_SEGMENT_LEVEL
//TODO these values are clipped when supplied via ffmpeg
pps->segmentation_feature_data[i][j] = buf->seg_info.feature_data[i][j];
}
}
//TODO i think it is correct
pps->coded_lossless = 1;
if (buf->y_dc_delta_q != 0 || buf->u_dc_delta_q != 0 || buf->v_dc_delta_q != 0 || buf->u_ac_delta_q != 0 || buf->v_ac_delta_q != 0) {
pps->coded_lossless = 0;
} else {
for (int i = 0; i < 8; i++) {
if (((pps->segmentation_feature_mask[i] & 1) != 0
&& (pps->base_qindex + pps->segmentation_feature_data[i][0] != 0))
|| pps->base_qindex != 0) {
pps->coded_lossless = 0;
break;
}
}
}
if (buf->primary_ref_frame == 7) { //PRIMARY_REF_NONE
pps->primary_ref_frame = -1;
} else {
//TODO check this
pps->primary_ref_frame = pps->ref_frame_map[buf->ref_frame_idx[buf->primary_ref_frame]];
}
for (int i = 0; i < 7; i++) { //REFS_PER_FRAME
int ref_idx = buf->ref_frame_idx[i];
pps->ref_frame[i].index = pps->ref_frame_map[ref_idx];
//pull these from the surface itself
NVSurface *surf = nvSurfaceFromSurfaceId(ctx->drv, buf->ref_frame_map[i]);
if (surf != NULL) {
pps->ref_frame[i].width = surf->width;
pps->ref_frame[i].height = surf->height;
}
//TODO not sure on this one
pps->global_motion[i].invalid = (buf->wm[i].wmtype == 0);
pps->global_motion[i].wmtype = buf->wm[i].wmtype;
for (int j = 0; j < 6; j++) {
pps->global_motion[i].wmmat[j] = buf->wm[i].wmmat[j];
}
}
if (pps->apply_grain) {
for (int i = 0; i < 14; i++) {
pps->scaling_points_y[i][0] = buf->film_grain_info.point_y_value[i];
pps->scaling_points_y[i][1] = buf->film_grain_info.point_y_scaling[i];
}
for (int i = 0; i < 10; i++) {
pps->scaling_points_cb[i][0] = buf->film_grain_info.point_cb_value[i];
pps->scaling_points_cb[i][1] = buf->film_grain_info.point_cb_scaling[i];
pps->scaling_points_cr[i][0] = buf->film_grain_info.point_cr_value[i];
pps->scaling_points_cr[i][1] = buf->film_grain_info.point_cr_scaling[i];
}
//TODO memcpy?
for (int i = 0; i < 24; i++) {
pps->ar_coeffs_y[i] = buf->film_grain_info.ar_coeffs_y[i];
}
//TODO memcpy?
for (int i = 0; i < 25; i++) {
pps->ar_coeffs_cb[i] = buf->film_grain_info.ar_coeffs_cb[i];
pps->ar_coeffs_cr[i] = buf->film_grain_info.ar_coeffs_cr[i];
}
}
//printCUVIDPICPARAMS(picParams);
}
static void copyAV1SliceParam(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams) {
ctx->lastSliceParams = buf->ptr;
ctx->lastSliceParamsCount = buf->elements;
picParams->nNumSlices += buf->elements;
}
static void copyAV1SliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams) {
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++) {
VASliceParameterBufferAV1 *sliceParams = &((VASliceParameterBufferAV1*) ctx->lastSliceParams)[i];
//copy just the slice we're looking at
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
//now append the offset and size of the slice we just copied
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
offset += sliceParams->slice_data_size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
}
picParams->nBitstreamDataLen = ctx->bitstreamBuffer.size;
}
static cudaVideoCodec computeAV1CudaCodec(VAProfile profile) {
switch (profile) {
case VAProfileAV1Profile0:
case VAProfileAV1Profile1:
return cudaVideoCodec_AV1;
default:
return cudaVideoCodec_NONE;
}
}
static const VAProfile av1SupportedProfiles[] = {
VAProfileAV1Profile0,
VAProfileAV1Profile1,
};
const DECLARE_CODEC(av1Codec) = {
.computeCudaCodec = computeAV1CudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyAV1PicParam,
[VASliceParameterBufferType] = copyAV1SliceParam,
[VASliceDataBufferType] = copyAV1SliceData
},
.supportedProfileCount = ARRAY_SIZE(av1SupportedProfiles),
.supportedProfiles = av1SupportedProfiles,
};
0707010000002F000081A4000000000000000000000001663926A70000042E000000000000000000000000000000000000003000000000nvidia-vaapi-driver-0.0.12/src/backend-common.c#include "vabackend.h"
#include "backend-common.h"
#include <sys/ioctl.h>
#include <string.h>
bool checkModesetParameterFromFd(int fd) {
if (fd > 0) {
//this ioctl should fail if modeset=0
struct drm_get_cap caps = { .capability = DRM_CAP_DUMB_BUFFER };
int ret = ioctl(fd, DRM_IOCTL_GET_CAP, &caps);
if (ret != 0) {
//the modeset parameter is set to 0
LOG("ERROR: This driver requires the nvidia_drm.modeset kernel module parameter set to 1");
return false;
}
return true;
}
return true;
}
bool isNvidiaDrmFd(int fd, bool log) {
if (fd > 0) {
char name[16] = {0};
struct drm_version ver = {
.name = name,
.name_len = 15
};
int ret = ioctl(fd, DRM_IOCTL_VERSION, &ver);
if (ret || strncmp(name, "nvidia-drm", 10)) {
if (log) {
LOG("Invalid driver for DRM device: %s", ver.name);
}
return false;
}
return true;
}
return false;
}
07070100000030000081A4000000000000000000000001663926A7000000B2000000000000000000000000000000000000003000000000nvidia-vaapi-driver-0.0.12/src/backend-common.h#ifndef BACKENDCOMMON_H
#define BACKENDCOMMON_H
#include <stdbool.h>
bool checkModesetParameterFromFd(int fd);
bool isNvidiaDrmFd(int fd, bool log);
#endif // BACKENDCOMMON_H
07070100000031000081A4000000000000000000000001663926A70000011A000000000000000000000000000000000000002800000000nvidia-vaapi-driver-0.0.12/src/common.h//
// Created by stephen on 12/11/23.
//
#ifndef COMMON_H
#define COMMON_H
typedef struct
{
uint32_t x;
uint32_t y;
} NVSubSampling;
typedef struct
{
uint32_t channelCount;
uint32_t fourcc;
NVSubSampling ss; // subsampling
} NVFormatPlane;
#endif //COMMON_H
07070100000032000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/src/direct07070100000033000081A4000000000000000000000001663926A700003074000000000000000000000000000000000000003A00000000nvidia-vaapi-driver-0.0.12/src/direct/direct-export-buf.c#define _GNU_SOURCE 1
#include "../vabackend.h"
#include <stdio.h>
#include <ffnvcodec/dynlink_loader.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <unistd.h>
#ifdef __linux__
#include <sys/sysmacros.h>
#endif
#include <string.h>
#include "../backend-common.h"
#include <drm.h>
#include <drm_fourcc.h>
static void destroyBackingImage(NVDriver *drv, BackingImage *img);
static void findGPUIndexFromFd(NVDriver *drv) {
//find the CUDA device id
char drmUuid[16];
get_device_uuid(&drv->driverContext, drmUuid);
int gpuCount = 0;
if (CHECK_CUDA_RESULT(drv->cu->cuDeviceGetCount(&gpuCount))) {
return;
}
for (int i = 0; i < gpuCount; i++) {
CUuuid uuid;
if (!CHECK_CUDA_RESULT(drv->cu->cuDeviceGetUuid(&uuid, i))) {
if (memcmp(drmUuid, uuid.bytes, 16) == 0) {
drv->cudaGpuId = i;
return;
}
}
}
//default to index 0
drv->cudaGpuId = 0;
}
static void debug(EGLenum error,const char *command,EGLint messageType,EGLLabelKHR threadLabel,EGLLabelKHR objectLabel,const char* message) {
LOG("[EGL] %s: %s", command, message);
}
static bool direct_initExporter(NVDriver *drv) {
//this is only needed to see errors in firefox
static const EGLAttrib debugAttribs[] = {EGL_DEBUG_MSG_WARN_KHR, EGL_TRUE, EGL_DEBUG_MSG_INFO_KHR, EGL_TRUE, EGL_NONE};
const PFNEGLDEBUGMESSAGECONTROLKHRPROC eglDebugMessageControlKHR = (PFNEGLDEBUGMESSAGECONTROLKHRPROC) eglGetProcAddress("eglDebugMessageControlKHR");
eglDebugMessageControlKHR(debug, debugAttribs);
//make sure we have a drm fd
if (drv->drmFd == -1) {
int nvdGpu = drv->cudaGpuId;
if (nvdGpu == -1) {
// The default GPU is the first one we find.
nvdGpu = 0;
}
int fd;
int nvIdx = 0;
uint8_t drmIdx = 128;
char node[20] = {0, };
do {
LOG("Searching for GPU: %d %d %d", nvIdx, nvdGpu, drmIdx)
snprintf(node, 20, "/dev/dri/renderD%d", drmIdx++);
fd = open(node, O_RDWR|O_CLOEXEC);
if (fd == -1) {
LOG("Unable to find NVIDIA GPU %d", nvdGpu);
return false;
}
if (!isNvidiaDrmFd(fd, true) || !checkModesetParameterFromFd(fd)) {
close(fd);
continue;
}
if (nvIdx != nvdGpu) {
close(fd);
nvIdx++;
continue;
}
break;
} while (drmIdx < 128 + 16);
drv->drmFd = fd;
LOG("Found NVIDIA GPU %d at %s", nvdGpu, node);
} else {
if (!isNvidiaDrmFd(drv->drmFd, true) || !checkModesetParameterFromFd(drv->drmFd)) {
return false;
}
//dup it so we can close it later and not effect firefox
drv->drmFd = dup(drv->drmFd);
}
const bool ret = init_nvdriver(&drv->driverContext, drv->drmFd);
//TODO this isn't really correct as we don't know if the driver version actually supports importing them
//but we don't have an easy way to find out.
drv->supports16BitSurface = true;
drv->supports444Surface = true;
findGPUIndexFromFd(drv);
return ret;
}
static void direct_releaseExporter(NVDriver *drv) {
free_nvdriver(&drv->driverContext);
}
static BackingImage *direct_allocateBackingImage(NVDriver *drv, NVSurface *surface) {
NVDriverImage driverImages[3] = { 0 };
BackingImage *backingImage = calloc(1, sizeof(BackingImage));
switch (surface->format)
{
case cudaVideoSurfaceFormat_P016:
switch (surface->bitDepth) {
case 10:
backingImage->format = NV_FORMAT_P010;
break;
case 12:
backingImage->format = NV_FORMAT_P012;
break;
default:
backingImage->format = NV_FORMAT_P016;
break;
}
break;
case cudaVideoSurfaceFormat_YUV444_16Bit:
backingImage->format = NV_FORMAT_Q416;
break;
case cudaVideoSurfaceFormat_YUV444:
backingImage->format = NV_FORMAT_444P;
break;
default:
backingImage->format = NV_FORMAT_NV12;
break;
}
const NVFormatInfo *fmtInfo = &formatsInfo[backingImage->format];
backingImage->totalSize = calculate_image_size(&drv->driverContext, driverImages, surface->width, surface->height, fmtInfo->bppc, fmtInfo->numPlanes, fmtInfo->plane);
LOG("Allocating BackingImage: %p %ux%u = %u bytes", backingImage, surface->width, surface->height, backingImage->totalSize);
//alloc memory - Note this requires that all the planes have the same widthInBytes
//otherwise the value passed to the kernel driver won't be correct, luckily all the formats
//we currently support are all the same width
int memFd = 0, memFd2 = 0, drmFd = 0;
if (!alloc_buffer(&drv->driverContext, backingImage->totalSize, driverImages, &memFd, &memFd2, &drmFd)) {
goto import_fail;
}
LOG("Allocate Buffer: %d %d %d", memFd, memFd2, drmFd);
//import the memory to CUDA
const CUDA_EXTERNAL_MEMORY_HANDLE_DESC extMemDesc = {
.type = CU_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD,
.handle.fd = memFd,
.flags = 0,
.size = backingImage->totalSize
};
LOG("Importing memory to CUDA")
if (CHECK_CUDA_RESULT(drv->cu->cuImportExternalMemory(&backingImage->extMem, &extMemDesc))) {
goto import_fail;
}
close(memFd);
close(memFd2);
memFd = -1;
memFd2 = -1;
//now map the arrays
for (uint32_t i = 0; i < fmtInfo->numPlanes; i++) {
CUDA_EXTERNAL_MEMORY_MIPMAPPED_ARRAY_DESC mipmapArrayDesc = {
.arrayDesc = {
.Width = driverImages[i].width,
.Height = driverImages[i].height,
.Depth = 0,
.Format = fmtInfo->bppc == 1 ? CU_AD_FORMAT_UNSIGNED_INT8 : CU_AD_FORMAT_UNSIGNED_INT16,
.NumChannels = fmtInfo->plane[i].channelCount,
.Flags = 0
},
.numLevels = 1,
.offset = driverImages[i].offset
};
//create a mimap array from the imported memory
if (CHECK_CUDA_RESULT(drv->cu->cuExternalMemoryGetMappedMipmappedArray(&backingImage->cudaImages[i].mipmapArray, backingImage->extMem, &mipmapArrayDesc))) {
goto bail;
}
//create an array from the mipmap array
if (CHECK_CUDA_RESULT(drv->cu->cuMipmappedArrayGetLevel(&backingImage->arrays[i], backingImage->cudaImages[i].mipmapArray, 0))) {
goto bail;
}
}
backingImage->width = surface->width;
backingImage->height = surface->height;
backingImage->fds[0] = drmFd;
for (uint32_t i = 0; i < fmtInfo->numPlanes; i++) {
backingImage->strides[i] = driverImages[i].pitch;
backingImage->mods[i] = driverImages[i].mods;
backingImage->offsets[i] = driverImages[i].offset;
}
return backingImage;
bail:
destroyBackingImage(drv, backingImage);
import_fail:
if (memFd != 0) {
close(memFd);
}
if (memFd != 0) {
close(memFd);
}
if (drmFd != 0) {
close(drmFd);
}
free(backingImage);
return NULL;
}
static void destroyBackingImage(NVDriver *drv, BackingImage *img) {
const NVFormatInfo *fmtInfo = &formatsInfo[img->format];
if (img->surface != NULL) {
img->surface->backingImage = NULL;
}
for (int i = 0; i < 4; i++) {
if (img->fds[i] > 0) {
close(img->fds[i]);
}
}
for (uint32_t i = 0; i < fmtInfo->numPlanes; i++) {
if (img->arrays[i] != NULL) {
CHECK_CUDA_RESULT(drv->cu->cuArrayDestroy(img->arrays[i]));
}
if (img->cudaImages[i].mipmapArray != NULL) {
CHECK_CUDA_RESULT(drv->cu->cuMipmappedArrayDestroy(img->cudaImages[i].mipmapArray));
}
}
if (img->extMem != NULL) {
CHECK_CUDA_RESULT(drv->cu->cuDestroyExternalMemory(img->extMem));
}
memset(img, 0, sizeof(BackingImage));
free(img);
}
static void direct_attachBackingImageToSurface(NVSurface *surface, BackingImage *img) {
surface->backingImage = img;
img->surface = surface;
}
static void direct_detachBackingImageFromSurface(NVDriver *drv, NVSurface *surface) {
if (surface->backingImage == NULL) {
return;
}
destroyBackingImage(drv, surface->backingImage);
surface->backingImage = NULL;
}
static void direct_destroyAllBackingImage(NVDriver *drv) {
pthread_mutex_lock(&drv->imagesMutex);
ARRAY_FOR_EACH_REV(BackingImage*, it, &drv->images)
destroyBackingImage(drv, it);
remove_element_at(&drv->images, it_idx);
END_FOR_EACH
pthread_mutex_unlock(&drv->imagesMutex);
}
static bool copyFrameToSurface(NVDriver *drv, CUdeviceptr ptr, NVSurface *surface, uint32_t pitch) {
const NVFormatInfo *fmtInfo = &formatsInfo[surface->backingImage->format];
uint32_t y = 0;
for (uint32_t i = 0; i < fmtInfo->numPlanes; i++) {
const NVFormatPlane *p = &fmtInfo->plane[i];
CUDA_MEMCPY2D cpy = {
.srcMemoryType = CU_MEMORYTYPE_DEVICE,
.srcDevice = ptr,
.srcY = y,
.srcPitch = pitch,
.dstMemoryType = CU_MEMORYTYPE_ARRAY,
.dstArray = surface->backingImage->arrays[i],
.Height = surface->height >> p->ss.y,
.WidthInBytes = (surface->width >> p->ss.x) * fmtInfo->bppc * p->channelCount
};
if (i == fmtInfo->numPlanes - 1) {
CHECK_CUDA_RESULT(drv->cu->cuMemcpy2D(&cpy));
} else {
CHECK_CUDA_RESULT(drv->cu->cuMemcpy2DAsync(&cpy, 0));
}
y += cpy.Height;
}
//notify anyone waiting for us to be resolved
pthread_mutex_lock(&surface->mutex);
surface->resolving = 0;
pthread_cond_signal(&surface->cond);
pthread_mutex_unlock(&surface->mutex);
return true;
}
static bool direct_realiseSurface(NVDriver *drv, NVSurface *surface) {
//make sure we're the only thread updating this surface
pthread_mutex_lock(&surface->mutex);
//check again to see if it's just been created
if (surface->backingImage == NULL) {
//try to find a free surface
BackingImage *img = direct_allocateBackingImage(drv, surface);
if (img == NULL) {
LOG("Unable to realise surface: %p (%d)", surface, surface->pictureIdx)
pthread_mutex_unlock(&surface->mutex);
return false;
}
direct_attachBackingImageToSurface(surface, img);
}
pthread_mutex_unlock(&surface->mutex);
return true;
}
static bool direct_exportCudaPtr(NVDriver *drv, CUdeviceptr ptr, NVSurface *surface, uint32_t pitch) {
if (!direct_realiseSurface(drv, surface)) {
return false;
}
if (ptr != 0) {
copyFrameToSurface(drv, ptr, surface, pitch);
} else {
LOG("exporting with null ptr")
}
return true;
}
static bool direct_fillExportDescriptor(NVDriver *drv, NVSurface *surface, VADRMPRIMESurfaceDescriptor *desc) {
const BackingImage *img = surface->backingImage;
const NVFormatInfo *fmtInfo = &formatsInfo[img->format];
desc->fourcc = fmtInfo->fourcc;
desc->width = surface->width;
desc->height = surface->height;
desc->num_layers = fmtInfo->numPlanes;
desc->num_objects = 1;
desc->objects[0].fd = dup(img->fds[0]);
desc->objects[0].size = img->totalSize;
desc->objects[0].drm_format_modifier = img->mods[0];
for (uint32_t i = 0; i < fmtInfo->numPlanes; i++) {
desc->layers[i].drm_format = fmtInfo->plane[i].fourcc;
desc->layers[i].num_planes = 1;
desc->layers[i].object_index[0] = 0;
desc->layers[i].offset[0] = img->offsets[i];
desc->layers[i].pitch[0] = img->strides[i];
}
return true;
}
const NVBackend DIRECT_BACKEND = {
.name = "direct",
.initExporter = direct_initExporter,
.releaseExporter = direct_releaseExporter,
.exportCudaPtr = direct_exportCudaPtr,
.detachBackingImageFromSurface = direct_detachBackingImageFromSurface,
.realiseSurface = direct_realiseSurface,
.fillExportDescriptor = direct_fillExportDescriptor,
.destroyAllBackingImage = direct_destroyAllBackingImage
};
07070100000034000081A4000000000000000000000001663926A700004C3A000000000000000000000000000000000000003200000000nvidia-vaapi-driver-0.0.12/src/direct/nv-driver.c#define _GNU_SOURCE 1
#include <sys/ioctl.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <stdint.h>
#include <errno.h>
#include <drm_fourcc.h>
#include "nv-driver.h"
#include <nvidia.h>
#include <sys/param.h>
#include "../vabackend.h"
#if !defined(_IOC_READ) && defined(IOC_OUT)
#define _IOC_READ IOC_OUT
#endif
#if !defined(_IOC_WRITE) && defined(IOC_IN)
#define _IOC_WRITE IOC_IN
#endif
//Technically these can vary per architecture, but all the ones we support have the same values
#define GOB_WIDTH_IN_BYTES 64
#define GOB_HEIGHT_IN_BYTES 8
static const NvHandle NULL_OBJECT;
static bool nv_alloc_object(const int fd, const int driverMajorVersion, const NvHandle hRoot, const NvHandle hObjectParent,
NvHandle* hObjectNew,const NvV32 hClass, const uint32_t paramSize, void* params) {
NVOS64_PARAMETERS alloc = {
.hRoot = hRoot,
.hObjectParent = hObjectParent,
.hObjectNew = *hObjectNew,
.hClass = hClass,
.pRightsRequested = (NvP64)NULL,
.pAllocParms = (NvP64)params,
.paramsSize = paramSize
};
//make sure we force this to 0 if the driver won't be using it
//as we'll need to check it for the status on the way out
if (driverMajorVersion < 535) {
alloc.paramsSize = 0;
}
//v525 is the base and is 40 bytes large
//v530 has an extra `flags` field, and is *still* 40 bytes large
//v535 has `paramsSize` and `flags` fields, and is 48 bytes large
int size = sizeof(NVOS64_PARAMETERS);
if (driverMajorVersion < 535) {
size -= 8;
}
const int ret = ioctl(fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_RM_ALLOC, size), &alloc);
//this structure changed over the versions, make sure we read the status from the correct place
//luckily the two new fields are the same width as the status field, so we can just read from that directly
int status = 0;
if (driverMajorVersion < 525) {
status = alloc.paramsSize;
} else if (driverMajorVersion < 535) {
status = alloc.flags;
} else {
status = alloc.status;
}
if (ret != 0 || status != NV_OK) {
LOG("nv_alloc_object failed: %d %X %d", ret, status, errno);
return false;
}
*hObjectNew = alloc.hObjectNew;
return true;
}
static bool nv_free_object(const int fd, const NvHandle hRoot, const NvHandle hObject) {
if (hObject == 0) {
return true;
}
NVOS00_PARAMETERS freeParams = {
.hRoot = hRoot,
.hObjectParent = NULL_OBJECT,
.hObjectOld = hObject
};
const int ret = ioctl(fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_RM_FREE, sizeof(NVOS00_PARAMETERS)), &freeParams);
if (ret != 0 || freeParams.status != NV_OK) {
LOG("nv_free_object failed: %d %X %d", ret, freeParams.status, errno);
return false;
}
return true;
}
static bool nv_rm_control(const int fd, const NvHandle hClient, const NvHandle hObject, const NvV32 cmd,
const NvU32 flags, const int paramSize, void* params) {
NVOS54_PARAMETERS control = {
.hClient = hClient,
.hObject = hObject,
.cmd = cmd,
.flags = flags,
.params = (NvP64)params,
.paramsSize = paramSize
};
const int ret = ioctl(fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_RM_CONTROL, sizeof(NVOS54_PARAMETERS)), &control);
if (ret != 0 || control.status != NV_OK) {
LOG("nv_rm_control failed: %d %X %d", ret, control.status, errno);
return false;
}
return true;
}
#if 0
static NvU64 nv_sys_params(int fd) {
//read from /sys/devices/system/memory/block_size_bytes
nv_ioctl_sys_params_t obj = { .memblock_size = 0x8000000 };
int ret = ioctl(fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_SYS_PARAMS, sizeof(obj)), &obj);
if (ret != 0) {
LOG("nv_sys_params failed: %d %d", ret, errno);
return 0;
}
return obj.memblock_size;
}
static bool nv_card_info(int fd, nv_ioctl_card_info_t (*card_info)[32]) {
int ret = ioctl(fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_CARD_INFO, sizeof(nv_ioctl_card_info_t) * 32), card_info);
if (ret != 0) {
LOG("nv_card_info failed: %d %d", ret, errno);
return false;
}
return ret == 0;
}
#endif
static bool nv_attach_gpus(const int fd, int gpu) {
const int ret = ioctl(fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_ATTACH_GPUS_TO_FD, sizeof(gpu)), &gpu);
if (ret != 0) {
LOG("nv_attach_gpus failed: %d %d", ret, errno);
return false;
}
return true;
}
static bool nv_export_object_to_fd(const int fd, const int export_fd, const NvHandle hClient, const NvHandle hDevice,
const NvHandle hParent,const NvHandle hObject) {
NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS params = {
.fd = export_fd,
.flags = 0,
.object = {
.type = NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TYPE_RM,
.data.rmObject = {
.hDevice = hDevice,
.hParent = hParent,
.hObject = hObject
}
}
};
return nv_rm_control(fd, hClient, hClient, NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD, 0, sizeof(params), ¶ms);
}
static bool nv_get_versions(const int fd, char **versionString) {
nv_ioctl_rm_api_version_t obj = {
.cmd = '2' //query
};
const int ret = ioctl(fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_CHECK_VERSION_STR, sizeof(obj)), &obj);
if (ret != 0) {
LOG("nv_check_version failed: %d %d", ret, errno);
return false;
}
if (strlen(obj.versionString) == 0) {
//the newer 470 series of drivers don't actually return the version number, so just substitute in a dummy one
*versionString = strdup("470.123.45");
} else {
*versionString = strdup(obj.versionString);
}
return obj.reply == NV_RM_API_VERSION_REPLY_RECOGNIZED;
}
static bool nv0_register_fd(const int nv0_fd, int nvctl_fd) {
const int ret = ioctl(nv0_fd, _IOC(_IOC_READ|_IOC_WRITE, NV_IOCTL_MAGIC, NV_ESC_REGISTER_FD, sizeof(int)), &nvctl_fd);
if (ret != 0) {
LOG("nv0_register_fd failed: %d %d", ret, errno);
return false;
}
return true;
}
static bool get_device_info(const int fd, NVDriverContext *context) {
//NVIDIA driver v545.29.02 changed the devInfo struct, and partly broke it in the process
//...who adds a field to the middle of an existing struct....
if (context->driverMajorVersion >= 545 && context->driverMinorVersion >= 29) {
struct drm_nvidia_get_dev_info_params_545 devInfo545;
const int ret = ioctl(fd, DRM_IOCTL_NVIDIA_GET_DEV_INFO_545, &devInfo545);
if (ret != 0) {
LOG("get_device_info failed: %d %d", ret, errno);
return false;
}
context->gpu_id = devInfo545.gpu_id;
context->sector_layout = devInfo545.sector_layout;
context->page_kind_generation = devInfo545.page_kind_generation;
context->generic_page_kind = devInfo545.generic_page_kind;
} else {
struct drm_nvidia_get_dev_info_params devInfo;
const int ret = ioctl(fd, DRM_IOCTL_NVIDIA_GET_DEV_INFO, &devInfo);
if (ret != 0) {
LOG("get_device_info failed: %d %d", ret, errno);
return false;
}
context->gpu_id = devInfo.gpu_id;
context->sector_layout = devInfo.sector_layout;
context->page_kind_generation = devInfo.page_kind_generation;
context->generic_page_kind = devInfo.generic_page_kind;
}
return true;
}
bool get_device_uuid(const NVDriverContext *context, char uuid[16]) {
NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS uuidParams = {
.gpuId = context->gpu_id,
.flags = NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_FORMAT_BINARY |
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID_FLAGS_TYPE_SHA1
};
const int ret = nv_rm_control(context->nvctlFd, context->clientObject, context->clientObject, NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID, 0, sizeof(uuidParams), &uuidParams);
if (ret) {
return false;
}
for (int i = 0; i < 16; i++) {
uuid[i] = uuidParams.gpuUuid[i];
}
return true;
}
bool init_nvdriver(NVDriverContext *context, const int drmFd) {
LOG("Initing nvdriver...");
int nvctlFd = -1, nv0Fd = -1;
nvctlFd = open("/dev/nvidiactl", O_RDWR|O_CLOEXEC);
if (nvctlFd == -1) {
goto err;
}
nv0Fd = open("/dev/nvidia0", O_RDWR|O_CLOEXEC);
if (nv0Fd == -1) {
goto err;
}
//query the version of the api
char *ver = NULL;
nv_get_versions(nvctlFd, &ver);
context->driverMajorVersion = atoi(ver);
context->driverMinorVersion = atoi(ver+4);
LOG("NVIDIA kernel driver version: %s, major version: %d, minor version: %d", ver, context->driverMajorVersion, context->driverMinorVersion);
free(ver);
if (!get_device_info(drmFd, context)) {
return false;
}
LOG("Got dev info: %x %x %x %x", context->gpu_id, context->sector_layout, context->page_kind_generation, context->generic_page_kind);
//allocate the root object
bool ret = nv_alloc_object(nvctlFd, context->driverMajorVersion, NULL_OBJECT, NULL_OBJECT, &context->clientObject, NV01_ROOT_CLIENT, 0, (void*)0);
if (!ret) {
LOG("nv_alloc_object NV01_ROOT_CLIENT failed");
goto err;
}
//attach the drm fd to this handle
ret = nv_attach_gpus(nvctlFd, context->gpu_id);
if (!ret) {
LOG("nv_attach_gpu failed");
goto err;
}
//allocate the parent memory object
NV0080_ALLOC_PARAMETERS deviceParams = {
.hClientShare = context->clientObject
};
//allocate the device object
ret = nv_alloc_object(nvctlFd, context->driverMajorVersion, context->clientObject, context->clientObject, &context->deviceObject, NV01_DEVICE_0, sizeof(deviceParams), &deviceParams);
if (!ret) {
LOG("nv_alloc_object NV01_DEVICE_0 failed");
goto err;
}
//allocate the subdevice object
NV2080_ALLOC_PARAMETERS subdevice = { 0 };
ret = nv_alloc_object(nvctlFd, context->driverMajorVersion, context->clientObject, context->deviceObject, &context->subdeviceObject, NV20_SUBDEVICE_0, sizeof(subdevice), &subdevice);
if (!ret) {
LOG("nv_alloc_object NV20_SUBDEVICE_0 failed");
goto err;
}
//TODO honestly not sure if this is needed
ret = nv0_register_fd(nv0Fd, nvctlFd);
if (!ret) {
LOG("nv0_register_fd failed");
goto err;
}
//figure out what page sizes are available
//we don't actually need this at the moment
// NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS vaParams = {0};
// ret = nv_rm_control(nvctlFd, context->clientObject, context->deviceObject, NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS, 0, sizeof(vaParams), &vaParams);
// if (!ret) {
// LOG("NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS failed");
// goto err;
// }
// LOG("Got big page size: %d, huge page size: %d", vaParams.bigPageSize, vaParams.hugePageSize);
context->drmFd = drmFd;
context->nvctlFd = nvctlFd;
context->nv0Fd = nv0Fd;
//context->hasHugePage = vaParams.hugePageSize != 0;
return true;
err:
LOG("Got error initing");
if (nvctlFd != -1) {
close(nvctlFd);
}
if (nv0Fd != -1) {
close(nv0Fd);
}
return false;
}
bool free_nvdriver(NVDriverContext *context) {
nv_free_object(context->nvctlFd, context->clientObject, context->subdeviceObject);
nv_free_object(context->nvctlFd, context->clientObject, context->deviceObject);
nv_free_object(context->nvctlFd, context->clientObject, context->clientObject);
if (context->nvctlFd > 0) {
close(context->nvctlFd);
}
if (context->drmFd > 0) {
close(context->drmFd);
}
if (context->nv0Fd > 0) {
close(context->nv0Fd);
}
memset(context, 0, sizeof(NVDriverContext));
return true;
}
bool alloc_memory(const NVDriverContext *context, const uint32_t size, int *fd) {
//allocate the buffer
int nvctlFd2 = -1;
NvHandle bufferObject = {0};
NV_MEMORY_ALLOCATION_PARAMS memParams = {
.owner = context->clientObject,
.type = NVOS32_TYPE_IMAGE,
.flags = NVOS32_ALLOC_FLAGS_IGNORE_BANK_PLACEMENT |
NVOS32_ALLOC_FLAGS_MAP_NOT_REQUIRED |
NVOS32_ALLOC_FLAGS_PERSISTENT_VIDMEM,
.attr = DRF_DEF(OS32, _ATTR, _PAGE_SIZE, _BIG) |
DRF_DEF(OS32, _ATTR, _DEPTH, _UNKNOWN) |
DRF_DEF(OS32, _ATTR, _FORMAT, _BLOCK_LINEAR) |
DRF_DEF(OS32, _ATTR, _PHYSICALITY, _CONTIGUOUS),
.format = 0,
.width = 0,
.height = 0,
.size = size,
.alignment = 0, //see flags above
.attr2 = DRF_DEF(OS32, _ATTR2, _ZBC, _PREFER_NO_ZBC) |
DRF_DEF(OS32, _ATTR2, _GPU_CACHEABLE, _YES)
};
bool ret = nv_alloc_object(context->nvctlFd, context->driverMajorVersion, context->clientObject, context->deviceObject, &bufferObject, NV01_MEMORY_LOCAL_USER, sizeof(memParams), &memParams);
if (!ret) {
LOG("nv_alloc_object NV01_MEMORY_LOCAL_USER failed");
return false;
}
//open a new handle to return
nvctlFd2 = open("/dev/nvidiactl", O_RDWR|O_CLOEXEC);
if (nvctlFd2 == -1) {
LOG("open /dev/nvidiactl failed");
goto err;
}
//attach the new fd to the correct gpus
ret = nv_attach_gpus(nvctlFd2, context->gpu_id);
if (!ret) {
LOG("nv_attach_gpus failed");
goto err;
}
//actually export the object
ret = nv_export_object_to_fd(context->nvctlFd, nvctlFd2, context->clientObject, context->deviceObject, context->deviceObject, bufferObject);
if (!ret) {
LOG("nv_export_object_to_fd failed");
goto err;
}
ret = nv_free_object(context->nvctlFd, context->clientObject, bufferObject);
if (!ret) {
LOG("nv_free_object failed");
goto err;
}
*fd = nvctlFd2;
return true;
err:
LOG("error");
if (nvctlFd2 > 0) {
close(nvctlFd2);
}
ret = nv_free_object(context->nvctlFd, context->clientObject, bufferObject);
if (!ret) {
LOG("nv_free_object failed");
}
return false;
}
uint32_t calculate_image_size(const NVDriverContext *context, NVDriverImage images[], const uint32_t width, const uint32_t height,
const uint32_t bppc, const uint32_t numPlanes, const NVFormatPlane planes[]) {
//first figure out the gob layout
const uint32_t log2GobsPerBlockX = 0;
const uint32_t log2GobsPerBlockZ = 0;
uint32_t offset = 0;
for (uint32_t i = 0; i < numPlanes; i++) {
//calculate each planes dimensions and bpp
const uint32_t planeWidth = width >> planes[i].ss.x;
const uint32_t planeHeight = height >> planes[i].ss.y;
const uint32_t bytesPerPixel = planes[i].channelCount * bppc;
//Depending on the height of the allocated image, the modifiers
//needed for the exported image to work correctly change. However this can cause problems if the Y surface
//needs one modifier, and UV need another when attempting to use a single surface export (as only one modifier
//is possible). So for now we're just going to limit the minimum height to 88 pixels so we can use a single
//modifier.
//Update: with the single buffer export this no longer works, as we're only allowed one mod per fd when exporting
//so different memory layouts for different planes can't work. Luckily this only seems to effect videos <= 128 pixels high.
uint32_t log2GobsPerBlockY = 4;
//uint32_t log2GobsPerBlockY = (planeHeight < 88) ? 3 : 4;
//LOG("Calculated log2GobsPerBlockY: %dx%d == %d", planeWidth, planeHeight, log2GobsPerBlockY);
//These two seem to be correct, but it was discovered by trial and error so I'm not 100% sure
const uint32_t widthInBytes = ROUND_UP(planeWidth * bytesPerPixel, GOB_WIDTH_IN_BYTES << log2GobsPerBlockX);
const uint32_t alignedHeight = ROUND_UP(planeHeight, GOB_HEIGHT_IN_BYTES << log2GobsPerBlockY);
images[i].width = planeWidth;
images[i].height = alignedHeight;
images[i].offset = offset;
images[i].memorySize = widthInBytes * alignedHeight;
images[i].pitch = widthInBytes;
images[i].mods = DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, context->sector_layout, context->page_kind_generation, context->generic_page_kind, log2GobsPerBlockY);
images[i].fourcc = planes[i].fourcc;
images[i].log2GobsPerBlockX = log2GobsPerBlockX;
images[i].log2GobsPerBlockY = log2GobsPerBlockY;
images[i].log2GobsPerBlockZ = log2GobsPerBlockZ;
offset += images[i].memorySize;
offset = ROUND_UP(offset, 64);
}
return offset;
}
bool alloc_buffer(NVDriverContext *context, const uint32_t size, const NVDriverImage images[], int *fd1, int *fd2, int *drmFd) {
int memFd = -1;
const bool ret = alloc_memory(context, size, &memFd);
if (!ret) {
LOG("alloc_memory failed");
return false;
}
//now export the dma-buf
//duplicate the fd so we don't invalidate it by importing it
const int memFd2 = dup(memFd);
if (memFd2 == -1) {
LOG("dup failed");
goto err;
}
struct NvKmsKapiPrivImportMemoryParams nvkmsParams = {
.memFd = memFd2,
.surfaceParams = {
.layout = NvKmsSurfaceMemoryLayoutBlockLinear,
.blockLinear = {
.genericMemory = 0,
.pitchInBlocks = images[0].pitch / GOB_WIDTH_IN_BYTES,
.log2GobsPerBlock.x = images[0].log2GobsPerBlockX,
.log2GobsPerBlock.y = images[0].log2GobsPerBlockY,
.log2GobsPerBlock.z = images[0].log2GobsPerBlockZ,
}
}
};
struct drm_nvidia_gem_import_nvkms_memory_params params = {
.mem_size = size,
.nvkms_params_ptr = (uint64_t) &nvkmsParams,
.nvkms_params_size = context->driverMajorVersion == 470 ? 0x20 : sizeof(nvkmsParams) //needs to be 0x20 in the 470 series driver
};
int drmret = ioctl(context->drmFd, DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY, ¶ms);
if (drmret != 0) {
LOG("DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY failed: %d %d", drmret, errno);
goto err;
}
//export dma-buf
struct drm_prime_handle prime_handle = {
.handle = params.handle
};
drmret = ioctl(context->drmFd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &prime_handle);
if (drmret != 0) {
LOG("DRM_IOCTL_PRIME_HANDLE_TO_FD failed: %d %d", drmret, errno);
goto err;
}
struct drm_gem_close gem_close = {
.handle = params.handle
};
drmret = ioctl(context->drmFd, DRM_IOCTL_GEM_CLOSE, &gem_close);
if (drmret != 0) {
LOG("DRM_IOCTL_GEM_CLOSE failed: %d %d", drmret, errno);
goto prime_err;
}
*fd1 = memFd;
*fd2 = memFd2;
*drmFd = prime_handle.fd;
return true;
prime_err:
if (prime_handle.fd > 0) {
close(prime_handle.fd);
}
err:
if (memFd > 0) {
close(memFd);
}
return false;
}
07070100000035000081A4000000000000000000000001663926A70000057E000000000000000000000000000000000000003200000000nvidia-vaapi-driver-0.0.12/src/direct/nv-driver.h#ifndef NV_DRIVER_H
#define NV_DRIVER_H
#include <stdint.h>
#include <stdbool.h>
#include "../common.h"
#include "nvidia-drm-ioctl.h"
#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
typedef struct {
int nvctlFd;
int nv0Fd;
int drmFd;
uint32_t clientObject;
uint32_t deviceObject;
uint32_t subdeviceObject;
uint32_t driverMajorVersion;
uint32_t driverMinorVersion;
//bool hasHugePage;
uint32_t gpu_id;
uint32_t generic_page_kind;
uint32_t page_kind_generation;
uint32_t sector_layout;
} NVDriverContext;
typedef struct {
uint32_t width;
uint32_t height;
uint64_t mods;
uint32_t memorySize;
uint32_t offset;
uint32_t pitch;
uint32_t fourcc;
uint32_t log2GobsPerBlockX;
uint32_t log2GobsPerBlockY;
uint32_t log2GobsPerBlockZ;
} NVDriverImage;
bool init_nvdriver(NVDriverContext *context, int drmFd);
bool free_nvdriver(NVDriverContext *context);
bool get_device_uuid(const NVDriverContext *context, char uuid[16]);
bool alloc_memory(const NVDriverContext *context, uint32_t size, int *fd);
bool alloc_buffer(NVDriverContext *context, uint32_t size, const NVDriverImage images[], int *fd1, int *fd2, int *drmFd);
uint32_t calculate_image_size(const NVDriverContext *context, NVDriverImage images[], uint32_t width, uint32_t height, uint32_t bppc, uint32_t numPlanes, const NVFormatPlane planes[]);
#endif
07070100000036000081A4000000000000000000000001663926A700006217000000000000000000000000000000000000002C00000000nvidia-vaapi-driver-0.0.12/src/export-buf.c#include "vabackend.h"
#include "backend-common.h"
#include <stdio.h>
#include <ffnvcodec/dynlink_loader.h>
#include <EGL/egl.h>
#include <EGL/eglext.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <unistd.h>
#ifdef __linux__
#include <sys/sysmacros.h>
#endif
#include <drm.h>
#include <drm_fourcc.h>
#ifndef EGL_NV_stream_consumer_eglimage
#define EGL_NV_stream_consumer_eglimage 1
#define EGL_STREAM_CONSUMER_IMAGE_NV 0x3373
#define EGL_STREAM_IMAGE_ADD_NV 0x3374
#define EGL_STREAM_IMAGE_REMOVE_NV 0x3375
#define EGL_STREAM_IMAGE_AVAILABLE_NV 0x3376
typedef EGLBoolean (EGLAPIENTRYP PFNEGLSTREAMIMAGECONSUMERCONNECTNVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLint num_modifiers, EGLuint64KHR *modifiers, EGLAttrib *attrib_list);
typedef EGLint (EGLAPIENTRYP PFNEGLQUERYSTREAMCONSUMEREVENTNVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLTime timeout, EGLenum *event, EGLAttrib *aux);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLSTREAMACQUIREIMAGENVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLImage *pImage, EGLSync sync);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLSTREAMRELEASEIMAGENVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLImage image, EGLSync sync);
#ifdef EGL_EGLEXT_PROTOTYPES
EGLAPI EGLBoolean EGLAPIENTRY eglStreamImageConsumerConnectNV (EGLDisplay dpy, EGLStreamKHR stream, EGLint num_modifiers, EGLuint64KHR *modifiers, EGLAttrib *attrib_list);
EGLAPI EGLint EGLAPIENTRY eglQueryStreamConsumerEventNV (EGLDisplay dpy, EGLStreamKHR stream, EGLTime timeout, EGLenum *event, EGLAttrib *aux);
EGLAPI EGLBoolean EGLAPIENTRY eglStreamAcquireImageNV (EGLDisplay dpy, EGLStreamKHR stream, EGLImage *pImage, EGLSync sync);
EGLAPI EGLBoolean EGLAPIENTRY eglStreamReleaseImageNV (EGLDisplay dpy, EGLStreamKHR stream, EGLImage image, EGLSync sync);
#endif
#endif
#ifndef EGL_EXT_device_drm
#define EGL_DRM_MASTER_FD_EXT 0x333C
#endif
#ifndef EGL_EXT_device_drm_render_node
#define EGL_DRM_RENDER_NODE_FILE_EXT 0x3377
#endif
#ifndef EGL_NV_stream_reset
#define EGL_SUPPORT_REUSE_NV 0x3335
#endif
static PFNEGLQUERYSTREAMCONSUMEREVENTNVPROC eglQueryStreamConsumerEventNV;
static PFNEGLSTREAMRELEASEIMAGENVPROC eglStreamReleaseImageNV;
static PFNEGLSTREAMACQUIREIMAGENVPROC eglStreamAcquireImageNV;
static PFNEGLEXPORTDMABUFIMAGEMESAPROC eglExportDMABUFImageMESA;
static PFNEGLEXPORTDMABUFIMAGEQUERYMESAPROC eglExportDMABUFImageQueryMESA;
static PFNEGLCREATESTREAMKHRPROC eglCreateStreamKHR;
static PFNEGLDESTROYSTREAMKHRPROC eglDestroyStreamKHR;
static PFNEGLSTREAMIMAGECONSUMERCONNECTNVPROC eglStreamImageConsumerConnectNV;
static void debug(EGLenum error,const char *command,EGLint messageType,EGLLabelKHR threadLabel,EGLLabelKHR objectLabel,const char* message) {
LOG("[EGL] %s: %s", command, message);
}
static void egl_releaseExporter(NVDriver *drv) {
//TODO not sure if this is still needed as we don't return anything now
LOG("Releasing exporter, %d outstanding frames", drv->numFramesPresented);
while (true) {
CUeglFrame eglframe;
CUresult cuStatus = drv->cu->cuEGLStreamProducerReturnFrame(&drv->cuStreamConnection, &eglframe, NULL);
if (cuStatus == CUDA_SUCCESS) {
drv->numFramesPresented--;
for (int i = 0; i < 3; i++) {
if (eglframe.frame.pArray[i] != NULL) {
LOG("Cleaning up CUDA array %p (%d outstanding)", eglframe.frame.pArray[i], drv->numFramesPresented);
drv->cu->cuArrayDestroy(eglframe.frame.pArray[i]);
eglframe.frame.pArray[i] = NULL;
}
}
} else {
break;
}
}
LOG("Done releasing frames");
if (drv->cuStreamConnection != NULL) {
drv->cu->cuEGLStreamProducerDisconnect(&drv->cuStreamConnection);
}
if (drv->eglDisplay != EGL_NO_DISPLAY) {
if (drv->eglStream != EGL_NO_STREAM_KHR) {
eglDestroyStreamKHR(drv->eglDisplay, drv->eglStream);
drv->eglStream = EGL_NO_STREAM_KHR;
}
//TODO terminate the EGLDisplay here?, sounds like that could break stuff
drv->eglDisplay = EGL_NO_DISPLAY;
}
}
static bool reconnect(NVDriver *drv) {
LOG("Reconnecting to stream");
eglInitialize(drv->eglDisplay, NULL, NULL);
if (drv->cuStreamConnection != NULL) {
CHECK_CUDA_RESULT_RETURN(drv->cu->cuEGLStreamProducerDisconnect(&drv->cuStreamConnection), false);
}
if (drv->eglStream != EGL_NO_STREAM_KHR) {
eglDestroyStreamKHR(drv->eglDisplay, drv->eglStream);
}
drv->numFramesPresented = 0;
//tell the driver we don't want it to reuse any EGLImages
EGLint stream_attrib_list[] = { EGL_SUPPORT_REUSE_NV, EGL_FALSE, EGL_NONE };
drv->eglStream = eglCreateStreamKHR(drv->eglDisplay, stream_attrib_list);
if (drv->eglStream == EGL_NO_STREAM_KHR) {
LOG("Unable to create EGLStream");
return false;
}
if (!eglStreamImageConsumerConnectNV(drv->eglDisplay, drv->eglStream, 0, 0, NULL)) {
LOG("Unable to connect EGLImage stream consumer");
return false;
}
CHECK_CUDA_RESULT_RETURN(drv->cu->cuEGLStreamProducerConnect(&drv->cuStreamConnection, drv->eglStream, 0, 0), false);
return true;
}
static void findGPUIndexFromFd(NVDriver *drv) {
struct stat buf;
int drmDeviceIndex;
PFNEGLQUERYDEVICESEXTPROC eglQueryDevicesEXT = (PFNEGLQUERYDEVICESEXTPROC) eglGetProcAddress("eglQueryDevicesEXT");
PFNEGLQUERYDEVICEATTRIBEXTPROC eglQueryDeviceAttribEXT = (PFNEGLQUERYDEVICEATTRIBEXTPROC) eglGetProcAddress("eglQueryDeviceAttribEXT");
PFNEGLQUERYDEVICESTRINGEXTPROC eglQueryDeviceStringEXT = (PFNEGLQUERYDEVICESTRINGEXTPROC) eglGetProcAddress("eglQueryDeviceStringEXT");
if (eglQueryDevicesEXT == NULL || eglQueryDeviceAttribEXT == NULL) {
LOG("No support for EGL_EXT_device_enumeration");
drv->cudaGpuId = 0;
return;
} else if (drv->cudaGpuId == -1 && drv->drmFd == -1) {
//there's no point scanning here as we don't have anything to match, just return GPU ID 0
LOG("Defaulting to CUDA GPU ID 0. Use NVD_GPU to select a specific CUDA GPU");
drv->cudaGpuId = 0;
}
//work out how we're searching for the GPU
if (drv->cudaGpuId == -1 && drv->drmFd != -1) {
//figure out the 'drm device index', basically the minor number of the device node & 0x7f
//since we don't know/want to care if we're dealing with a master or render node
if (!isNvidiaDrmFd(drv->drmFd, true) || !checkModesetParameterFromFd(drv->drmFd)) {
return;
}
fstat(drv->drmFd, &buf);
drmDeviceIndex = minor(buf.st_rdev);
LOG("Looking for DRM device index: %d", drmDeviceIndex);
} else {
LOG("Looking for GPU index: %d", drv->cudaGpuId);
}
//go grab some EGL devices
EGLDeviceEXT devices[8];
EGLint num_devices;
if(!eglQueryDevicesEXT(8, devices, &num_devices)) {
LOG("Unable to query EGL devices");
drv->cudaGpuId = 0;
return;
}
LOG("Found %d EGL devices", num_devices);
for (int i = 0; i < num_devices; i++) {
EGLAttrib attr = -1;
//retrieve the DRM device path for this EGLDevice
const char* drmRenderNodeFile = eglQueryDeviceStringEXT(devices[i], EGL_DRM_RENDER_NODE_FILE_EXT);
if (drmRenderNodeFile != NULL) {
//if we have one, try and get the CUDA device id
if (eglQueryDeviceAttribEXT(devices[i], EGL_CUDA_DEVICE_NV, &attr)) {
LOG("Got EGL_CUDA_DEVICE_NV value '%d' for EGLDevice %d", attr, i);
//if we're looking for a matching drm device index check it here
if (drv->cudaGpuId == -1 && drv->drmFd != -1) {
stat(drmRenderNodeFile, &buf);
int foundDrmDeviceIndex = minor(buf.st_rdev);
LOG("Found drmDeviceIndex: %d", foundDrmDeviceIndex);
if (foundDrmDeviceIndex != drmDeviceIndex) {
continue;
}
} else if (drv->cudaGpuId != attr) {
//LOG("Not selected device, skipping");
continue;
}
//if it's the device we're looking for, check the modeset parameter on it.
bool checkModeset = checkModesetParameterFromFd(drv->drmFd);
if (!checkModeset) {
continue;
}
LOG("Selecting EGLDevice %d", i);
drv->eglDevice = devices[i];
drv->cudaGpuId = attr;
return;
} else {
LOG("No EGL_CUDA_DEVICE_NV support for EGLDevice %d", i);
}
} else {
LOG("No DRM device file for EGLDevice %d", i);
}
}
LOG("No match found, falling back to default device");
drv->cudaGpuId = 0;
}
static bool egl_initExporter(NVDriver *drv) {
findGPUIndexFromFd(drv);
//if we didn't find an EGLDevice, then exit now
if (drv->eglDevice == NULL) {
return false;
}
static const EGLAttrib debugAttribs[] = {EGL_DEBUG_MSG_WARN_KHR, EGL_TRUE, EGL_DEBUG_MSG_INFO_KHR, EGL_TRUE, EGL_NONE};
eglQueryStreamConsumerEventNV = (PFNEGLQUERYSTREAMCONSUMEREVENTNVPROC) eglGetProcAddress("eglQueryStreamConsumerEventNV");
eglStreamReleaseImageNV = (PFNEGLSTREAMRELEASEIMAGENVPROC) eglGetProcAddress("eglStreamReleaseImageNV");
eglStreamAcquireImageNV = (PFNEGLSTREAMACQUIREIMAGENVPROC) eglGetProcAddress("eglStreamAcquireImageNV");
eglExportDMABUFImageMESA = (PFNEGLEXPORTDMABUFIMAGEMESAPROC) eglGetProcAddress("eglExportDMABUFImageMESA");
eglExportDMABUFImageQueryMESA = (PFNEGLEXPORTDMABUFIMAGEQUERYMESAPROC) eglGetProcAddress("eglExportDMABUFImageQueryMESA");
eglCreateStreamKHR = (PFNEGLCREATESTREAMKHRPROC) eglGetProcAddress("eglCreateStreamKHR");
eglDestroyStreamKHR = (PFNEGLDESTROYSTREAMKHRPROC) eglGetProcAddress("eglDestroyStreamKHR");
eglStreamImageConsumerConnectNV = (PFNEGLSTREAMIMAGECONSUMERCONNECTNVPROC) eglGetProcAddress("eglStreamImageConsumerConnectNV");
PFNEGLQUERYDMABUFFORMATSEXTPROC eglQueryDmaBufFormatsEXT = (PFNEGLQUERYDMABUFFORMATSEXTPROC) eglGetProcAddress("eglQueryDmaBufFormatsEXT");
PFNEGLDEBUGMESSAGECONTROLKHRPROC eglDebugMessageControlKHR = (PFNEGLDEBUGMESSAGECONTROLKHRPROC) eglGetProcAddress("eglDebugMessageControlKHR");
drv->eglDisplay = eglGetPlatformDisplay(EGL_PLATFORM_DEVICE_EXT, (EGLDeviceEXT) drv->eglDevice, NULL);
if (drv->eglDisplay == NULL) {
LOG("Falling back to using default EGLDisplay");
drv->eglDisplay = eglGetDisplay(NULL);
}
if (drv->eglDisplay == NULL) {
return false;
}
if (!eglInitialize(drv->eglDisplay, NULL, NULL)) {
LOG("Unable to initialise EGL for display: %p", drv->eglDisplay);
return false;
}
//setup debug logging
eglDebugMessageControlKHR(debug, debugAttribs);
//see if the driver supports 16-bit exports
EGLint formats[64];
EGLint formatCount;
if (eglQueryDmaBufFormatsEXT(drv->eglDisplay, 64, formats, &formatCount)) {
bool r16 = false, rg1616 = false;
for (int i = 0; i < formatCount; i++) {
if (formats[i] == DRM_FORMAT_R16) {
r16 = true;
} else if (formats[i] == DRM_FORMAT_RG1616) {
rg1616 = true;
}
}
drv->supports16BitSurface = r16 & rg1616;
drv->supports444Surface = false;
if (drv->supports16BitSurface) {
LOG("Driver supports 16-bit surfaces");
} else {
LOG("Driver doesn't support 16-bit surfaces");
}
}
return true;
}
static bool exportBackingImage(NVDriver *drv, BackingImage *img) {
int planes = 0;
if (!eglExportDMABUFImageQueryMESA(drv->eglDisplay, img->image, &img->fourcc, &planes, img->mods)) {
LOG("eglExportDMABUFImageQueryMESA failed");
return false;
}
LOG("eglExportDMABUFImageQueryMESA: %p %.4s (%x) planes:%d mods:%lx %lx", img, (char*)&img->fourcc, img->fourcc, planes, img->mods[0], img->mods[1]);
EGLBoolean r = eglExportDMABUFImageMESA(drv->eglDisplay, img->image, img->fds, img->strides, img->offsets);
//LOG("Offset/Pitch: %d %d %d %d", surface->offsets[0], surface->offsets[1], surface->strides[0], surface->strides[1]);
if (!r) {
LOG("Unable to export image");
return false;
}
return true;
}
static BackingImage* createBackingImage(NVDriver *drv, uint32_t width, uint32_t height, EGLImage image, CUarray arrays[]) {
BackingImage* img = (BackingImage*) calloc(1, sizeof(BackingImage));
img->image = image;
img->arrays[0] = arrays[0];
img->arrays[1] = arrays[1];
img->width = width;
img->height = height;
if (!exportBackingImage(drv, img)) {
LOG("Unable to export Backing Image");
free(img);
return NULL;
}
return img;
}
static bool egl_destroyBackingImage(NVDriver *drv, BackingImage *img) {
//if we're attached to a surface, update the surface to remove us
if (img->surface != NULL) {
img->surface->backingImage = NULL;
}
LOG("Destroying BackingImage: %p", img);
for (int i = 0; i < 4; i++) {
if (img->fds[i] != 0) {
close(img->fds[i]);
}
}
//eglStreamReleaseImageNV(drv->eglDisplay, drv->eglStream, surface->eglImage, EGL_NO_SYNC);
//destroy them rather than releasing them
eglDestroyImage(drv->eglDisplay, img->image);
CHECK_CUDA_RESULT_RETURN(drv->cu->cuArrayDestroy(img->arrays[0]), false);
CHECK_CUDA_RESULT_RETURN(drv->cu->cuArrayDestroy(img->arrays[1]), false);
img->arrays[0] = NULL;
img->arrays[1] = NULL;
free(img);
return true;
}
static void egl_attachBackingImageToSurface(NVSurface *surface, BackingImage *img) {
surface->backingImage = img;
img->surface = surface;
}
static void egl_detachBackingImageFromSurface(NVDriver *drv, NVSurface *surface) {
if (surface->backingImage == NULL) {
LOG("Cannot detach NULL BackingImage from Surface");
return;
}
if (surface->backingImage->fourcc == DRM_FORMAT_NV21) {
if (!egl_destroyBackingImage(drv, surface->backingImage)) {
LOG("Unable to destory backing image");
}
} else {
pthread_mutex_lock(&drv->imagesMutex);
ARRAY_FOR_EACH(BackingImage*, img, &drv->images)
//find the entry for this surface
if (img->surface == surface) {
LOG("Detaching BackingImage %p from Surface %p", img, surface);
img->surface = NULL;
break;
}
}
pthread_mutex_unlock(&drv->imagesMutex);
}
surface->backingImage = NULL;
}
static void egl_destroyAllBackingImage(NVDriver *drv) {
pthread_mutex_lock(&drv->imagesMutex);
ARRAY_FOR_EACH_REV(BackingImage*, it, &drv->images)
egl_destroyBackingImage(drv, it);
remove_element_at(&drv->images, it_idx);
END_FOR_EACH
pthread_mutex_unlock(&drv->imagesMutex);
}
static BackingImage* findFreeBackingImage(NVDriver *drv, NVSurface *surface) {
BackingImage *ret = NULL;
pthread_mutex_lock(&drv->imagesMutex);
//look through the free'd surfaces and see if we can reuse one
ARRAY_FOR_EACH(BackingImage*, img, &drv->images)
if (img->surface == NULL && img->width == surface->width && img->height == surface->height) {
LOG("Using BackingImage %p for Surface %p", img, surface);
egl_attachBackingImageToSurface(surface, img);
ret = img;
break;
}
END_FOR_EACH
pthread_mutex_unlock(&drv->imagesMutex);
return ret;
}
static BackingImage *egl_allocateBackingImage(NVDriver *drv, const NVSurface *surface) {
CUeglFrame eglframe = {
.width = surface->width,
.height = surface->height,
.depth = 1,
.pitch = 0,
.planeCount = 2,
.numChannels = 1,
.frameType = CU_EGL_FRAME_TYPE_ARRAY,
};
if (surface->format == cudaVideoSurfaceFormat_NV12) {
eglframe.eglColorFormat = drv->useCorrectNV12Format ? CU_EGL_COLOR_FORMAT_YUV420_SEMIPLANAR :
CU_EGL_COLOR_FORMAT_YVU420_SEMIPLANAR;
eglframe.cuFormat = CU_AD_FORMAT_UNSIGNED_INT8;
} else if (surface->format == cudaVideoSurfaceFormat_P016) {
if (surface->bitDepth == 10) {
eglframe.eglColorFormat = CU_EGL_COLOR_FORMAT_Y10V10U10_420_SEMIPLANAR;
} else if (surface->bitDepth == 12) {
// Logically, we should use the explicit 12bit format here, but it fails
// to export to a dmabuf if we do. In practice, that should be fine as the
// data is still stored in 16 bits and they (surely?) aren't going to
// zero out the extra bits.
// eglframe.eglColorFormat = CU_EGL_COLOR_FORMAT_Y12V12U12_420_SEMIPLANAR;
eglframe.eglColorFormat = CU_EGL_COLOR_FORMAT_Y10V10U10_420_SEMIPLANAR;
} else {
LOG("Unknown bitdepth");
}
eglframe.cuFormat = CU_AD_FORMAT_UNSIGNED_INT16;
}
CUDA_ARRAY3D_DESCRIPTOR arrDesc = {
.Width = eglframe.width,
.Height = eglframe.height,
.Depth = 0,
.NumChannels = 1,
.Flags = 0,
.Format = eglframe.cuFormat
};
CUDA_ARRAY3D_DESCRIPTOR arr2Desc = {
.Width = eglframe.width >> 1,
.Height = eglframe.height >> 1,
.Depth = 0,
.NumChannels = 2,
.Flags = 0,
.Format = eglframe.cuFormat
};
CHECK_CUDA_RESULT_RETURN(drv->cu->cuArray3DCreate(&eglframe.frame.pArray[0], &arrDesc), NULL);
CHECK_CUDA_RESULT_RETURN(drv->cu->cuArray3DCreate(&eglframe.frame.pArray[1], &arr2Desc), NULL);
pthread_mutex_lock(&drv->exportMutex);
LOG("Presenting frame %d %dx%d (%p, %p, %p)", surface->pictureIdx, eglframe.width, eglframe.height, surface, eglframe.frame.pArray[0], eglframe.frame.pArray[1]);
if (CHECK_CUDA_RESULT(drv->cu->cuEGLStreamProducerPresentFrame( &drv->cuStreamConnection, eglframe, NULL))) {
//if we got an error here, try to reconnect to the EGLStream
if (!reconnect(drv) ||
CHECK_CUDA_RESULT(drv->cu->cuEGLStreamProducerPresentFrame( &drv->cuStreamConnection, eglframe, NULL))) {
pthread_mutex_unlock(&drv->exportMutex);
return NULL;
}
}
BackingImage *ret = NULL;
while (1) {
EGLenum event = 0;
EGLAttrib aux = 0;
//check for the next event
if (eglQueryStreamConsumerEventNV(drv->eglDisplay, drv->eglStream, 0, &event, &aux) != EGL_TRUE) {
break;
}
if (event == EGL_STREAM_IMAGE_ADD_NV) {
EGLImage image = eglCreateImage(drv->eglDisplay, EGL_NO_CONTEXT, EGL_STREAM_CONSUMER_IMAGE_NV, drv->eglStream, NULL);
LOG("Adding frame from EGLStream: %p", image);
} else if (event == EGL_STREAM_IMAGE_REMOVE_NV) {
//Not sure if this is ever called
eglDestroyImage(drv->eglDisplay, (EGLImage) aux);
LOG("Removing frame from EGLStream: %p", aux);
} else if (event == EGL_STREAM_IMAGE_AVAILABLE_NV) {
EGLImage img;
if (!eglStreamAcquireImageNV(drv->eglDisplay, drv->eglStream, &img, EGL_NO_SYNC_NV)) {
LOG("eglStreamAcquireImageNV failed");
break;
}
LOG("Acquired image from EGLStream: %p", img);
ret = createBackingImage(drv, surface->width, surface->height, img, eglframe.frame.pArray);
} else {
LOG("Unhandled event: %X", event);
}
}
pthread_mutex_unlock(&drv->exportMutex);
return ret;
}
static bool copyFrameToSurface(NVDriver *drv, CUdeviceptr ptr, NVSurface *surface, uint32_t pitch) {
int bpp = surface->format == cudaVideoSurfaceFormat_NV12 ? 1 : 2;
CUDA_MEMCPY2D cpy = {
.srcMemoryType = CU_MEMORYTYPE_DEVICE,
.srcDevice = ptr,
.srcPitch = pitch,
.dstMemoryType = CU_MEMORYTYPE_ARRAY,
.dstArray = surface->backingImage->arrays[0],
.Height = surface->height,
.WidthInBytes = surface->width * bpp
};
CHECK_CUDA_RESULT_RETURN(drv->cu->cuMemcpy2DAsync(&cpy, 0), false);
CUDA_MEMCPY2D cpy2 = {
.srcMemoryType = CU_MEMORYTYPE_DEVICE,
.srcDevice = ptr,
.srcY = surface->height,
.srcPitch = pitch,
.dstMemoryType = CU_MEMORYTYPE_ARRAY,
.dstArray = surface->backingImage->arrays[1],
.Height = surface->height >> 1,
.WidthInBytes = surface->width * bpp
};
CHECK_CUDA_RESULT_RETURN(drv->cu->cuMemcpy2D(&cpy2), false);
//notify anyone waiting for us to be resolved
pthread_mutex_lock(&surface->mutex);
surface->resolving = 0;
pthread_cond_signal(&surface->cond);
pthread_mutex_unlock(&surface->mutex);
return true;
}
static bool egl_realiseSurface(NVDriver *drv, NVSurface *surface) {
//make sure we're the only thread updating this surface
pthread_mutex_lock(&surface->mutex);
//check again to see if it's just been created
if (surface->backingImage == NULL) {
//try to find a free surface
BackingImage *img = findFreeBackingImage(drv, surface);
//if we can't find a free backing image...
if (img == NULL) {
LOG("No free surfaces found");
//...allocate one
img = egl_allocateBackingImage(drv, surface);
if (img == NULL) {
LOG("Unable to realise surface: %p (%d)", surface, surface->pictureIdx)
pthread_mutex_unlock(&surface->mutex);
return false;
}
if (img->fourcc == DRM_FORMAT_NV21) {
LOG("Detected NV12/NV21 NVIDIA driver bug, attempting to work around");
//free the old surface to prevent leaking them
if (!egl_destroyBackingImage(drv, img)) {
LOG("Unable to destroy backing image");
}
//this is a caused by a bug in old versions the driver that was fixed in the 510 series
drv->useCorrectNV12Format = !drv->useCorrectNV12Format;
//re-export the frame in the correct format
img = egl_allocateBackingImage(drv, surface);
if (img->fourcc != DRM_FORMAT_NV12) {
LOG("Work around unsuccessful");
}
}
egl_attachBackingImageToSurface(surface, img);
//add our newly created BackingImage to the list
pthread_mutex_lock(&drv->imagesMutex);
add_element(&drv->images, img);
pthread_mutex_unlock(&drv->imagesMutex);
}
}
pthread_mutex_unlock(&surface->mutex);
return true;
}
static bool egl_exportCudaPtr(NVDriver *drv, CUdeviceptr ptr, NVSurface *surface, uint32_t pitch) {
if (!egl_realiseSurface(drv, surface)) {
return false;
}
if (ptr != 0 && !copyFrameToSurface(drv, ptr, surface, pitch)) {
LOG("Unable to update surface from frame");
return false;
} else if (ptr == 0) {
LOG("exporting with null ptr");
}
return true;
}
static bool egl_fillExportDescriptor(NVDriver *drv, NVSurface *surface, VADRMPRIMESurfaceDescriptor *desc) {
BackingImage *img = surface->backingImage;
int bpp = img->fourcc == DRM_FORMAT_NV12 ? 1 : 2;
//TODO only support 420 images (either NV12, P010 or P012)
desc->fourcc = img->fourcc;
desc->width = img->width;
desc->height = img->height;
desc->num_layers = 2;
desc->num_objects = 2;
desc->objects[0].fd = dup(img->fds[0]);
desc->objects[0].size = img->width * img->height * bpp;
desc->objects[0].drm_format_modifier = img->mods[0];
desc->objects[1].fd = dup(img->fds[1]);
desc->objects[1].size = img->width * (img->height >> 1) * bpp;
desc->objects[1].drm_format_modifier = img->mods[1];
desc->layers[0].drm_format = img->fourcc == DRM_FORMAT_NV12 ? DRM_FORMAT_R8 : DRM_FORMAT_R16;
desc->layers[0].num_planes = 1;
desc->layers[0].object_index[0] = 0;
desc->layers[0].offset[0] = img->offsets[0];
desc->layers[0].pitch[0] = img->strides[0];
desc->layers[1].drm_format = img->fourcc == DRM_FORMAT_NV12 ? DRM_FORMAT_RG88 : DRM_FORMAT_RG1616;
desc->layers[1].num_planes = 1;
desc->layers[1].object_index[0] = 1;
desc->layers[1].offset[0] = img->offsets[1];
desc->layers[1].pitch[0] = img->strides[1];
return true;
}
const NVBackend EGL_BACKEND = {
.name = "egl",
.initExporter = egl_initExporter,
.releaseExporter = egl_releaseExporter,
.exportCudaPtr = egl_exportCudaPtr,
.detachBackingImageFromSurface = egl_detachBackingImageFromSurface,
.realiseSurface = egl_realiseSurface,
.fillExportDescriptor = egl_fillExportDescriptor,
.destroyAllBackingImage = egl_destroyAllBackingImage
};
07070100000037000081A4000000000000000000000001663926A700001DE1000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/src/h264.c#include "vabackend.h"
#include <string.h>
static void copyH264PicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VAPictureParameterBufferH264* buf = (VAPictureParameterBufferH264*) buffer->ptr;
picParams->PicWidthInMbs = buf->picture_width_in_mbs_minus1 + 1; //int
picParams->FrameHeightInMbs = buf->picture_height_in_mbs_minus1 + 1; //int
ctx->renderTarget->progressiveFrame = !buf->pic_fields.bits.field_pic_flag;
picParams->field_pic_flag = buf->pic_fields.bits.field_pic_flag;
picParams->bottom_field_flag = (buf->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) != 0;
picParams->second_field = (buf->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD) != 0 && (buf->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD) != 0;
picParams->ref_pic_flag = buf->pic_fields.bits.reference_pic_flag;
picParams->intra_pic_flag = 1; //this is set to 0 in copyH264SliceParam
picParams->CodecSpecific.h264.log2_max_frame_num_minus4 = buf->seq_fields.bits.log2_max_frame_num_minus4;
picParams->CodecSpecific.h264.pic_order_cnt_type = buf->seq_fields.bits.pic_order_cnt_type;
picParams->CodecSpecific.h264.log2_max_pic_order_cnt_lsb_minus4 = buf->seq_fields.bits.log2_max_pic_order_cnt_lsb_minus4;
picParams->CodecSpecific.h264.delta_pic_order_always_zero_flag = buf->seq_fields.bits.delta_pic_order_always_zero_flag;
picParams->CodecSpecific.h264.frame_mbs_only_flag = buf->seq_fields.bits.frame_mbs_only_flag;
picParams->CodecSpecific.h264.direct_8x8_inference_flag = buf->seq_fields.bits.direct_8x8_inference_flag;
picParams->CodecSpecific.h264.num_ref_frames = buf->num_ref_frames;
picParams->CodecSpecific.h264.residual_colour_transform_flag = buf->seq_fields.bits.residual_colour_transform_flag;
picParams->CodecSpecific.h264.bit_depth_luma_minus8 = buf->bit_depth_luma_minus8;
picParams->CodecSpecific.h264.bit_depth_chroma_minus8 = buf->bit_depth_chroma_minus8;
picParams->CodecSpecific.h264.entropy_coding_mode_flag = buf->pic_fields.bits.entropy_coding_mode_flag;
picParams->CodecSpecific.h264.pic_order_present_flag = buf->pic_fields.bits.pic_order_present_flag;
picParams->CodecSpecific.h264.weighted_pred_flag = buf->pic_fields.bits.weighted_pred_flag;
picParams->CodecSpecific.h264.weighted_bipred_idc = buf->pic_fields.bits.weighted_bipred_idc;
picParams->CodecSpecific.h264.pic_init_qp_minus26 = buf->pic_init_qp_minus26;
picParams->CodecSpecific.h264.deblocking_filter_control_present_flag = buf->pic_fields.bits.deblocking_filter_control_present_flag;
picParams->CodecSpecific.h264.redundant_pic_cnt_present_flag = buf->pic_fields.bits.redundant_pic_cnt_present_flag;
picParams->CodecSpecific.h264.transform_8x8_mode_flag = buf->pic_fields.bits.transform_8x8_mode_flag;
picParams->CodecSpecific.h264.MbaffFrameFlag = buf->seq_fields.bits.mb_adaptive_frame_field_flag && !picParams->field_pic_flag;
picParams->CodecSpecific.h264.constrained_intra_pred_flag = buf->pic_fields.bits.constrained_intra_pred_flag;
picParams->CodecSpecific.h264.chroma_qp_index_offset = buf->chroma_qp_index_offset;
picParams->CodecSpecific.h264.second_chroma_qp_index_offset = buf->second_chroma_qp_index_offset;
picParams->CodecSpecific.h264.ref_pic_flag = buf->pic_fields.bits.reference_pic_flag;
picParams->CodecSpecific.h264.frame_num = buf->frame_num;
picParams->CodecSpecific.h264.CurrFieldOrderCnt[0] = buf->CurrPic.TopFieldOrderCnt;
picParams->CodecSpecific.h264.CurrFieldOrderCnt[1] = buf->CurrPic.BottomFieldOrderCnt;
for (int i = 0; i < 16; i++) {
if (!(buf->ReferenceFrames[i].flags & VA_PICTURE_H264_INVALID)) {
picParams->CodecSpecific.h264.dpb[i].PicIdx = pictureIdxFromSurfaceId(ctx->drv, buf->ReferenceFrames[i].picture_id);
picParams->CodecSpecific.h264.dpb[i].FrameIdx = buf->ReferenceFrames[i].frame_idx;
picParams->CodecSpecific.h264.dpb[i].FieldOrderCnt[0] = buf->ReferenceFrames[i].TopFieldOrderCnt;
picParams->CodecSpecific.h264.dpb[i].FieldOrderCnt[1] = buf->ReferenceFrames[i].BottomFieldOrderCnt;
picParams->CodecSpecific.h264.dpb[i].is_long_term = (buf->ReferenceFrames[i].flags & VA_PICTURE_H264_LONG_TERM_REFERENCE) != 0;
picParams->CodecSpecific.h264.dpb[i].not_existing = 0;
int tmp = 0;
if ((buf->ReferenceFrames[i].flags & VA_PICTURE_H264_TOP_FIELD) != 0) tmp |= 1;
if ((buf->ReferenceFrames[i].flags & VA_PICTURE_H264_BOTTOM_FIELD) != 0) tmp |= 2;
if (tmp == 0) {
tmp = 3; //TODO seems to look better with a hardcoded 3
}
picParams->CodecSpecific.h264.dpb[i].used_for_reference = tmp;
} else {
picParams->CodecSpecific.h264.dpb[i].PicIdx = -1;
}
}
}
static void copyH264SliceParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VASliceParameterBufferH264* buf = (VASliceParameterBufferH264*) buffer->ptr;
picParams->CodecSpecific.h264.num_ref_idx_l0_active_minus1 = buf->num_ref_idx_l0_active_minus1;
picParams->CodecSpecific.h264.num_ref_idx_l1_active_minus1 = buf->num_ref_idx_l1_active_minus1;
if (buf->slice_type != 2 && buf->slice_type != 4) { // != I && != SI
picParams->intra_pic_flag = 0;
}
ctx->lastSliceParams = buffer->ptr;
ctx->lastSliceParamsCount = buffer->elements;
picParams->nNumSlices += buffer->elements;
}
static void copyH264SliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
static const uint8_t header[] = { 0, 0, 1 }; //1 as a 24-bit Big Endian
VASliceParameterBufferH264 *sliceParams = &((VASliceParameterBufferH264*) ctx->lastSliceParams)[i];
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, header, sizeof(header));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
picParams->nBitstreamDataLen += sliceParams->slice_data_size + 3;
}
}
static void copyH264IQMatrix(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
VAIQMatrixBufferH264 *iq = (VAIQMatrixBufferH264*) buf->ptr;
memcpy(picParams->CodecSpecific.h264.WeightScale4x4, iq->ScalingList4x4, sizeof(iq->ScalingList4x4));
memcpy(picParams->CodecSpecific.h264.WeightScale8x8, iq->ScalingList8x8, sizeof(iq->ScalingList8x8));
}
static cudaVideoCodec computeH264CudaCodec(VAProfile profile) {
//cudaVideoCodec_H264_SVC missing in VA-API?
if (profile == VAProfileH264ConstrainedBaseline || profile == VAProfileH264Main || profile == VAProfileH264High) {
return cudaVideoCodec_H264;
}
//if (profile == VAProfileH264StereoHigh || profile == VAProfileH264MultiviewHigh) {
// return cudaVideoCodec_H264_MVC;
//}
return cudaVideoCodec_NONE;
}
static const VAProfile h264SupportedProfiles[] = {
VAProfileH264ConstrainedBaseline,
VAProfileH264Main,
VAProfileH264High,
};
const DECLARE_CODEC(h264Codec) = {
.computeCudaCodec = computeH264CudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyH264PicParam,
[VAIQMatrixBufferType] = copyH264IQMatrix,
[VASliceParameterBufferType] = copyH264SliceParam,
[VASliceDataBufferType] = copyH264SliceData,
},
.supportedProfileCount = ARRAY_SIZE(h264SupportedProfiles),
.supportedProfiles = h264SupportedProfiles,
};
07070100000038000081A4000000000000000000000001663926A700003BB0000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/src/hevc.c#define _GNU_SOURCE
#include "vabackend.h"
#include <stdlib.h>
#if !defined(__GLIBC__)
typedef int (*__compar_d_fn_t) (const void *, const void *, void *);
#if defined(__FreeBSD__) && __FreeBSD__ < 14
// https://github.com/freebsd/freebsd-src/commit/af3c78886fd8
typedef int (*__old_compar_d_fn_t) (void *, const void *, const void *);
#define qsort_r(base, nmemb, size, compar, thunk) \
qsort_r(base, nmemb, size, thunk, (__old_compar_d_fn_t)compar)
#endif
#endif
static const uint8_t ff_hevc_diag_scan4x4_x[16] = {
0, 0, 1, 0,
1, 2, 0, 1,
2, 3, 1, 2,
3, 2, 3, 3,
};
static const uint8_t ff_hevc_diag_scan4x4_y[16] = {
0, 1, 0, 2,
1, 0, 3, 2,
1, 0, 3, 2,
1, 3, 2, 3,
};
static const uint8_t ff_hevc_diag_scan8x8_x[64] = {
0, 0, 1, 0,
1, 2, 0, 1,
2, 3, 0, 1,
2, 3, 4, 0,
1, 2, 3, 4,
5, 0, 1, 2,
3, 4, 5, 6,
0, 1, 2, 3,
4, 5, 6, 7,
1, 2, 3, 4,
5, 6, 7, 2,
3, 4, 5, 6,
7, 3, 4, 5,
6, 7, 4, 5,
6, 7, 5, 6,
7, 6, 7, 7,
};
static const uint8_t ff_hevc_diag_scan8x8_y[64] = {
0, 1, 0, 2,
1, 0, 3, 2,
1, 0, 4, 3,
2, 1, 0, 5,
4, 3, 2, 1,
0, 6, 5, 4,
3, 2, 1, 0,
7, 6, 5, 4,
3, 2, 1, 0,
7, 6, 5, 4,
3, 2, 1, 7,
6, 5, 4, 3,
2, 7, 6, 5,
4, 3, 7, 6,
5, 4, 7, 6,
5, 7, 6, 7,
};
static int sortFunc(const unsigned char *a, const unsigned char *b, int *POCV) {
return POCV[*a] < POCV[*b] ? -1 : 1;
}
static int sortFuncRev(const unsigned char *a, const unsigned char *b, int *POCV) {
return POCV[*a] < POCV[*b] ? 1 : -1;
}
static void copyHEVCPicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VAPictureParameterBufferHEVC* buf = (VAPictureParameterBufferHEVC*) buffer->ptr;
picParams->PicWidthInMbs = buf->pic_width_in_luma_samples / 16;
picParams->FrameHeightInMbs = buf->pic_height_in_luma_samples / 16;
picParams->field_pic_flag = !!(buf->CurrPic.flags & VA_PICTURE_HEVC_FIELD_PIC);
picParams->bottom_field_flag = !!(buf->CurrPic.flags & VA_PICTURE_HEVC_BOTTOM_FIELD);
picParams->second_field = 0;
ctx->renderTarget->progressiveFrame = !picParams->field_pic_flag;
picParams->ref_pic_flag = 1;
picParams->intra_pic_flag = buf->slice_parsing_fields.bits.IntraPicFlag;
CUVIDHEVCPICPARAMS* ppc = &picParams->CodecSpecific.hevc;
ppc->pic_width_in_luma_samples = buf->pic_width_in_luma_samples;
ppc->pic_height_in_luma_samples = buf->pic_height_in_luma_samples;
ppc->log2_min_luma_coding_block_size_minus3 = buf->log2_min_luma_coding_block_size_minus3;
ppc->log2_diff_max_min_luma_coding_block_size = buf->log2_diff_max_min_luma_coding_block_size;
ppc->log2_min_transform_block_size_minus2 = buf->log2_min_transform_block_size_minus2;
ppc->log2_diff_max_min_transform_block_size = buf->log2_diff_max_min_transform_block_size;
ppc->pcm_enabled_flag = buf->pic_fields.bits.pcm_enabled_flag;
ppc->log2_min_pcm_luma_coding_block_size_minus3 = buf->log2_min_pcm_luma_coding_block_size_minus3; //? set conditionally in va-api
ppc->log2_diff_max_min_pcm_luma_coding_block_size = buf->log2_diff_max_min_pcm_luma_coding_block_size;
ppc->pcm_sample_bit_depth_luma_minus1 = buf->pcm_sample_bit_depth_luma_minus1;
ppc->pcm_sample_bit_depth_chroma_minus1 = buf->pcm_sample_bit_depth_chroma_minus1;
// ppc->log2_max_transform_skip_block_size_minus2 = buf->; //in VAPictureParameterBufferHEVCRext
// ppc->log2_sao_offset_scale_luma = buf->pcm_sample_bit_depth_chroma_minus1;
// ppc->log2_sao_offset_scale_chroma = buf->pcm_sample_bit_depth_chroma_minus1;
// ppc->high_precision_offsets_enabled_flag = buf->pcm_sample_bit_depth_chroma_minus1;
ppc->pcm_loop_filter_disabled_flag = buf->pic_fields.bits.pcm_loop_filter_disabled_flag;
ppc->strong_intra_smoothing_enabled_flag = buf->pic_fields.bits.strong_intra_smoothing_enabled_flag;
ppc->max_transform_hierarchy_depth_intra = buf->max_transform_hierarchy_depth_intra;
ppc->max_transform_hierarchy_depth_inter = buf->max_transform_hierarchy_depth_inter;
ppc->amp_enabled_flag = buf->pic_fields.bits.amp_enabled_flag;
ppc->separate_colour_plane_flag = buf->pic_fields.bits.separate_colour_plane_flag;
ppc->log2_max_pic_order_cnt_lsb_minus4 = buf->log2_max_pic_order_cnt_lsb_minus4;
ppc->num_short_term_ref_pic_sets = buf->num_short_term_ref_pic_sets;
ppc->long_term_ref_pics_present_flag = buf->slice_parsing_fields.bits.long_term_ref_pics_present_flag;
ppc->num_long_term_ref_pics_sps = buf->num_long_term_ref_pic_sps;
ppc->sps_temporal_mvp_enabled_flag = buf->slice_parsing_fields.bits.sps_temporal_mvp_enabled_flag;
ppc->sample_adaptive_offset_enabled_flag = buf->slice_parsing_fields.bits.sample_adaptive_offset_enabled_flag;
ppc->scaling_list_enable_flag = buf->pic_fields.bits.scaling_list_enabled_flag;
ppc->IrapPicFlag = buf->slice_parsing_fields.bits.RapPicFlag;
ppc->IdrPicFlag = buf->slice_parsing_fields.bits.IdrPicFlag;
ppc->bit_depth_luma_minus8 = buf->bit_depth_luma_minus8;
ppc->bit_depth_chroma_minus8 = buf->bit_depth_chroma_minus8;
ppc->pps_beta_offset_div2 = buf->pps_beta_offset_div2;
ppc->pps_tc_offset_div2 = buf->pps_tc_offset_div2;
//This is all Range Extension/Rext stuff
// ppc->sps_range_extension_flag = buf->;
// ppc->transform_skip_rotation_enabled_flag = buf->; in VAPictureParameterBufferHEVCRext
// ppc->transform_skip_context_enabled_flag = buf->slice_parsing_fields.bits.IdrPicFlag;
// ppc->implicit_rdpcm_enabled_flag = buf->slice_parsing_fields.bits.IdrPicFlag;
// ppc->explicit_rdpcm_enabled_flag = buf->slice_parsing_fields.bits.IdrPicFlag;
// ppc->extended_precision_processing_flag = buf->slice_parsing_fields.bits.IdrPicFlag;
// ppc->intra_smoothing_disabled_flag = buf->slice_parsing_fields.bits.IdrPicFlag;
// ppc->persistent_rice_adaptation_enabled_flag = buf->slice_parsing_fields.bits.IdrPicFlag;
// ppc->cabac_bypass_alignment_enabled_flag = buf->slice_parsing_fields.bits.IdrPicFlag;
ppc->dependent_slice_segments_enabled_flag = buf->slice_parsing_fields.bits.dependent_slice_segments_enabled_flag;
ppc->slice_segment_header_extension_present_flag = buf->slice_parsing_fields.bits.slice_segment_header_extension_present_flag;
ppc->sign_data_hiding_enabled_flag = buf->pic_fields.bits.sign_data_hiding_enabled_flag;
ppc->cu_qp_delta_enabled_flag = buf->pic_fields.bits.cu_qp_delta_enabled_flag;
ppc->diff_cu_qp_delta_depth = buf->diff_cu_qp_delta_depth;
ppc->init_qp_minus26 = buf->init_qp_minus26;
ppc->pps_cb_qp_offset = buf->pps_cb_qp_offset;
ppc->pps_cr_qp_offset = buf->pps_cr_qp_offset;
ppc->constrained_intra_pred_flag = buf->pic_fields.bits.constrained_intra_pred_flag;
ppc->weighted_pred_flag = buf->pic_fields.bits.weighted_pred_flag;
ppc->weighted_bipred_flag = buf->pic_fields.bits.weighted_bipred_flag;
ppc->transform_skip_enabled_flag = buf->pic_fields.bits.transform_skip_enabled_flag;
ppc->transquant_bypass_enabled_flag = buf->pic_fields.bits.transquant_bypass_enabled_flag;
ppc->entropy_coding_sync_enabled_flag = buf->pic_fields.bits.entropy_coding_sync_enabled_flag;
ppc->log2_parallel_merge_level_minus2 = buf->log2_parallel_merge_level_minus2;
ppc->num_extra_slice_header_bits = buf->num_extra_slice_header_bits;
ppc->loop_filter_across_tiles_enabled_flag = buf->pic_fields.bits.loop_filter_across_tiles_enabled_flag;
ppc->loop_filter_across_slices_enabled_flag = buf->pic_fields.bits.pps_loop_filter_across_slices_enabled_flag;
ppc->output_flag_present_flag = buf->slice_parsing_fields.bits.output_flag_present_flag;
ppc->num_ref_idx_l0_default_active_minus1 = buf->num_ref_idx_l0_default_active_minus1;
ppc->num_ref_idx_l1_default_active_minus1 = buf->num_ref_idx_l1_default_active_minus1;
ppc->lists_modification_present_flag = buf->slice_parsing_fields.bits.lists_modification_present_flag;
ppc->cabac_init_present_flag = buf->slice_parsing_fields.bits.cabac_init_present_flag;
ppc->pps_slice_chroma_qp_offsets_present_flag = buf->slice_parsing_fields.bits.pps_slice_chroma_qp_offsets_present_flag;
ppc->deblocking_filter_override_enabled_flag = buf->slice_parsing_fields.bits.deblocking_filter_override_enabled_flag;
ppc->pps_deblocking_filter_disabled_flag = buf->slice_parsing_fields.bits.pps_disable_deblocking_filter_flag;
ppc->tiles_enabled_flag = buf->pic_fields.bits.tiles_enabled_flag;
ppc->uniform_spacing_flag = 1;
ppc->num_tile_columns_minus1 = buf->num_tile_columns_minus1;
ppc->num_tile_rows_minus1 = buf->num_tile_rows_minus1;
if (ppc->tiles_enabled_flag) {
//the uniform_spacing_flag isn't directly exposed in VA-API, so look through the columns and rows
//and see if they're all the same, this probably isn't correct
for (int i = 0; i < 19; i++) {
if (buf->column_width_minus1[i] != buf->column_width_minus1[i+1]) {
ppc->uniform_spacing_flag = 0;
break;
}
}
if (ppc->uniform_spacing_flag) {
for (int i = 0; i < 21; i++) {
if (buf->row_height_minus1[i] != buf->row_height_minus1[i+1]) {
ppc->uniform_spacing_flag = 0;
break;
}
}
}
}
//More Range Extension/Rext stuff
// ppc->pps_range_extension_flag = buf->pic_fields.bits.tiles_enabled_flag; //in VAPictureParameterBufferHEVCRext
// ppc->cross_component_prediction_enabled_flag = buf->pic_fields.bits.tiles_enabled_flag;
// ppc->chroma_qp_offset_list_enabled_flag = buf->pic_fields.bits.tiles_enabled_flag;
// ppc->diff_cu_chroma_qp_offset_depth = buf->pic_fields.bits.tiles_enabled_flag;
// ppc->chroma_qp_offset_list_len_minus1 = buf->pic_fields.bits.tiles_enabled_flag;
ppc->NumBitsForShortTermRPSInSlice = buf->st_rps_bits;
ppc->NumDeltaPocsOfRefRpsIdx = 0;//TODO
ppc->NumPocTotalCurr = 0; //this looks to be the amount of reference images...
ppc->NumPocStCurrBefore = 0; //these three are set properly below
ppc->NumPocStCurrAfter = 0;
ppc->NumPocLtCurr = 0;
ppc->CurrPicOrderCntVal = buf->CurrPic.pic_order_cnt;
//TODO can probably be replace with memcpy
for (int i = 0; i <= ppc->num_tile_columns_minus1; i++)
ppc->column_width_minus1[i] = buf->column_width_minus1[i];
for (int i = 0; i <= ppc->num_tile_rows_minus1; i++)
ppc->row_height_minus1[i] = buf->row_height_minus1[i];
//in VAPictureParameterBufferHEVCRext
// for (int i = 0; i <= ppc->chroma_qp_offset_list_len_minus1; i++) {
// ppc->cb_qp_offset_list[i] = buf->cb_qp_offset_list[i];
// ppc->cr_qp_offset_list[i] = buf->cr_qp_offset_list[i];
// }
//double check this
VAPictureHEVC *pic = &buf->CurrPic;
for (int i = 0; i < 16; i++) {
ppc->RefPicIdx[i] = pictureIdxFromSurfaceId(ctx->drv, pic[i].picture_id);
ppc->PicOrderCntVal[i] = pic[i].pic_order_cnt;
ppc->IsLongTerm[i] = i != 0 && (pic[i].flags & VA_PICTURE_HEVC_LONG_TERM_REFERENCE) != 0;
if (i != 0 && ppc->RefPicIdx[i] != -1) {
ppc->NumPocTotalCurr++;
}
if (pic[i].flags & VA_PICTURE_HEVC_RPS_ST_CURR_BEFORE) {
ppc->RefPicSetStCurrBefore[ppc->NumPocStCurrBefore++] = i;
} else if (pic[i].flags & VA_PICTURE_HEVC_RPS_ST_CURR_AFTER) {
ppc->RefPicSetStCurrAfter[ppc->NumPocStCurrAfter++] = i;
} else if (pic[i].flags & VA_PICTURE_HEVC_RPS_LT_CURR) {
ppc->RefPicSetLtCurr[ppc->NumPocLtCurr++] = i;
}
}
//This is required to make sure that the RefPicSetStCurrBefore and RefPicSetStCurrAfter arrays are in the correct order
//VA-API doesn't pass this is, only marking each picture if it's in the arrays.
//I'm not sure this is correct
qsort_r(ppc->RefPicSetStCurrBefore, ppc->NumPocStCurrBefore, sizeof(unsigned char), (__compar_d_fn_t) sortFuncRev, ppc->PicOrderCntVal);
qsort_r(ppc->RefPicSetStCurrAfter, ppc->NumPocStCurrAfter, sizeof(unsigned char), (__compar_d_fn_t) sortFunc, ppc->PicOrderCntVal);
}
static void copyHEVCSliceParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
ctx->lastSliceParams = buffer->ptr;
ctx->lastSliceParamsCount = buffer->elements;
picParams->nNumSlices += buffer->elements;
}
static void copyHEVCSliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
static const uint8_t header[] = { 0, 0, 1 }; //1 as a 24-bit Big Endian
VASliceParameterBufferHEVC *sliceParams = &((VASliceParameterBufferHEVC*) ctx->lastSliceParams)[i];
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, header, sizeof(header));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
picParams->nBitstreamDataLen += sliceParams->slice_data_size + 3;
}
}
static void copyHEVCIQMatrix(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
VAIQMatrixBufferHEVC *iq = (VAIQMatrixBufferHEVC*) buf->ptr;
CUVIDHEVCPICPARAMS* ppc = &picParams->CodecSpecific.hevc;
for (int i = 0; i < 6; i++) {
for (int j = 0; j < 16; j++) {
int pos = 4 * ff_hevc_diag_scan4x4_y[j] + ff_hevc_diag_scan4x4_x[j];
ppc->ScalingList4x4[i][j] = iq->ScalingList4x4[i][pos];
}
for (int j = 0; j < 64; j++) {
int pos = 8 * ff_hevc_diag_scan8x8_y[j] + ff_hevc_diag_scan8x8_x[j];
ppc->ScalingList8x8[i][j] = iq->ScalingList8x8[i][pos];
ppc->ScalingList16x16[i][j] = iq->ScalingList16x16[i][pos];
if (i < 2)
ppc->ScalingList32x32[i][j] = iq->ScalingList32x32[i * 3][pos];
}
ppc->ScalingListDCCoeff16x16[i] = iq->ScalingListDC16x16[i];
if (i < 2)
ppc->ScalingListDCCoeff32x32[i] = iq->ScalingListDC32x32[i * 3];
}
}
static cudaVideoCodec computeHEVCCudaCodec(VAProfile profile) {
switch (profile) {
case VAProfileHEVCMain:
case VAProfileHEVCMain10:
case VAProfileHEVCMain12:
case VAProfileHEVCMain444:
case VAProfileHEVCMain444_10:
case VAProfileHEVCMain444_12:
return cudaVideoCodec_HEVC;
default:
return cudaVideoCodec_NONE;
}
}
static const VAProfile hevcSupportedProfiles[] = {
VAProfileHEVCMain,
VAProfileHEVCMain10,
VAProfileHEVCMain12,
VAProfileHEVCMain444,
VAProfileHEVCMain444_10,
VAProfileHEVCMain444_12,
};
const DECLARE_CODEC(hevcCodec) = {
.computeCudaCodec = computeHEVCCudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyHEVCPicParam,
[VAIQMatrixBufferType] = copyHEVCIQMatrix,
[VASliceParameterBufferType] = copyHEVCSliceParam,
[VASliceDataBufferType] = copyHEVCSliceData,
},
.supportedProfileCount = ARRAY_SIZE(hevcSupportedProfiles),
.supportedProfiles = hevcSupportedProfiles,
};
07070100000039000081A4000000000000000000000001663926A7000008D5000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/src/jpeg.c#include "vabackend.h"
#include <string.h>
/* This one looks difficult to implement as NVDEC wants the whole JPEG file, and VA-API only supplied part of it */
static void copyJPEGPicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VAPictureParameterBufferJPEGBaseline* buf = (VAPictureParameterBufferJPEGBaseline*) buffer->ptr;
picParams->PicWidthInMbs = (int) ( buf->picture_width + 15) / 16; //int
picParams->FrameHeightInMbs = (int) ( buf->picture_height + 15) / 16; //int
picParams->field_pic_flag = 0;
picParams->bottom_field_flag = 0;
picParams->second_field = 0;
picParams->intra_pic_flag = 1;
picParams->ref_pic_flag = 0;
}
static void copyJPEGSliceParam(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
ctx->lastSliceParams = buf->ptr;
ctx->lastSliceParamsCount = buf->elements;
picParams->nNumSlices += buf->elements;
}
static void copyJPEGSliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
VASliceParameterBufferJPEGBaseline *sliceParams = &((VASliceParameterBufferJPEGBaseline*) ctx->lastSliceParams)[i];
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
picParams->nBitstreamDataLen += sliceParams->slice_data_size;
}
}
static cudaVideoCodec computeJPEGCudaCodec(VAProfile profile) {
switch (profile) {
case VAProfileJPEGBaseline:
return cudaVideoCodec_JPEG;
default:
return cudaVideoCodec_NONE;
}
}
static const VAProfile jpegSupportedProfiles[] = {
VAProfileJPEGBaseline,
};
const DECLARE_DISABLED_CODEC(jpegCodec) = {
.computeCudaCodec = computeJPEGCudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyJPEGPicParam,
[VASliceParameterBufferType] = copyJPEGSliceParam,
[VASliceDataBufferType] = copyJPEGSliceData,
},
.supportedProfileCount = ARRAY_SIZE(jpegSupportedProfiles),
.supportedProfiles = jpegSupportedProfiles,
};
0707010000003A000081A4000000000000000000000001663926A7000007B0000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/src/list.c#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "list.h"
static void ensure_capacity(Array *arr, uint32_t new_capacity) {
if (new_capacity <= arr->capacity) {
//we already have enough capacity to hold the new element
return;
}
uint32_t old_capacity = arr->capacity;
if (arr->capacity == 0) {
//if we're completely empty allocate a small amount
arr->capacity = 16;
} else {
//grow the capacity until we can hold the new amount
while (new_capacity > arr->capacity) {
arr->capacity += arr->capacity >> 1;
}
}
if (arr->buf == NULL) {
arr->buf = malloc(arr->capacity * sizeof(void*));
} else {
arr->buf = realloc(arr->buf, arr->capacity * sizeof(void*));
}
//clear the new part of the array
memset(&arr->buf[old_capacity], 0, (arr->capacity - old_capacity) * sizeof(void*));
}
void add_element(Array *arr, void *element) {
ensure_capacity(arr, arr->size + 1);
arr->buf[arr->size++] = element;
}
void* alloc_and_add_element(Array *arr, size_t size) {
ensure_capacity(arr, arr->size + 1);
void *element = calloc(1, size);
arr->buf[arr->size++] = element;
return element;
}
void remove_element_at(Array *arr, uint32_t index) {
if (index >= arr->size) {
return;
}
arr->size--;
if (index < arr->size) {
for (uint32_t i = index; i < arr->size; i++) {
arr->buf[i] = arr->buf[i+1];
}
}
//clear out the remaining element
arr->buf[arr->size] = NULL;
}
void remove_and_free_element_at(Array *arr, uint32_t index) {
void *element = get_element_at(arr, index);
remove_element_at(arr, index);
free(element);
}
uint32_t get_size(Array *arr) {
return arr->size;
}
void *get_element_at(Array *arr, uint32_t index) {
if (arr->buf == NULL || index >= arr->size) {
return NULL;
}
return arr->buf[index];
}
0707010000003B000081A4000000000000000000000001663926A70000035F000000000000000000000000000000000000002600000000nvidia-vaapi-driver-0.0.12/src/list.h#include <stdint.h>
#include <stddef.h>
typedef struct {
void **buf;
uint32_t size;
uint32_t capacity;
} Array;
//maybe not the nicest, but simple. Usage:
// ARRAY_FOR_EACH(void*, it, arr)
// printf("%u: %p\n", it_idx, it);
// END_FOR_EACH
#define ARRAY_FOR_EACH(T, N, A) for (uint32_t N ## _idx = 0; N ## _idx < (A)->size; N ## _idx++) { T N = (T) (A)->buf[N ## _idx];
#define ARRAY_FOR_EACH_REV(T, N, A) for (uint32_t N ## _idx = (A)->size-1; N ## _idx < (A)->size; N ## _idx--) { T N = (T) (A)->buf[N ## _idx];
#define END_FOR_EACH }
void add_element(Array *arr, void *element);
void remove_element_at(Array *arr, uint32_t index);
uint32_t get_size(Array *arr);
void *get_element_at(Array *arr, uint32_t index);
void remove_and_free_element_at(Array *arr, uint32_t index);
void* alloc_and_add_element(Array *arr, size_t size);
0707010000003C000081A4000000000000000000000001663926A700001A11000000000000000000000000000000000000002700000000nvidia-vaapi-driver-0.0.12/src/mpeg2.c#include "vabackend.h"
#include <string.h>
static const uint8_t ff_identity[64] = {
0, 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37, 38, 39,
40, 41, 42, 43, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63
};
static const uint8_t ff_zigzag_direct[64] = {
0, 1, 8, 16, 9, 2, 3, 10,
17, 24, 32, 25, 18, 11, 4, 5,
12, 19, 26, 33, 40, 48, 41, 34,
27, 20, 13, 6, 7, 14, 21, 28,
35, 42, 49, 56, 57, 50, 43, 36,
29, 22, 15, 23, 30, 37, 44, 51,
58, 59, 52, 45, 38, 31, 39, 46,
53, 60, 61, 54, 47, 55, 62, 63
};
static const uint8_t ff_mpeg1_default_intra_matrix[64] = {
8, 16, 19, 22, 26, 27, 29, 34,
16, 16, 22, 24, 27, 29, 34, 37,
19, 22, 26, 27, 29, 34, 34, 38,
22, 22, 26, 27, 29, 34, 37, 40,
22, 26, 27, 29, 32, 35, 40, 48,
26, 27, 29, 32, 35, 40, 48, 58,
26, 27, 29, 34, 38, 46, 56, 69,
27, 29, 35, 38, 46, 56, 69, 83
};
static const uint8_t ff_mpeg1_default_non_intra_matrix[64] = {
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 16
};
static void copyMPEG2PicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VAPictureParameterBufferMPEG2* buf = (VAPictureParameterBufferMPEG2*) buffer->ptr;
picParams->PicWidthInMbs = (int) ( buf->horizontal_size + 15) / 16; //int
picParams->FrameHeightInMbs = (int) ( buf->vertical_size + 15) / 16; //int
ctx->renderTarget->progressiveFrame = buf->picture_coding_extension.bits.progressive_frame;
picParams->field_pic_flag = buf->picture_coding_extension.bits.picture_structure != 3;
picParams->bottom_field_flag = buf->picture_coding_extension.bits.picture_structure == 2; //PICT_BOTTOM_FIELD
picParams->second_field = picParams->field_pic_flag && !buf->picture_coding_extension.bits.is_first_field;
picParams->intra_pic_flag = buf->picture_coding_type == 1; //Intra
picParams->ref_pic_flag = buf->picture_coding_type == 1 || //Intra
buf->picture_coding_type == 2; //Predicted
picParams->CodecSpecific.mpeg2.ForwardRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->forward_reference_picture);
picParams->CodecSpecific.mpeg2.BackwardRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->backward_reference_picture);
picParams->CodecSpecific.mpeg2.picture_coding_type = buf->picture_coding_type;
picParams->CodecSpecific.mpeg2.full_pel_forward_vector = 0;
picParams->CodecSpecific.mpeg2.full_pel_backward_vector = 0;
picParams->CodecSpecific.mpeg2.f_code[0][0] = (buf->f_code >> 12) & 0xf;
picParams->CodecSpecific.mpeg2.f_code[0][1] = (buf->f_code >> 8) & 0xf;
picParams->CodecSpecific.mpeg2.f_code[1][0] = (buf->f_code >> 4) & 0xf;
picParams->CodecSpecific.mpeg2.f_code[1][1] = buf->f_code & 0xf;
picParams->CodecSpecific.mpeg2.intra_dc_precision = buf->picture_coding_extension.bits.intra_dc_precision;;
picParams->CodecSpecific.mpeg2.frame_pred_frame_dct = buf->picture_coding_extension.bits.frame_pred_frame_dct;
picParams->CodecSpecific.mpeg2.concealment_motion_vectors = buf->picture_coding_extension.bits.concealment_motion_vectors;
picParams->CodecSpecific.mpeg2.q_scale_type = buf->picture_coding_extension.bits.q_scale_type;
picParams->CodecSpecific.mpeg2.intra_vlc_format = buf->picture_coding_extension.bits.intra_vlc_format;
picParams->CodecSpecific.mpeg2.alternate_scan = buf->picture_coding_extension.bits.alternate_scan;
picParams->CodecSpecific.mpeg2.top_field_first = buf->picture_coding_extension.bits.top_field_first;
}
static void copyMPEG2SliceParam(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
ctx->lastSliceParams = buf->ptr;
ctx->lastSliceParamsCount = buf->elements;
picParams->nNumSlices += buf->elements;
}
static void copyMPEG2SliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
VASliceParameterBufferMPEG2 *sliceParams = &((VASliceParameterBufferMPEG2*) ctx->lastSliceParams)[i];
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
picParams->nBitstreamDataLen += sliceParams->slice_data_size;
}
}
static void copyMPEG2IQMatrix(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
VAIQMatrixBufferMPEG2 *iq = (VAIQMatrixBufferMPEG2*) buf->ptr;
const uint8_t *intra_matrix, *intra_matrix_lookup;
const uint8_t *inter_matrix, *inter_matrix_lookup;
if (iq->load_intra_quantiser_matrix) {
intra_matrix = iq->intra_quantiser_matrix;
intra_matrix_lookup = ff_zigzag_direct;
}
else {
intra_matrix = ff_mpeg1_default_intra_matrix;
intra_matrix_lookup = ff_identity;
}
if (iq->load_non_intra_quantiser_matrix) {
inter_matrix = iq->non_intra_quantiser_matrix;
inter_matrix_lookup = ff_zigzag_direct;
}
else {
inter_matrix = ff_mpeg1_default_non_intra_matrix;
inter_matrix_lookup = ff_identity;
}
for (int i = 0; i < 64; i++) {
//Quantization matrices (raster order)
picParams->CodecSpecific.mpeg2.QuantMatrixIntra[intra_matrix_lookup[i]] = intra_matrix[i];
picParams->CodecSpecific.mpeg2.QuantMatrixInter[inter_matrix_lookup[i]] = inter_matrix[i];
}
}
static cudaVideoCodec computeMPEG2CudaCodec(VAProfile profile) {
switch (profile) {
case VAProfileMPEG2Main:
case VAProfileMPEG2Simple:
return cudaVideoCodec_MPEG2;
default:
return cudaVideoCodec_NONE;
}
}
static const VAProfile mpeg2SupportedProfiles[] = {
VAProfileMPEG2Main,
VAProfileMPEG2Simple,
};
const DECLARE_CODEC(mpeg2Codec) = {
.computeCudaCodec = computeMPEG2CudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyMPEG2PicParam,
[VAIQMatrixBufferType] = copyMPEG2IQMatrix,
[VASliceParameterBufferType] = copyMPEG2SliceParam,
[VASliceDataBufferType] = copyMPEG2SliceData,
},
.supportedProfileCount = ARRAY_SIZE(mpeg2SupportedProfiles),
.supportedProfiles = mpeg2SupportedProfiles,
};
0707010000003D000081A4000000000000000000000001663926A700001875000000000000000000000000000000000000002700000000nvidia-vaapi-driver-0.0.12/src/mpeg4.c#include "vabackend.h"
#include <math.h>
static void copyMPEG4PicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
//Not working, it seems that the information that VA-API supplies is not enough to feed NVDEC
//It might be possible to reconstruct it from the supplied fields like the VDPAU implementation does.
//In addition there looks to be a race condition in FFMPEG (h263_decode.c:573 : if (avctx->pix_fmt != h263_get_format(avctx)) {)
//where h263_get_format attempts to set pix_fmt, but the if statement has already read that value leading to a spurious failure.
VAPictureParameterBufferMPEG4* buf = (VAPictureParameterBufferMPEG4*) buffer->ptr;
CUVIDMPEG4PICPARAMS *ppc = &picParams->CodecSpecific.mpeg4;
picParams->PicWidthInMbs = (int) (buf->vop_width + 15) / 16; //int
picParams->FrameHeightInMbs = (int) (buf->vop_height + 15) / 16; //int
ctx->renderTarget->progressiveFrame = !buf->vol_fields.bits.interlaced;
picParams->field_pic_flag = buf->vol_fields.bits.interlaced;
picParams->bottom_field_flag = buf->vop_fields.bits.top_field_first;
picParams->second_field = 0;
picParams->intra_pic_flag = buf->vop_fields.bits.vop_coding_type == 0; //Intra
picParams->ref_pic_flag = buf->vop_fields.bits.vop_coding_type == 0 || //Intra
buf->vop_fields.bits.vop_coding_type == 1 || //Predicted
buf->vop_fields.bits.vop_coding_type == 3; //S(GMC)-VOP MPEG-4
ppc->ForwardRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->forward_reference_picture);
ppc->BackwardRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->backward_reference_picture);
ppc->video_object_layer_width = buf->vop_width;
ppc->video_object_layer_height = buf->vop_height;
ppc->vop_time_increment_bitcount = log2l(buf->vop_time_increment_resolution - 1) + 1; //
if (ppc->vop_time_increment_bitcount < 1) {
ppc->vop_time_increment_bitcount = 1;
}
ppc->top_field_first = buf->vop_fields.bits.top_field_first;
ppc->resync_marker_disable = buf->vol_fields.bits.resync_marker_disable;
ppc->quant_type = buf->vol_fields.bits.quant_type;
ppc->quarter_sample = buf->vol_fields.bits.quarter_sample;
ppc->short_video_header = buf->vol_fields.bits.short_video_header;
ppc->divx_flags = 5; //needed for test video...
ppc->vop_coding_type = buf->vop_fields.bits.vop_coding_type;
ppc->vop_coded = 1;//buf->vop_fields.bits.backward_reference_vop_coding_type; //?
ppc->vop_rounding_type = buf->vop_fields.bits.vop_rounding_type;
ppc->alternate_vertical_scan_flag = buf->vop_fields.bits.alternate_vertical_scan_flag;
ppc->interlaced = buf->vol_fields.bits.interlaced;
ppc->vop_fcode_forward = buf->vop_fcode_forward;
ppc->vop_fcode_backward = buf->vop_fcode_backward;
ppc->trd[0] = buf->TRD;
//ppc->trd[1] = 2; //not correct
ppc->trb[0] = buf->TRB;
//ppc->trb[1] = 4; //not correct
ppc->gmc_enabled = buf->vop_fields.bits.vop_coding_type == 3 && buf->vol_fields.bits.sprite_enable;
}
static void copyMPEG4SliceParam(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
ctx->lastSliceParams = buf->ptr;
ctx->lastSliceParamsCount = buf->elements;
picParams->nNumSlices += buf->elements;
}
static void copyMPEG4SliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
VASliceParameterBufferMPEG4 *sliceParams = &((VASliceParameterBufferMPEG4*) ctx->lastSliceParams)[i];
LOG("here: %d", sliceParams->macroblock_offset);
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
picParams->nBitstreamDataLen += sliceParams->slice_data_size;
}
}
static void copyMPEG4IQMatrix(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
VAIQMatrixBufferMPEG4 *iq = (VAIQMatrixBufferMPEG4*) buf->ptr;
for (int i = 0; i < 64; i++) {
picParams->CodecSpecific.mpeg4.QuantMatrixIntra[i] = iq->intra_quant_mat[i];
picParams->CodecSpecific.mpeg4.QuantMatrixInter[i] = iq->non_intra_quant_mat[i];
}
// for (int i = 0; i < 64; ++i) {
// printf("Intra[%d] = %d\n", i, ppc->QuantMatrixIntra[i]);
// printf("Inter[%d] = %d\n", i, ppc->QuantMatrixInter[i]);
// }
}
static cudaVideoCodec computeMPEG4CudaCodec(VAProfile profile) {
switch (profile) {
case VAProfileH263Baseline:
case VAProfileMPEG4Main:
case VAProfileMPEG4Simple:
case VAProfileMPEG4AdvancedSimple:
return cudaVideoCodec_MPEG4;
default:
return cudaVideoCodec_NONE;
}
}
static const VAProfile mpeg4SupportProfiles[] = {
VAProfileH263Baseline,
VAProfileMPEG4Main,
VAProfileMPEG4Simple,
VAProfileMPEG4AdvancedSimple,
};
// change this to DECLARE_CODEC to reenable MPEG-4 support
const DECLARE_DISABLED_CODEC(mpeg4Codec) = {
.computeCudaCodec = computeMPEG4CudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyMPEG4PicParam,
[VAIQMatrixBufferType] = copyMPEG4IQMatrix,
[VASliceParameterBufferType] = copyMPEG4SliceParam,
[VASliceDataBufferType] = copyMPEG4SliceData,
},
.supportedProfileCount = ARRAY_SIZE(mpeg4SupportProfiles),
.supportedProfiles = mpeg4SupportProfiles,
};
/*
This code needs to go in nvCreateBuffer, to realign the buffer to capture everything that's needed by NVDEC. However this hack is specific to ffmpeg
and is likely to break anything that doesn't pass in a pointer into the full data. Also, I'm not sure the values (69 and 8) are valid for all videos.
else if ((nvCtx->profile == VAProfileMPEG4AdvancedSimple || nvCtx->profile == VAProfileMPEG4Main || nvCtx->profile == VAProfileMPEG4Simple)
&& type == VASliceDataBufferType) {
//HACK HACK HACK
offset = 69;
if ((((uintptr_t) data - 8) & 0xf) == 0) {
offset = 8;
}
data -= offset;
size += offset;
}
*/
0707010000003E000081A4000000000000000000000001663926A7000121C7000000000000000000000000000000000000002B00000000nvidia-vaapi-driver-0.0.12/src/vabackend.c#define _GNU_SOURCE
#include "vabackend.h"
#include <assert.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys/param.h>
#include <sys/ioctl.h>
#include <inttypes.h>
#include <va/va_backend.h>
#include <va/va_drmcommon.h>
#include <drm_fourcc.h>
#include <unistd.h>
#include <sys/types.h>
#include <stdarg.h>
#include <time.h>
#ifndef __has_builtin
#define __has_builtin(x) 0
#endif
#ifndef __has_include
#define __has_include(x) 0
#endif
#if __has_include(<pthread_np.h>)
#include <pthread_np.h>
#define gettid pthread_getthreadid_np
#define HAVE_GETTID 1
#endif
#ifndef HAVE_GETTID
#include <sys/syscall.h>
/* Bionic and glibc >= 2.30 declare gettid() system call wrapper in unistd.h and
* has a definition for it */
#ifdef __BIONIC__
#define HAVE_GETTID 1
#elif !defined(__GLIBC_PREREQ)
#define HAVE_GETTID 0
#elif !__GLIBC_PREREQ(2,30)
#define HAVE_GETTID 0
#else
#define HAVE_GETTID 1
#endif
#endif
static pid_t nv_gettid(void)
{
#if HAVE_GETTID
return gettid();
#else
return syscall(__NR_gettid);
#endif
}
static pthread_mutex_t concurrency_mutex = PTHREAD_MUTEX_INITIALIZER;
static uint32_t instances;
static uint32_t max_instances;
static CudaFunctions *cu;
static CuvidFunctions *cv;
extern const NVCodec __start_nvd_codecs[];
extern const NVCodec __stop_nvd_codecs[];
static FILE *LOG_OUTPUT;
static int gpu = -1;
static enum {
EGL, DIRECT
} backend = DIRECT;
const NVFormatInfo formatsInfo[] =
{
[NV_FORMAT_NONE] = {0},
[NV_FORMAT_NV12] = {1, 2, DRM_FORMAT_NV12, false, false, {{1, DRM_FORMAT_R8, {0,0}}, {2, DRM_FORMAT_RG88, {1,1}}}, {VA_FOURCC_NV12, VA_LSB_FIRST, 12, 0,0,0,0,0}},
[NV_FORMAT_P010] = {2, 2, DRM_FORMAT_P010, true, false, {{1, DRM_FORMAT_R16, {0,0}}, {2, DRM_FORMAT_RG1616, {1,1}}}, {VA_FOURCC_P010, VA_LSB_FIRST, 24, 0,0,0,0,0}},
[NV_FORMAT_P012] = {2, 2, DRM_FORMAT_P012, true, false, {{1, DRM_FORMAT_R16, {0,0}}, {2, DRM_FORMAT_RG1616, {1,1}}}, {VA_FOURCC_P012, VA_LSB_FIRST, 24, 0,0,0,0,0}},
[NV_FORMAT_P016] = {2, 2, DRM_FORMAT_P016, true, false, {{1, DRM_FORMAT_R16, {0,0}}, {2, DRM_FORMAT_RG1616, {1,1}}}, {VA_FOURCC_P016, VA_LSB_FIRST, 24, 0,0,0,0,0}},
[NV_FORMAT_444P] = {1, 3, DRM_FORMAT_YUV444, false, true, {{1, DRM_FORMAT_R8, {0,0}}, {1, DRM_FORMAT_R8, {0,0}}, {1, DRM_FORMAT_R8, {0,0}}}, {VA_FOURCC_444P, VA_LSB_FIRST, 24, 0,0,0,0,0}},
#if VA_CHECK_VERSION(1, 20, 0)
[NV_FORMAT_Q416] = {2, 3, DRM_FORMAT_INVALID, true, true, {{1, DRM_FORMAT_R16, {0,0}}, {1, DRM_FORMAT_R16, {0,0}}, {1, DRM_FORMAT_R16,{0,0}}}, {VA_FOURCC_Q416, VA_LSB_FIRST, 48, 0,0,0,0,0}},
#endif
};
static NVFormat nvFormatFromVaFormat(uint32_t fourcc) {
for (uint32_t i = NV_FORMAT_NONE + 1; i < ARRAY_SIZE(formatsInfo); i++) {
if (formatsInfo[i].vaFormat.fourcc == fourcc) {
return i;
}
}
return NV_FORMAT_NONE;
}
__attribute__ ((constructor))
static void init() {
char *nvdLog = getenv("NVD_LOG");
if (nvdLog != NULL) {
if (strcmp(nvdLog, "1") == 0) {
LOG_OUTPUT = stdout;
} else {
LOG_OUTPUT = fopen(nvdLog, "a");
if (LOG_OUTPUT == NULL) {
LOG_OUTPUT = stdout;
}
}
}
char *nvdGpu = getenv("NVD_GPU");
if (nvdGpu != NULL) {
gpu = atoi(nvdGpu);
}
char *nvdMaxInstances = getenv("NVD_MAX_INSTANCES");
if (nvdMaxInstances != NULL) {
max_instances = atoi(nvdMaxInstances);
}
char *nvdBackend = getenv("NVD_BACKEND");
if (nvdBackend != NULL) {
if (strncmp(nvdBackend, "direct", 6) == 0) {
backend = DIRECT;
} else if (strncmp(nvdBackend, "egl", 6) == 0) {
backend = EGL;
}
}
//try to detect the Firefox sandbox and skip loading CUDA if detected
int fd = open("/proc/version", O_RDONLY);
if (fd < 0) {
LOG("ERROR: Potential Firefox sandbox detected, failing to init!");
LOG("If running in Firefox, set env var MOZ_DISABLE_RDD_SANDBOX=1 to disable sandbox.");
//exit here so we don't init CUDA, unless an env var has been set to force us to init even though we've detected a sandbox
if (getenv("NVD_FORCE_INIT") == NULL) {
return;
}
} else {
//we're not in a sandbox
//continue as normal
close(fd);
}
//initialise the CUDA and NVDEC functions
int ret = cuda_load_functions(&cu, NULL);
if (ret != 0) {
cu = NULL;
LOG("Failed to load CUDA functions");
return;
}
ret = cuvid_load_functions(&cv, NULL);
if (ret != 0) {
cv = NULL;
LOG("Failed to load NVDEC functions");
return;
}
//Not really much we can do here to abort the loading of the library
CHECK_CUDA_RESULT(cu->cuInit(0));
}
__attribute__ ((destructor))
static void cleanup() {
if (cv != NULL) {
cuvid_free_functions(&cv);
}
if (cu != NULL) {
cuda_free_functions(&cu);
}
}
#ifndef __has_attribute
#define __has_attribute(x) 0
#endif
#if __has_attribute(gnu_printf) || (defined(__GNUC__) && !defined(__clang__))
__attribute((format(gnu_printf, 4, 5)))
#endif
void logger(const char *filename, const char *function, int line, const char *msg, ...) {
if (LOG_OUTPUT == 0) {
return;
}
va_list argList;
char formattedMessage[1024];
va_start(argList, msg);
vsnprintf(formattedMessage, 1024, msg, argList);
va_end(argList);
struct timespec tp;
clock_gettime(CLOCK_MONOTONIC, &tp);
fprintf(LOG_OUTPUT, "%10ld.%09ld [%d-%d] %s:%4d %24s %s\n", (long)tp.tv_sec, tp.tv_nsec, getpid(), nv_gettid(), filename, line, function, formattedMessage);
fflush(LOG_OUTPUT);
}
bool checkCudaErrors(CUresult err, const char *file, const char *function, const int line) {
if (CUDA_SUCCESS != err) {
const char *errStr = NULL;
cu->cuGetErrorString(err, &errStr);
logger(file, function, line, "CUDA ERROR '%s' (%d)\n", errStr, err);
return true;
}
return false;
}
void appendBuffer(AppendableBuffer *ab, const void *buf, uint64_t size) {
if (ab->buf == NULL) {
ab->allocated = size*2;
ab->buf = memalign(16, ab->allocated);
ab->size = 0;
} else if (ab->size + size > ab->allocated) {
while (ab->size + size > ab->allocated) {
ab->allocated += ab->allocated >> 1;
}
void *nb = memalign(16, ab->allocated);
memcpy(nb, ab->buf, ab->size);
free(ab->buf);
ab->buf = nb;
}
memcpy(PTROFF(ab->buf, ab->size), buf, size);
ab->size += size;
}
static void freeBuffer(AppendableBuffer *ab) {
if (ab->buf != NULL) {
free(ab->buf);
ab->buf = NULL;
ab->size = 0;
ab->allocated = 0;
}
}
static Object allocateObject(NVDriver *drv, ObjectType type, int allocatePtrSize) {
Object newObj = (Object) calloc(1, sizeof(struct Object_t));
newObj->type = type;
newObj->id = (++drv->nextObjId);
if (allocatePtrSize > 0) {
newObj->obj = calloc(1, allocatePtrSize);
}
pthread_mutex_lock(&drv->objectCreationMutex);
add_element(&drv->objects, newObj);
pthread_mutex_unlock(&drv->objectCreationMutex);
return newObj;
}
static Object getObject(NVDriver *drv, VAGenericID id) {
Object ret = NULL;
if (id != VA_INVALID_ID) {
pthread_mutex_lock(&drv->objectCreationMutex);
ARRAY_FOR_EACH(Object, o, &drv->objects)
if (o->id == id) {
ret = o;
break;
}
END_FOR_EACH
pthread_mutex_unlock(&drv->objectCreationMutex);
}
return ret;
}
static void* getObjectPtr(NVDriver *drv, VAGenericID id) {
if (id != VA_INVALID_ID) {
Object o = getObject(drv, id);
if (o != NULL) {
return o->obj;
}
}
return NULL;
}
static Object getObjectByPtr(NVDriver *drv, void *ptr) {
Object ret = NULL;
if (ptr != NULL) {
pthread_mutex_lock(&drv->objectCreationMutex);
ARRAY_FOR_EACH(Object, o, &drv->objects)
if (o->obj == ptr) {
ret = o;
break;
}
END_FOR_EACH
pthread_mutex_unlock(&drv->objectCreationMutex);
}
return ret;
}
static void deleteObject(NVDriver *drv, VAGenericID id) {
if (id == VA_INVALID_ID) {
return;
}
pthread_mutex_lock(&drv->objectCreationMutex);
ARRAY_FOR_EACH(Object, o, &drv->objects)
if (o->id == id) {
remove_element_at(&drv->objects, o_idx);
if (o->obj != NULL) {
free(o->obj);
}
free(o);
//we've found the object, no need to continue
break;
}
END_FOR_EACH
pthread_mutex_unlock(&drv->objectCreationMutex);
}
static bool destroyContext(NVDriver *drv, NVContext *nvCtx) {
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), false);
LOG("Signaling resolve thread to exit");
struct timespec timeout;
clock_gettime(CLOCK_REALTIME, &timeout);
timeout.tv_sec += 5;
nvCtx->exiting = true;
pthread_cond_signal(&nvCtx->resolveCondition);
LOG("Waiting for resolve thread to exit");
int ret = pthread_timedjoin_np(nvCtx->resolveThread, NULL, &timeout);
LOG("pthread_timedjoin_np finished with %d", ret);
freeBuffer(&nvCtx->sliceOffsets);
freeBuffer(&nvCtx->bitstreamBuffer);
bool successful = true;
if (nvCtx->decoder != NULL) {
CUresult result = cv->cuvidDestroyDecoder(nvCtx->decoder);
if (result != CUDA_SUCCESS) {
LOG("cuvidDestroyDecoder failed: %d", result);
successful = false;
}
}
nvCtx->decoder = NULL;
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPopCurrent(NULL), false);
return successful;
}
static void deleteAllObjects(NVDriver *drv) {
pthread_mutex_lock(&drv->objectCreationMutex);
ARRAY_FOR_EACH(Object, o, &drv->objects)
LOG("Found object %d or type %d", o->id, o->type);
if (o->type == OBJECT_TYPE_CONTEXT) {
destroyContext(drv, (NVContext*) o->obj);
deleteObject(drv, o->id);
}
END_FOR_EACH
pthread_mutex_unlock(&drv->objectCreationMutex);
}
NVSurface* nvSurfaceFromSurfaceId(NVDriver *drv, VASurfaceID surf) {
Object obj = getObject(drv, surf);
if (obj != NULL && obj->type == OBJECT_TYPE_SURFACE) {
NVSurface *suf = (NVSurface*) obj->obj;
return suf;
}
return NULL;
}
int pictureIdxFromSurfaceId(NVDriver *drv, VASurfaceID surfId) {
NVSurface *surf = nvSurfaceFromSurfaceId(drv, surfId);
if (surf != NULL) {
return surf->pictureIdx;
}
return -1;
}
static cudaVideoCodec vaToCuCodec(VAProfile profile) {
for (const NVCodec *c = __start_nvd_codecs; c < __stop_nvd_codecs; c++) {
cudaVideoCodec cvc = c->computeCudaCodec(profile);
if (cvc != cudaVideoCodec_NONE) {
return cvc;
}
}
return cudaVideoCodec_NONE;
}
static bool doesGPUSupportCodec(cudaVideoCodec codec, int bitDepth, cudaVideoChromaFormat chromaFormat, uint32_t *width, uint32_t *height)
{
CUVIDDECODECAPS videoDecodeCaps = {
.eCodecType = codec,
.eChromaFormat = chromaFormat,
.nBitDepthMinus8 = bitDepth - 8
};
CHECK_CUDA_RESULT_RETURN(cv->cuvidGetDecoderCaps(&videoDecodeCaps), false);
if (width != NULL) {
*width = videoDecodeCaps.nMaxWidth;
}
if (height != NULL) {
*height = videoDecodeCaps.nMaxHeight;
}
return (videoDecodeCaps.bIsSupported == 1);
}
static void* resolveSurfaces(void *param) {
NVContext *ctx = (NVContext*) param;
NVDriver *drv = ctx->drv;
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), NULL);
LOG("[RT] Resolve thread for %p started", ctx);
while (!ctx->exiting) {
//wait for frame on queue
pthread_mutex_lock(&ctx->resolveMutex);
while (ctx->surfaceQueueReadIdx == ctx->surfaceQueueWriteIdx) {
pthread_cond_wait(&ctx->resolveCondition, &ctx->resolveMutex);
if (ctx->exiting) {
pthread_mutex_unlock(&ctx->resolveMutex);
goto out;
}
}
pthread_mutex_unlock(&ctx->resolveMutex);
//find the last item
//LOG("Reading from queue: %d %d", ctx->surfaceQueueReadIdx, ctx->surfaceQueueWriteIdx);
NVSurface *surface = ctx->surfaceQueue[ctx->surfaceQueueReadIdx++];
if (ctx->surfaceQueueReadIdx >= SURFACE_QUEUE_SIZE) {
ctx->surfaceQueueReadIdx = 0;
}
CUdeviceptr deviceMemory = (CUdeviceptr) NULL;
unsigned int pitch = 0;
//map frame
CUVIDPROCPARAMS procParams = {
.progressive_frame = surface->progressiveFrame,
.top_field_first = surface->topFieldFirst,
.second_field = surface->secondField
};
//LOG("Mapping surface %d", surface->pictureIdx);
if (CHECK_CUDA_RESULT(cv->cuvidMapVideoFrame(ctx->decoder, surface->pictureIdx, &deviceMemory, &pitch, &procParams))) {
continue;
}
//LOG("Mapped surface %d to %p (%d)", surface->pictureIdx, (void*)deviceMemory, pitch);
//update cuarray
drv->backend->exportCudaPtr(drv, deviceMemory, surface, pitch);
//LOG("Surface %d exported", surface->pictureIdx);
//unmap frame
CHECK_CUDA_RESULT(cv->cuvidUnmapVideoFrame(ctx->decoder, deviceMemory));
}
out:
LOG("[RT] Resolve thread for %p exiting", ctx);
return NULL;
}
#define MAX_PROFILES 32
static VAStatus nvQueryConfigProfiles(
VADriverContextP ctx,
VAProfile *profile_list, /* out */
int *num_profiles /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
int profiles = 0;
if (doesGPUSupportCodec(cudaVideoCodec_MPEG2, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileMPEG2Simple;
profile_list[profiles++] = VAProfileMPEG2Main;
}
if (doesGPUSupportCodec(cudaVideoCodec_MPEG4, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileMPEG4Simple;
profile_list[profiles++] = VAProfileMPEG4AdvancedSimple;
profile_list[profiles++] = VAProfileMPEG4Main;
}
if (doesGPUSupportCodec(cudaVideoCodec_VC1, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileVC1Simple;
profile_list[profiles++] = VAProfileVC1Main;
profile_list[profiles++] = VAProfileVC1Advanced;
}
if (doesGPUSupportCodec(cudaVideoCodec_H264, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileH264Main;
profile_list[profiles++] = VAProfileH264High;
profile_list[profiles++] = VAProfileH264ConstrainedBaseline;
}
if (doesGPUSupportCodec(cudaVideoCodec_JPEG, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileJPEGBaseline;
}
if (doesGPUSupportCodec(cudaVideoCodec_H264_SVC, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileH264StereoHigh;
}
if (doesGPUSupportCodec(cudaVideoCodec_H264_MVC, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileH264MultiviewHigh;
}
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain;
}
if (doesGPUSupportCodec(cudaVideoCodec_VP8, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileVP8Version0_3;
}
if (doesGPUSupportCodec(cudaVideoCodec_VP9, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileVP9Profile0; //color depth: 8 bit, 4:2:0
}
if (doesGPUSupportCodec(cudaVideoCodec_AV1, 8, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileAV1Profile0;
}
if (drv->supports16BitSurface) {
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 10, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain10;
}
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 12, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain12;
}
if (doesGPUSupportCodec(cudaVideoCodec_VP9, 10, cudaVideoChromaFormat_420, NULL, NULL)) {
profile_list[profiles++] = VAProfileVP9Profile2; //color depth: 10–12 bit, 4:2:0
}
}
if (drv->supports444Surface) {
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 8, cudaVideoChromaFormat_444, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain444;
}
if (doesGPUSupportCodec(cudaVideoCodec_VP9, 8, cudaVideoChromaFormat_444, NULL, NULL)) {
profile_list[profiles++] = VAProfileVP9Profile1; //color depth: 8 bit, 4:2:2, 4:4:0, 4:4:4
}
if (doesGPUSupportCodec(cudaVideoCodec_AV1, 8, cudaVideoChromaFormat_444, NULL, NULL)) {
profile_list[profiles++] = VAProfileAV1Profile1;
}
#if VA_CHECK_VERSION(1, 20, 0)
if (drv->supports16BitSurface) {
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 10, cudaVideoChromaFormat_444, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain444_10;
}
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 12, cudaVideoChromaFormat_444, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain444_12;
}
if (doesGPUSupportCodec(cudaVideoCodec_VP9, 10, cudaVideoChromaFormat_444, NULL, NULL)) {
profile_list[profiles++] = VAProfileVP9Profile3; //color depth: 10–12 bit, 4:2:2, 4:4:0, 4:4:4
}
}
#endif
}
// Nvidia decoder doesn't support 422 chroma layout
#if 0
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 10, cudaVideoChromaFormat_422, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain422_10;
}
if (doesGPUSupportCodec(cudaVideoCodec_HEVC, 12, cudaVideoChromaFormat_422, NULL, NULL)) {
profile_list[profiles++] = VAProfileHEVCMain422_12;
}
#endif
//now filter out the codecs we don't support
for (int i = 0; i < profiles; i++) {
if (vaToCuCodec(profile_list[i]) == cudaVideoCodec_NONE) {
for (int x = i; x < profiles-1; x++) {
profile_list[x] = profile_list[x+1];
}
profiles--;
i--;
}
}
*num_profiles = profiles;
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPopCurrent(NULL), VA_STATUS_ERROR_OPERATION_FAILED);
return VA_STATUS_SUCCESS;
}
static VAStatus nvQueryConfigEntrypoints(
VADriverContextP ctx,
VAProfile profile,
VAEntrypoint *entrypoint_list, /* out */
int *num_entrypoints /* out */
)
{
entrypoint_list[0] = VAEntrypointVLD;
*num_entrypoints = 1;
return VA_STATUS_SUCCESS;
}
static VAStatus nvGetConfigAttributes(
VADriverContextP ctx,
VAProfile profile,
VAEntrypoint entrypoint,
VAConfigAttrib *attrib_list, /* in/out */
int num_attribs
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
if (vaToCuCodec(profile) == cudaVideoCodec_NONE) {
return VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
}
LOG("Got here with profile: %d == %d", profile, vaToCuCodec(profile));
for (int i = 0; i < num_attribs; i++)
{
if (attrib_list[i].type == VAConfigAttribRTFormat)
{
attrib_list[i].value = VA_RT_FORMAT_YUV420;
switch (profile) {
case VAProfileHEVCMain12:
case VAProfileVP9Profile2:
attrib_list[i].value |= VA_RT_FORMAT_YUV420_12;
// Fall-through
case VAProfileHEVCMain10:
case VAProfileAV1Profile0:
attrib_list[i].value |= VA_RT_FORMAT_YUV420_10;
break;
case VAProfileHEVCMain444_12:
case VAProfileVP9Profile3:
attrib_list[i].value |= VA_RT_FORMAT_YUV444_12 | VA_RT_FORMAT_YUV420_12;
// Fall-through
case VAProfileHEVCMain444_10:
case VAProfileAV1Profile1:
attrib_list[i].value |= VA_RT_FORMAT_YUV444_10 | VA_RT_FORMAT_YUV420_10;
// Fall-through
case VAProfileHEVCMain444:
case VAProfileVP9Profile1:
attrib_list[i].value |= VA_RT_FORMAT_YUV444;
break;
default:
//do nothing
break;
}
if (!drv->supports16BitSurface) {
attrib_list[i].value &= ~(VA_RT_FORMAT_YUV420_10 | VA_RT_FORMAT_YUV420_12 | VA_RT_FORMAT_YUV444_10 | VA_RT_FORMAT_YUV444_12);
}
if (!drv->supports444Surface) {
attrib_list[i].value &= ~(VA_RT_FORMAT_YUV444 | VA_RT_FORMAT_YUV444_10 | VA_RT_FORMAT_YUV444_12);
}
}
else if (attrib_list[i].type == VAConfigAttribMaxPictureWidth)
{
doesGPUSupportCodec(vaToCuCodec(profile), 8, cudaVideoChromaFormat_420, &attrib_list[i].value, NULL);
}
else if (attrib_list[i].type == VAConfigAttribMaxPictureHeight)
{
doesGPUSupportCodec(vaToCuCodec(profile), 8, cudaVideoChromaFormat_420, NULL, &attrib_list[i].value);
}
else
{
LOG("unhandled config attribute: %d", attrib_list[i].type);
}
}
return VA_STATUS_SUCCESS;
}
static VAStatus nvCreateConfig(
VADriverContextP ctx,
VAProfile profile,
VAEntrypoint entrypoint,
VAConfigAttrib *attrib_list,
int num_attribs,
VAConfigID *config_id /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
LOG("got profile: %d with %d attributes", profile, num_attribs);
cudaVideoCodec cudaCodec = vaToCuCodec(profile);
if (cudaCodec == cudaVideoCodec_NONE) {
//we don't support this yet
LOG("Profile not supported: %d", profile);
return VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
}
if (entrypoint != VAEntrypointVLD) {
LOG("Entrypoint not supported: %d", entrypoint);
return VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
}
Object obj = allocateObject(drv, OBJECT_TYPE_CONFIG, sizeof(NVConfig));
NVConfig *cfg = (NVConfig*) obj->obj;
cfg->profile = profile;
cfg->entrypoint = entrypoint;
//this will contain all the attributes the client cares about
for (int i = 0; i < num_attribs; i++) {
LOG("got config attrib: %d %d %d", i, attrib_list[i].type, attrib_list[i].value);
}
cfg->cudaCodec = cudaCodec;
cfg->chromaFormat = cudaVideoChromaFormat_420;
cfg->surfaceFormat = cudaVideoSurfaceFormat_NV12;
cfg->bitDepth = 8;
if (drv->supports16BitSurface) {
switch(cfg->profile) {
case VAProfileHEVCMain10:
cfg->surfaceFormat = cudaVideoSurfaceFormat_P016;
cfg->bitDepth = 10;
break;
case VAProfileHEVCMain12:
cfg->surfaceFormat = cudaVideoSurfaceFormat_P016;
cfg->bitDepth = 12;
break;
case VAProfileVP9Profile2:
case VAProfileAV1Profile0:
// If the user provides an RTFormat, we can use that to identify which decoder
// configuration is appropriate. If a format is not required here, the caller
// must pass render targets to createContext so we can use those to establish
// the surface format and bit depth.
if (num_attribs > 0 && attrib_list[0].type == VAConfigAttribRTFormat) {
switch(attrib_list[0].value) {
case VA_RT_FORMAT_YUV420_12:
cfg->surfaceFormat = cudaVideoSurfaceFormat_P016;
cfg->bitDepth = 12;
break;
case VA_RT_FORMAT_YUV420_10:
cfg->surfaceFormat = cudaVideoSurfaceFormat_P016;
cfg->bitDepth = 10;
break;
default:
break;
}
} else {
if (cfg->profile == VAProfileVP9Profile2) {
cfg->surfaceFormat = cudaVideoSurfaceFormat_P016;
cfg->bitDepth = 10;
} else {
LOG("Unable to determine surface type for VP9/AV1 codec due to no RTFormat specified.");
}
}
default:
break;
}
}
if (drv->supports444Surface) {
switch(cfg->profile) {
case VAProfileHEVCMain444:
case VAProfileVP9Profile1:
case VAProfileAV1Profile1:
cfg->surfaceFormat = cudaVideoSurfaceFormat_YUV444;
cfg->chromaFormat = cudaVideoChromaFormat_444;
cfg->bitDepth = 8;
break;
default:
break;
}
}
if (drv->supports444Surface && drv->supports16BitSurface) {
switch(cfg->profile) {
case VAProfileHEVCMain444_10:
cfg->surfaceFormat = cudaVideoSurfaceFormat_YUV444_16Bit;
cfg->chromaFormat = cudaVideoChromaFormat_444;
cfg->bitDepth = 10;
break;
case VAProfileHEVCMain444_12:
cfg->surfaceFormat = cudaVideoSurfaceFormat_YUV444_16Bit;
cfg->chromaFormat = cudaVideoChromaFormat_444;
cfg->bitDepth = 12;
break;
case VAProfileVP9Profile3:
case VAProfileAV1Profile1:
// If the user provides an RTFormat, we can use that to identify which decoder
// configuration is appropriate. If a format is not required here, the caller
// must pass render targets to createContext so we can use those to establish
// the surface format and bit depth.
if (num_attribs > 0 && attrib_list[0].type == VAConfigAttribRTFormat) {
switch(attrib_list[0].value) {
case VA_RT_FORMAT_YUV444_12:
cfg->surfaceFormat = cudaVideoSurfaceFormat_YUV444_16Bit;
cfg->chromaFormat = cudaVideoChromaFormat_444;
cfg->bitDepth = 12;
break;
case VA_RT_FORMAT_YUV444_10:
cfg->surfaceFormat = cudaVideoSurfaceFormat_YUV444_16Bit;
cfg->chromaFormat = cudaVideoChromaFormat_444;
cfg->bitDepth = 10;
break;
case VA_RT_FORMAT_YUV444:
cfg->surfaceFormat = cudaVideoSurfaceFormat_YUV444;
cfg->chromaFormat = cudaVideoChromaFormat_444;
cfg->bitDepth = 8;
break;
default:
break;
}
} else {
if (cfg->profile == VAProfileVP9Profile3) {
cfg->surfaceFormat = cudaVideoSurfaceFormat_YUV444_16Bit;
cfg->chromaFormat = cudaVideoChromaFormat_444;
cfg->bitDepth = 10;
}
}
default:
break;
}
}
*config_id = obj->id;
return VA_STATUS_SUCCESS;
}
static VAStatus nvDestroyConfig(
VADriverContextP ctx,
VAConfigID config_id
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
deleteObject(drv, config_id);
return VA_STATUS_SUCCESS;
}
static VAStatus nvQueryConfigAttributes(
VADriverContextP ctx,
VAConfigID config_id,
VAProfile *profile, /* out */
VAEntrypoint *entrypoint, /* out */
VAConfigAttrib *attrib_list, /* out */
int *num_attribs /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVConfig *cfg = (NVConfig*) getObjectPtr(drv, config_id);
if (cfg == NULL) {
return VA_STATUS_ERROR_INVALID_CONFIG;
}
*profile = cfg->profile;
*entrypoint = cfg->entrypoint;
int i = 0;
attrib_list[i].value = VA_RT_FORMAT_YUV420;
attrib_list[i].type = VAConfigAttribRTFormat;
switch (cfg->profile) {
case VAProfileHEVCMain12:
case VAProfileVP9Profile2:
attrib_list[i].value |= VA_RT_FORMAT_YUV420_12;
// Fall-through
case VAProfileHEVCMain10:
case VAProfileAV1Profile0:
attrib_list[i].value |= VA_RT_FORMAT_YUV420_10;
break;
case VAProfileHEVCMain444_12:
case VAProfileVP9Profile3:
attrib_list[i].value |= VA_RT_FORMAT_YUV444_12 | VA_RT_FORMAT_YUV420_12;
// Fall-through
case VAProfileHEVCMain444_10:
case VAProfileAV1Profile1:
attrib_list[i].value |= VA_RT_FORMAT_YUV444_10 | VA_RT_FORMAT_YUV420_10;
// Fall-through
case VAProfileHEVCMain444:
case VAProfileVP9Profile1:
attrib_list[i].value |= VA_RT_FORMAT_YUV444;
break;
default:
//do nothing
break;
}
if (!drv->supports16BitSurface) {
attrib_list[i].value &= ~(VA_RT_FORMAT_YUV420_10 | VA_RT_FORMAT_YUV420_12 | VA_RT_FORMAT_YUV444_10 | VA_RT_FORMAT_YUV444_12);
}
if (!drv->supports444Surface) {
attrib_list[i].value &= ~(VA_RT_FORMAT_YUV444 | VA_RT_FORMAT_YUV444_10 | VA_RT_FORMAT_YUV444_12);
}
i++;
*num_attribs = i;
return VA_STATUS_SUCCESS;
}
static VAStatus nvCreateSurfaces2(
VADriverContextP ctx,
unsigned int format,
unsigned int width,
unsigned int height,
VASurfaceID *surfaces,
unsigned int num_surfaces,
VASurfaceAttrib *attrib_list,
unsigned int num_attribs
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
cudaVideoSurfaceFormat nvFormat;
cudaVideoChromaFormat chromaFormat;
int bitdepth;
switch (format)
{
case VA_RT_FORMAT_YUV420:
nvFormat = cudaVideoSurfaceFormat_NV12;
chromaFormat = cudaVideoChromaFormat_420;
bitdepth = 8;
break;
case VA_RT_FORMAT_YUV420_10:
nvFormat = cudaVideoSurfaceFormat_P016;
chromaFormat = cudaVideoChromaFormat_420;
bitdepth = 10;
break;
case VA_RT_FORMAT_YUV420_12:
nvFormat = cudaVideoSurfaceFormat_P016;
chromaFormat = cudaVideoChromaFormat_420;
bitdepth = 12;
break;
case VA_RT_FORMAT_YUV444:
nvFormat = cudaVideoSurfaceFormat_YUV444;
chromaFormat = cudaVideoChromaFormat_444;
bitdepth = 8;
break;
case VA_RT_FORMAT_YUV444_10:
nvFormat = cudaVideoSurfaceFormat_YUV444_16Bit;
chromaFormat = cudaVideoChromaFormat_444;
bitdepth = 10;
break;
case VA_RT_FORMAT_YUV444_12:
nvFormat = cudaVideoSurfaceFormat_YUV444_16Bit;
chromaFormat = cudaVideoChromaFormat_444;
bitdepth = 12;
break;
default:
LOG("Unknown format: %X", format);
return VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT;
}
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
for (uint32_t i = 0; i < num_surfaces; i++) {
Object surfaceObject = allocateObject(drv, OBJECT_TYPE_SURFACE, sizeof(NVSurface));
surfaces[i] = surfaceObject->id;
NVSurface *suf = (NVSurface*) surfaceObject->obj;
suf->width = width;
suf->height = height;
suf->format = nvFormat;
suf->pictureIdx = -1;
suf->bitDepth = bitdepth;
suf->context = NULL;
suf->chromaFormat = chromaFormat;
pthread_mutex_init(&suf->mutex, NULL);
pthread_cond_init(&suf->cond, NULL);
LOG("Creating surface %dx%d, format %X (%p)", width, height, format, suf);
}
drv->surfaceCount += num_surfaces;
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPopCurrent(NULL), VA_STATUS_ERROR_OPERATION_FAILED);
return VA_STATUS_SUCCESS;
}
static VAStatus nvCreateSurfaces(
VADriverContextP ctx,
int width,
int height,
int format,
int num_surfaces,
VASurfaceID *surfaces /* out */
)
{
return nvCreateSurfaces2(ctx, format, width, height, surfaces, num_surfaces, NULL, 0);
}
static VAStatus nvDestroySurfaces(
VADriverContextP ctx,
VASurfaceID *surface_list,
int num_surfaces
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
for (int i = 0; i < num_surfaces; i++) {
NVSurface *surface = (NVSurface*) getObjectPtr(drv, surface_list[i]);
LOG("Destroying surface %d (%p)", surface->pictureIdx, surface);
drv->backend->detachBackingImageFromSurface(drv, surface);
deleteObject(drv, surface_list[i]);
}
drv->surfaceCount = MAX(drv->surfaceCount - num_surfaces, 0);
return VA_STATUS_SUCCESS;
}
static VAStatus nvCreateContext(
VADriverContextP ctx,
VAConfigID config_id,
int picture_width,
int picture_height,
int flag,
VASurfaceID *render_targets,
int num_render_targets,
VAContextID *context /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVConfig *cfg = (NVConfig*) getObjectPtr(drv, config_id);
if (cfg == NULL) {
return VA_STATUS_ERROR_INVALID_CONFIG;
}
LOG("creating context with %d render targets, %d surfaces, at %dx%d", num_render_targets, drv->surfaceCount, picture_width, picture_height);
//find the codec they've selected
const NVCodec *selectedCodec = NULL;
for (const NVCodec *c = __start_nvd_codecs; c < __stop_nvd_codecs; c++) {
for (int i = 0; i < c->supportedProfileCount; i++) {
if (c->supportedProfiles[i] == cfg->profile) {
selectedCodec = c;
break;
}
}
}
if (selectedCodec == NULL) {
LOG("Unable to find codec for profile: %d", cfg->profile);
return VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
}
if (num_render_targets) {
// Update the decoder configuration to match the passed in surfaces.
NVSurface *surface = (NVSurface *) getObjectPtr(drv, render_targets[0]);
cfg->surfaceFormat = surface->format;
cfg->chromaFormat = surface->chromaFormat;
cfg->bitDepth = surface->bitDepth;
}
if (drv->surfaceCount == 0 && num_render_targets == 0) {
LOG("0 surfaces have been passed to vaCreateContext, this might cause errors. Setting surface count to 32");
num_render_targets = 32;
}
int surfaceCount = drv->surfaceCount != 0 ? drv->surfaceCount : num_render_targets;
if (surfaceCount > 32) {
LOG("Application requested %d surface(s), limiting to 32. This may cause issues.", surfaceCount);
surfaceCount = 32;
}
CUVIDDECODECREATEINFO vdci = {
.ulWidth = vdci.ulMaxWidth = vdci.ulTargetWidth = picture_width,
.ulHeight = vdci.ulMaxHeight = vdci.ulTargetHeight = picture_height,
.CodecType = cfg->cudaCodec,
.ulCreationFlags = cudaVideoCreate_PreferCUVID,
.ulIntraDecodeOnly = 0, //TODO (flag & VA_PROGRESSIVE) != 0
.display_area.right = picture_width,
.display_area.bottom = picture_height,
.ChromaFormat = cfg->chromaFormat,
.OutputFormat = cfg->surfaceFormat,
.bitDepthMinus8 = cfg->bitDepth - 8,
.DeinterlaceMode = cudaVideoDeinterlaceMode_Weave,
//we only ever map one frame at a time, so we can set this to 1
//it isn't particually efficient to do this, but it is simple
.ulNumOutputSurfaces = 1,
//just allocate as many surfaces as have been created since we can never have as much information as the decode to guess correctly
.ulNumDecodeSurfaces = surfaceCount,
};
//reset this to 0 as there are some cases where the context will be destroyed but not terminated, meaning if it's initialised again
//we'll have even more surfaces
drv->surfaceCount = 0;
CHECK_CUDA_RESULT_RETURN(cv->cuvidCtxLockCreate(&vdci.vidLock, drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
CUvideodecoder decoder;
CHECK_CUDA_RESULT_RETURN(cv->cuvidCreateDecoder(&decoder, &vdci), VA_STATUS_ERROR_ALLOCATION_FAILED);
Object contextObj = allocateObject(drv, OBJECT_TYPE_CONTEXT, sizeof(NVContext));
NVContext *nvCtx = (NVContext*) contextObj->obj;
nvCtx->drv = drv;
nvCtx->decoder = decoder;
nvCtx->profile = cfg->profile;
nvCtx->entrypoint = cfg->entrypoint;
nvCtx->width = picture_width;
nvCtx->height = picture_height;
nvCtx->codec = selectedCodec;
pthread_mutexattr_t attrib;
pthread_mutexattr_init(&attrib);
pthread_mutexattr_settype(&attrib, PTHREAD_MUTEX_RECURSIVE);
pthread_mutex_init(&nvCtx->surfaceCreationMutex, &attrib);
pthread_mutex_init(&nvCtx->resolveMutex, NULL);
pthread_cond_init(&nvCtx->resolveCondition, NULL);
int err = pthread_create(&nvCtx->resolveThread, NULL, &resolveSurfaces, nvCtx);
if (err != 0) {
LOG("Unable to create resolve thread: %d", err);
deleteObject(drv, contextObj->id);
return VA_STATUS_ERROR_OPERATION_FAILED;
}
*context = contextObj->id;
return VA_STATUS_SUCCESS;
}
static VAStatus nvDestroyContext(
VADriverContextP ctx,
VAContextID context)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
LOG("Destroying context: %d", context);
NVContext *nvCtx = (NVContext*) getObjectPtr(drv, context);
if (nvCtx == NULL) {
return VA_STATUS_ERROR_INVALID_CONTEXT;
}
VAStatus ret = VA_STATUS_SUCCESS;
if (!destroyContext(drv, nvCtx)) {
ret = VA_STATUS_ERROR_OPERATION_FAILED;
}
deleteObject(drv, context);
return ret;
}
static VAStatus nvCreateBuffer(
VADriverContextP ctx,
VAContextID context, /* in */
VABufferType type, /* in */
unsigned int size, /* in */
unsigned int num_elements, /* in */
void *data, /* in */
VABufferID *buf_id
)
{
//LOG("got buffer %p, type %x, size %u, elements %u", data, type, size, num_elements);
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVContext *nvCtx = (NVContext*) getObjectPtr(drv, context);
if (nvCtx == NULL) {
return VA_STATUS_ERROR_INVALID_CONTEXT;
}
//HACK: This is an awful hack to support VP8 videos when running within FFMPEG.
//VA-API doesn't pass enough information for NVDEC to work with, but the information is there
//just before the start of the buffer that was passed to us.
int offset = 0;
if (nvCtx->profile == VAProfileVP8Version0_3 && type == VASliceDataBufferType) {
offset = (int) (((uintptr_t) data) & 0xf);
data = ((char *) data) - offset;
size += offset;
}
//TODO should pool these as most of the time these should be the same size
Object bufferObject = allocateObject(drv, OBJECT_TYPE_BUFFER, sizeof(NVBuffer));
*buf_id = bufferObject->id;
NVBuffer *buf = (NVBuffer*) bufferObject->obj;
buf->bufferType = type;
buf->elements = num_elements;
buf->size = num_elements * size;
buf->ptr = memalign(16, buf->size);
buf->offset = offset;
if (buf->ptr == NULL) {
LOG("Unable to allocate buffer of %d bytes", buf->size);
return VA_STATUS_ERROR_ALLOCATION_FAILED;
}
if (data != NULL)
{
memcpy(buf->ptr, data, buf->size);
}
return VA_STATUS_SUCCESS;
}
static VAStatus nvBufferSetNumElements(
VADriverContextP ctx,
VABufferID buf_id, /* in */
unsigned int num_elements /* in */
)
{
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvMapBuffer(
VADriverContextP ctx,
VABufferID buf_id, /* in */
void **pbuf /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVBuffer *buf = getObjectPtr(drv, buf_id);
if (buf == NULL) {
return VA_STATUS_ERROR_INVALID_BUFFER;
}
*pbuf = buf->ptr;
return VA_STATUS_SUCCESS;
}
static VAStatus nvUnmapBuffer(
VADriverContextP ctx,
VABufferID buf_id /* in */
)
{
return VA_STATUS_SUCCESS;
}
static VAStatus nvDestroyBuffer(
VADriverContextP ctx,
VABufferID buffer_id
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVBuffer *buf = getObjectPtr(drv, buffer_id);
if (buf == NULL) {
return VA_STATUS_ERROR_INVALID_BUFFER;
}
if (buf->ptr != NULL) {
free(buf->ptr);
}
deleteObject(drv, buffer_id);
return VA_STATUS_SUCCESS;
}
static VAStatus nvBeginPicture(
VADriverContextP ctx,
VAContextID context,
VASurfaceID render_target
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVContext *nvCtx = (NVContext*) getObjectPtr(drv, context);
NVSurface *surface = (NVSurface*) getObjectPtr(drv, render_target);
if (surface == NULL) {
return VA_STATUS_ERROR_INVALID_SURFACE;
}
if (surface->context != NULL && surface->context != nvCtx) {
//this surface was last used on a different context, we need to free up the backing image (it might not be the correct size)
if (surface->backingImage != NULL) {
drv->backend->detachBackingImageFromSurface(drv, surface);
}
//...and reset the pictureIdx
surface->pictureIdx = -1;
}
//if this surface hasn't been used before, give it a new picture index
if (surface->pictureIdx == -1) {
surface->pictureIdx = nvCtx->currentPictureId++;
}
//I don't know if we actually need to lock here, nothing should be waiting
//until after this function returns...
pthread_mutex_lock(&surface->mutex);
surface->resolving = 1;
pthread_mutex_unlock(&surface->mutex);
memset(&nvCtx->pPicParams, 0, sizeof(CUVIDPICPARAMS));
nvCtx->renderTarget = surface;
nvCtx->renderTarget->progressiveFrame = true; //assume we're producing progressive frame unless the codec says otherwise
nvCtx->pPicParams.CurrPicIdx = nvCtx->renderTarget->pictureIdx;
return VA_STATUS_SUCCESS;
}
static VAStatus nvRenderPicture(
VADriverContextP ctx,
VAContextID context,
VABufferID *buffers,
int num_buffers
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVContext *nvCtx = (NVContext*) getObjectPtr(drv, context);
if (nvCtx == NULL) {
return VA_STATUS_ERROR_INVALID_CONTEXT;
}
CUVIDPICPARAMS *picParams = &nvCtx->pPicParams;
for (int i = 0; i < num_buffers; i++) {
NVBuffer *buf = (NVBuffer*) getObject(drv, buffers[i])->obj;
if (buf == NULL || buf->ptr == NULL) {
LOG("Invalid buffer detected, skipping: %d", buffers[i]);
continue;
}
HandlerFunc func = nvCtx->codec->handlers[buf->bufferType];
if (func != NULL) {
func(nvCtx, buf, picParams);
} else {
LOG("Unhandled buffer type: %d", buf->bufferType);
}
}
return VA_STATUS_SUCCESS;
}
static VAStatus nvEndPicture(
VADriverContextP ctx,
VAContextID context
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVContext *nvCtx = (NVContext*) getObject(drv, context)->obj;
if (nvCtx == NULL) {
return VA_STATUS_ERROR_INVALID_CONTEXT;
}
CUVIDPICPARAMS *picParams = &nvCtx->pPicParams;
picParams->pBitstreamData = nvCtx->bitstreamBuffer.buf;
picParams->pSliceDataOffsets = nvCtx->sliceOffsets.buf;
nvCtx->bitstreamBuffer.size = 0;
nvCtx->sliceOffsets.size = 0;
CUresult result = cv->cuvidDecodePicture(nvCtx->decoder, picParams);
if (result != CUDA_SUCCESS)
{
LOG("cuvidDecodePicture failed: %d", result);
return VA_STATUS_ERROR_DECODING_ERROR;
}
//LOG("Decoded frame successfully to idx: %d (%p)", picParams->CurrPicIdx, nvCtx->renderTarget);
NVSurface *surface = nvCtx->renderTarget;
surface->context = nvCtx;
surface->topFieldFirst = !picParams->bottom_field_flag;
surface->secondField = picParams->second_field;
//TODO check we're not overflowing the queue
pthread_mutex_lock(&nvCtx->resolveMutex);
nvCtx->surfaceQueue[nvCtx->surfaceQueueWriteIdx++] = nvCtx->renderTarget;
if (nvCtx->surfaceQueueWriteIdx >= SURFACE_QUEUE_SIZE) {
nvCtx->surfaceQueueWriteIdx = 0;
}
pthread_mutex_unlock(&nvCtx->resolveMutex);
//Wake up the resolve thread
pthread_cond_signal(&nvCtx->resolveCondition);
return VA_STATUS_SUCCESS;
}
static VAStatus nvSyncSurface(
VADriverContextP ctx,
VASurfaceID render_target
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVSurface *surface = getObjectPtr(drv, render_target);
if (surface == NULL) {
return VA_STATUS_ERROR_INVALID_SURFACE;
}
//LOG("Syncing on surface: %d (%p)", surface->pictureIdx, surface);
//wait for resolve to occur before synchronising
pthread_mutex_lock(&surface->mutex);
if (surface->resolving) {
//LOG("Surface %d not resolved, waiting", surface->pictureIdx);
pthread_cond_wait(&surface->cond, &surface->mutex);
}
pthread_mutex_unlock(&surface->mutex);
//LOG("Surface %d resolved (%p)", surface->pictureIdx, surface);
return VA_STATUS_SUCCESS;
}
static VAStatus nvQuerySurfaceStatus(
VADriverContextP ctx,
VASurfaceID render_target,
VASurfaceStatus *status /* out */
)
{
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvQuerySurfaceError(
VADriverContextP ctx,
VASurfaceID render_target,
VAStatus error_status,
void **error_info /*out*/
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvPutSurface(
VADriverContextP ctx,
VASurfaceID surface,
void* draw, /* Drawable of window system */
short srcx,
short srcy,
unsigned short srcw,
unsigned short srch,
short destx,
short desty,
unsigned short destw,
unsigned short desth,
VARectangle *cliprects, /* client supplied clip list */
unsigned int number_cliprects, /* number of clip rects in the clip list */
unsigned int flags /* de-interlacing flags */
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvQueryImageFormats(
VADriverContextP ctx,
VAImageFormat *format_list, /* out */
int *num_formats /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
LOG("In %s", __func__);
*num_formats = 0;
for (unsigned int i = NV_FORMAT_NONE + 1; i < ARRAY_SIZE(formatsInfo); i++) {
if (formatsInfo[i].is16bits && !drv->supports16BitSurface) {
continue;
}
if (formatsInfo[i].isYuv444 && !drv->supports444Surface) {
continue;
}
format_list[(*num_formats)++] = formatsInfo[i].vaFormat;
}
return VA_STATUS_SUCCESS;
}
static VAStatus nvCreateImage(
VADriverContextP ctx,
VAImageFormat *format,
int width,
int height,
VAImage *image /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVFormat nvFormat = nvFormatFromVaFormat(format->fourcc);
const NVFormatInfo *fmtInfo = &formatsInfo[nvFormat];
const NVFormatPlane *p = fmtInfo->plane;
if (nvFormat == NV_FORMAT_NONE) {
return VA_STATUS_ERROR_INVALID_IMAGE_FORMAT;
}
Object imageObj = allocateObject(drv, OBJECT_TYPE_IMAGE, sizeof(NVImage));
image->image_id = imageObj->id;
LOG("created image id: %d", imageObj->id);
NVImage *img = (NVImage*) imageObj->obj;
img->width = width;
img->height = height;
img->format = nvFormat;
//allocate buffer to hold image when we copy down from the GPU
//TODO could probably put these in a pool, they appear to be allocated, used, then freed
Object imageBufferObject = allocateObject(drv, OBJECT_TYPE_BUFFER, sizeof(NVBuffer));
NVBuffer *imageBuffer = (NVBuffer*) imageBufferObject->obj;
imageBuffer->bufferType = VAImageBufferType;
imageBuffer->size = 0;
for (uint32_t i = 0; i < fmtInfo->numPlanes; i++) {
imageBuffer->size += ((width * height) >> (p[i].ss.x + p[i].ss.y)) * fmtInfo->bppc * p[i].channelCount;
}
imageBuffer->elements = 1;
imageBuffer->ptr = memalign(16, imageBuffer->size);
img->imageBuffer = imageBuffer;
memcpy(&image->format, format, sizeof(VAImageFormat));
image->buf = imageBufferObject->id; /* image data buffer */
/*
* Image data will be stored in a buffer of type VAImageBufferType to facilitate
* data store on the server side for optimal performance. The buffer will be
* created by the CreateImage function, and proper storage allocated based on the image
* size and format. This buffer is managed by the library implementation, and
* accessed by the client through the buffer Map/Unmap functions.
*/
image->width = width;
image->height = height;
image->data_size = imageBuffer->size;
image->num_planes = fmtInfo->numPlanes; /* can not be greater than 3 */
/*
* An array indicating the scanline pitch in bytes for each plane.
* Each plane may have a different pitch. Maximum 3 planes for planar formats
*/
image->pitches[0] = width * fmtInfo->bppc;
image->pitches[1] = width * fmtInfo->bppc;
image->pitches[2] = width * fmtInfo->bppc;
/*
* An array indicating the byte offset from the beginning of the image data
* to the start of each plane.
*/
image->offsets[0] = 0;
image->offsets[1] = image->offsets[0] + ((width * height) >> (p[0].ss.x + p[0].ss.y)) * fmtInfo->bppc * p[0].channelCount;
image->offsets[2] = image->offsets[1] + ((width * height) >> (p[1].ss.x + p[1].ss.y)) * fmtInfo->bppc * p[1].channelCount;
return VA_STATUS_SUCCESS;
}
static VAStatus nvDeriveImage(
VADriverContextP ctx,
VASurfaceID surface,
VAImage *image /* out */
)
{
LOG("In %s", __func__);
//FAILED because we don't support it
return VA_STATUS_ERROR_OPERATION_FAILED;
}
static VAStatus nvDestroyImage(
VADriverContextP ctx,
VAImageID image
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVImage *img = (NVImage*) getObjectPtr(drv, image);
if (img == NULL) {
return VA_STATUS_ERROR_INVALID_IMAGE;
}
Object imageBufferObj = getObjectByPtr(drv, img->imageBuffer);
if (imageBufferObj != NULL) {
if (img->imageBuffer->ptr != NULL) {
free(img->imageBuffer->ptr);
}
deleteObject(drv, imageBufferObj->id);
}
deleteObject(drv, image);
return VA_STATUS_SUCCESS;
}
static VAStatus nvSetImagePalette(
VADriverContextP ctx,
VAImageID image,
/*
* pointer to an array holding the palette data. The size of the array is
* num_palette_entries * entry_bytes in size. The order of the components
* in the palette is described by the component_order in VAImage struct
*/
unsigned char *palette
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvGetImage(
VADriverContextP ctx,
VASurfaceID surface,
int x, /* coordinates of the upper left source pixel */
int y,
unsigned int width, /* width and height of the region */
unsigned int height,
VAImageID image
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVSurface *surfaceObj = (NVSurface*) getObject(drv, surface)->obj;
NVImage *imageObj = (NVImage*) getObject(drv, image)->obj;
NVContext *context = (NVContext*) surfaceObj->context;
const NVFormatInfo *fmtInfo = &formatsInfo[imageObj->format];
uint32_t offset = 0;
if (context == NULL) {
return VA_STATUS_ERROR_INVALID_CONTEXT;
}
//wait for the surface to be decoded
nvSyncSurface(ctx, surface);
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
for (uint32_t i = 0; i < fmtInfo->numPlanes; i++) {
const NVFormatPlane *p = &fmtInfo->plane[i];
CUDA_MEMCPY2D memcpy2d = {
.srcXInBytes = 0, .srcY = 0,
.srcMemoryType = CU_MEMORYTYPE_ARRAY,
.srcArray = surfaceObj->backingImage->arrays[i],
.dstXInBytes = 0, .dstY = 0,
.dstMemoryType = CU_MEMORYTYPE_HOST,
.dstHost = (char *)imageObj->imageBuffer->ptr + offset,
.dstPitch = width * fmtInfo->bppc,
.WidthInBytes = (width >> p->ss.x) * fmtInfo->bppc * p->channelCount,
.Height = height >> p->ss.y
};
CUresult result = cu->cuMemcpy2D(&memcpy2d);
if (result != CUDA_SUCCESS)
{
LOG("cuMemcpy2D failed: %d", result);
return VA_STATUS_ERROR_DECODING_ERROR;
}
offset += ((width * height) >> (p->ss.x + p->ss.y)) * fmtInfo->bppc * p->channelCount;
}
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPopCurrent(NULL), VA_STATUS_ERROR_OPERATION_FAILED);
return VA_STATUS_SUCCESS;
}
static VAStatus nvPutImage(
VADriverContextP ctx,
VASurfaceID surface,
VAImageID image,
int src_x,
int src_y,
unsigned int src_width,
unsigned int src_height,
int dest_x,
int dest_y,
unsigned int dest_width,
unsigned int dest_height
)
{
LOG("In %s", __func__);
return VA_STATUS_SUCCESS;
}
static VAStatus nvQuerySubpictureFormats(
VADriverContextP ctx,
VAImageFormat *format_list, /* out */
unsigned int *flags, /* out */
unsigned int *num_formats /* out */
)
{
LOG("In %s", __func__);
*num_formats = 0;
return VA_STATUS_SUCCESS;
}
static VAStatus nvCreateSubpicture(
VADriverContextP ctx,
VAImageID image,
VASubpictureID *subpicture /* out */
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvDestroySubpicture(
VADriverContextP ctx,
VASubpictureID subpicture
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvSetSubpictureImage(
VADriverContextP ctx,
VASubpictureID subpicture,
VAImageID image
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvSetSubpictureChromakey(
VADriverContextP ctx,
VASubpictureID subpicture,
unsigned int chromakey_min,
unsigned int chromakey_max,
unsigned int chromakey_mask
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvSetSubpictureGlobalAlpha(
VADriverContextP ctx,
VASubpictureID subpicture,
float global_alpha
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvAssociateSubpicture(
VADriverContextP ctx,
VASubpictureID subpicture,
VASurfaceID *target_surfaces,
int num_surfaces,
short src_x, /* upper left offset in subpicture */
short src_y,
unsigned short src_width,
unsigned short src_height,
short dest_x, /* upper left offset in surface */
short dest_y,
unsigned short dest_width,
unsigned short dest_height,
/*
* whether to enable chroma-keying or global-alpha
* see VA_SUBPICTURE_XXX values
*/
unsigned int flags
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvDeassociateSubpicture(
VADriverContextP ctx,
VASubpictureID subpicture,
VASurfaceID *target_surfaces,
int num_surfaces
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvQueryDisplayAttributes(
VADriverContextP ctx,
VADisplayAttribute *attr_list, /* out */
int *num_attributes /* out */
)
{
LOG("In %s", __func__);
*num_attributes = 0;
return VA_STATUS_SUCCESS;
}
static VAStatus nvGetDisplayAttributes(
VADriverContextP ctx,
VADisplayAttribute *attr_list, /* in/out */
int num_attributes
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvSetDisplayAttributes(
VADriverContextP ctx,
VADisplayAttribute *attr_list,
int num_attributes
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvQuerySurfaceAttributes(
VADriverContextP ctx,
VAConfigID config,
VASurfaceAttrib *attrib_list,
unsigned int *num_attribs
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
NVConfig *cfg = (NVConfig*) getObjectPtr(drv, config);
if (cfg == NULL) {
return VA_STATUS_ERROR_INVALID_CONFIG;
}
LOG("with %d (%d) %p %d", cfg->cudaCodec, cfg->bitDepth, attrib_list, *num_attribs);
if (cfg->chromaFormat != cudaVideoChromaFormat_420 && cfg->chromaFormat != cudaVideoChromaFormat_444) {
//TODO not sure what pixel formats are needed for 422 formats
LOG("Unknown chrome format: %d", cfg->chromaFormat);
return VA_STATUS_ERROR_INVALID_CONFIG;
}
if ((cfg->chromaFormat == cudaVideoChromaFormat_444 || cfg->surfaceFormat == cudaVideoSurfaceFormat_YUV444_16Bit) && !drv->supports444Surface) {
//TODO not sure what pixel formats are needed for 422 and 444 formats
LOG("YUV444 surfaces not supported: %d", cfg->chromaFormat);
return VA_STATUS_ERROR_INVALID_CONFIG;
}
if (cfg->surfaceFormat == cudaVideoSurfaceFormat_P016 && !drv->supports16BitSurface) {
//TODO not sure what pixel formats are needed for 422 and 444 formats
LOG("16 bits surfaces not supported: %d", cfg->chromaFormat);
return VA_STATUS_ERROR_INVALID_CONFIG;
}
if (num_attribs != NULL) {
int cnt = 4;
if (cfg->chromaFormat == cudaVideoChromaFormat_444) {
cnt += 1;
#if VA_CHECK_VERSION(1, 20, 0)
cnt += 1;
#endif
} else {
cnt += 1;
if (drv->supports16BitSurface) {
cnt += 3;
}
}
*num_attribs = cnt;
}
if (attrib_list != NULL) {
CUVIDDECODECAPS videoDecodeCaps = {
.eCodecType = cfg->cudaCodec,
.eChromaFormat = cfg->chromaFormat,
.nBitDepthMinus8 = cfg->bitDepth - 8
};
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
CHECK_CUDA_RESULT_RETURN(cv->cuvidGetDecoderCaps(&videoDecodeCaps), VA_STATUS_ERROR_OPERATION_FAILED);
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPopCurrent(NULL), VA_STATUS_ERROR_OPERATION_FAILED);
attrib_list[0].type = VASurfaceAttribMinWidth;
attrib_list[0].flags = 0;
attrib_list[0].value.type = VAGenericValueTypeInteger;
attrib_list[0].value.value.i = videoDecodeCaps.nMinWidth;
attrib_list[1].type = VASurfaceAttribMinHeight;
attrib_list[1].flags = 0;
attrib_list[1].value.type = VAGenericValueTypeInteger;
attrib_list[1].value.value.i = videoDecodeCaps.nMinHeight;
attrib_list[2].type = VASurfaceAttribMaxWidth;
attrib_list[2].flags = 0;
attrib_list[2].value.type = VAGenericValueTypeInteger;
attrib_list[2].value.value.i = videoDecodeCaps.nMaxWidth;
attrib_list[3].type = VASurfaceAttribMaxHeight;
attrib_list[3].flags = 0;
attrib_list[3].value.type = VAGenericValueTypeInteger;
attrib_list[3].value.value.i = videoDecodeCaps.nMaxHeight;
LOG("Returning constraints: width: %d - %d, height: %d - %d", attrib_list[0].value.value.i, attrib_list[2].value.value.i, attrib_list[1].value.value.i, attrib_list[3].value.value.i);
int attrib_idx = 4;
/* returning all the surfaces here probably isn't the best thing we could do
* but we don't always have enough information to determine exactly which
* pixel formats should be used (for instance, AV1 10-bit videos) */
if (cfg->chromaFormat == cudaVideoChromaFormat_444) {
attrib_list[attrib_idx].type = VASurfaceAttribPixelFormat;
attrib_list[attrib_idx].flags = 0;
attrib_list[attrib_idx].value.type = VAGenericValueTypeInteger;
attrib_list[attrib_idx].value.value.i = VA_FOURCC_444P;
attrib_idx += 1;
#if VA_CHECK_VERSION(1, 20, 0)
attrib_list[attrib_idx].type = VASurfaceAttribPixelFormat;
attrib_list[attrib_idx].flags = 0;
attrib_list[attrib_idx].value.type = VAGenericValueTypeInteger;
attrib_list[attrib_idx].value.value.i = VA_FOURCC_Q416;
attrib_idx += 1;
#endif
} else {
attrib_list[attrib_idx].type = VASurfaceAttribPixelFormat;
attrib_list[attrib_idx].flags = 0;
attrib_list[attrib_idx].value.type = VAGenericValueTypeInteger;
attrib_list[attrib_idx].value.value.i = VA_FOURCC_NV12;
attrib_idx += 1;
if (drv->supports16BitSurface) {
attrib_list[attrib_idx].type = VASurfaceAttribPixelFormat;
attrib_list[attrib_idx].flags = 0;
attrib_list[attrib_idx].value.type = VAGenericValueTypeInteger;
attrib_list[attrib_idx].value.value.i = VA_FOURCC_P010;
attrib_idx += 1;
attrib_list[attrib_idx].type = VASurfaceAttribPixelFormat;
attrib_list[attrib_idx].flags = 0;
attrib_list[attrib_idx].value.type = VAGenericValueTypeInteger;
attrib_list[attrib_idx].value.value.i = VA_FOURCC_P012;
attrib_idx += 1;
attrib_list[attrib_idx].type = VASurfaceAttribPixelFormat;
attrib_list[attrib_idx].flags = 0;
attrib_list[attrib_idx].value.type = VAGenericValueTypeInteger;
attrib_list[attrib_idx].value.value.i = VA_FOURCC_P016;
attrib_idx += 1;
}
}
}
return VA_STATUS_SUCCESS;
}
/* used by va trace */
static VAStatus nvBufferInfo(
VADriverContextP ctx, /* in */
VABufferID buf_id, /* in */
VABufferType *type, /* out */
unsigned int *size, /* out */
unsigned int *num_elements /* out */
)
{
LOG("In %s", __func__);
*size=0;
*num_elements=0;
return VA_STATUS_SUCCESS;
}
static VAStatus nvAcquireBufferHandle(
VADriverContextP ctx,
VABufferID buf_id, /* in */
VABufferInfo * buf_info /* in/out */
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvReleaseBufferHandle(
VADriverContextP ctx,
VABufferID buf_id /* in */
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
// /* lock/unlock surface for external access */
static VAStatus nvLockSurface(
VADriverContextP ctx,
VASurfaceID surface,
unsigned int *fourcc, /* out for follow argument */
unsigned int *luma_stride,
unsigned int *chroma_u_stride,
unsigned int *chroma_v_stride,
unsigned int *luma_offset,
unsigned int *chroma_u_offset,
unsigned int *chroma_v_offset,
unsigned int *buffer_name, /* if it is not NULL, assign the low lever
* surface buffer name
*/
void **buffer /* if it is not NULL, map the surface buffer for
* CPU access
*/
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvUnlockSurface(
VADriverContextP ctx,
VASurfaceID surface
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvCreateMFContext(
VADriverContextP ctx,
VAMFContextID *mfe_context /* out */
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvMFAddContext(
VADriverContextP ctx,
VAMFContextID mf_context,
VAContextID context
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvMFReleaseContext(
VADriverContextP ctx,
VAMFContextID mf_context,
VAContextID context
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvMFSubmit(
VADriverContextP ctx,
VAMFContextID mf_context,
VAContextID *contexts,
int num_contexts
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvCreateBuffer2(
VADriverContextP ctx,
VAContextID context, /* in */
VABufferType type, /* in */
unsigned int width, /* in */
unsigned int height, /* in */
unsigned int *unit_size, /* out */
unsigned int *pitch, /* out */
VABufferID *buf_id /* out */
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvQueryProcessingRate(
VADriverContextP ctx, /* in */
VAConfigID config_id, /* in */
VAProcessingRateParameter *proc_buf,/* in */
unsigned int *processing_rate /* out */
)
{
LOG("In %s", __func__);
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
static VAStatus nvExportSurfaceHandle(
VADriverContextP ctx,
VASurfaceID surface_id, /* in */
uint32_t mem_type, /* in */
uint32_t flags, /* in */
void *descriptor /* out */
)
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
if ((mem_type & VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME_2) == 0) {
return VA_STATUS_ERROR_UNSUPPORTED_MEMORY_TYPE;
}
if ((flags & VA_EXPORT_SURFACE_SEPARATE_LAYERS) == 0) {
return VA_STATUS_ERROR_INVALID_SURFACE;
}
NVSurface *surface = (NVSurface*) getObjectPtr(drv, surface_id);
if (surface == NULL) {
return VA_STATUS_ERROR_INVALID_SURFACE;
}
//LOG("Exporting surface: %d (%p)", surface->pictureIdx, surface);
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
if (!drv->backend->realiseSurface(drv, surface)) {
LOG("Unable to export surface");
return VA_STATUS_ERROR_ALLOCATION_FAILED;
}
VADRMPRIMESurfaceDescriptor *ptr = (VADRMPRIMESurfaceDescriptor*) descriptor;
drv->backend->fillExportDescriptor(drv, surface, ptr);
// LOG("Exporting with w:%d h:%d o:%d p:%d m:%" PRIx64 " o:%d p:%d m:%" PRIx64, ptr->width, ptr->height, ptr->layers[0].offset[0],
// ptr->layers[0].pitch[0], ptr->objects[0].drm_format_modifier,
// ptr->layers[1].offset[0], ptr->layers[1].pitch[0],
// ptr->objects[1].drm_format_modifier);
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPopCurrent(NULL), VA_STATUS_ERROR_OPERATION_FAILED);
return VA_STATUS_SUCCESS;
}
static VAStatus nvTerminate( VADriverContextP ctx )
{
NVDriver *drv = (NVDriver*) ctx->pDriverData;
LOG("Terminating %p", ctx);
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPushCurrent(drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
drv->backend->destroyAllBackingImage(drv);
deleteAllObjects(drv);
drv->backend->releaseExporter(drv);
CHECK_CUDA_RESULT_RETURN(cu->cuCtxPopCurrent(NULL), VA_STATUS_ERROR_OPERATION_FAILED);
pthread_mutex_lock(&concurrency_mutex);
instances--;
LOG("Now have %d (%d max) instances", instances, max_instances);
pthread_mutex_unlock(&concurrency_mutex);
CHECK_CUDA_RESULT_RETURN(cu->cuCtxDestroy(drv->cudaContext), VA_STATUS_ERROR_OPERATION_FAILED);
drv->cudaContext = NULL;
return VA_STATUS_SUCCESS;
}
extern const NVBackend DIRECT_BACKEND;
extern const NVBackend EGL_BACKEND;
#define VTABLE(func) .va ## func = &nv ## func
static const struct VADriverVTable vtable = {
VTABLE(Terminate),
VTABLE(QueryConfigProfiles),
VTABLE(QueryConfigEntrypoints),
VTABLE(QueryConfigAttributes),
VTABLE(CreateConfig),
VTABLE(DestroyConfig),
VTABLE(GetConfigAttributes),
VTABLE(CreateSurfaces),
VTABLE(CreateSurfaces2),
VTABLE(DestroySurfaces),
VTABLE(CreateContext),
VTABLE(DestroyContext),
VTABLE(CreateBuffer),
VTABLE(BufferSetNumElements),
VTABLE(MapBuffer),
VTABLE(UnmapBuffer),
VTABLE(DestroyBuffer),
VTABLE(BeginPicture),
VTABLE(RenderPicture),
VTABLE(EndPicture),
VTABLE(SyncSurface),
VTABLE(QuerySurfaceStatus),
VTABLE(QuerySurfaceError),
VTABLE(PutSurface),
VTABLE(QueryImageFormats),
VTABLE(CreateImage),
VTABLE(DeriveImage),
VTABLE(DestroyImage),
VTABLE(SetImagePalette),
VTABLE(GetImage),
VTABLE(PutImage),
VTABLE(QuerySubpictureFormats),
VTABLE(CreateSubpicture),
VTABLE(DestroySubpicture),
VTABLE(SetSubpictureImage),
VTABLE(SetSubpictureChromakey),
VTABLE(SetSubpictureGlobalAlpha),
VTABLE(AssociateSubpicture),
VTABLE(DeassociateSubpicture),
VTABLE(QueryDisplayAttributes),
VTABLE(GetDisplayAttributes),
VTABLE(SetDisplayAttributes),
VTABLE(QuerySurfaceAttributes),
VTABLE(BufferInfo),
VTABLE(AcquireBufferHandle),
VTABLE(ReleaseBufferHandle),
VTABLE(LockSurface),
VTABLE(UnlockSurface),
VTABLE(CreateMFContext),
VTABLE(MFAddContext),
VTABLE(MFReleaseContext),
VTABLE(MFSubmit),
VTABLE(CreateBuffer2),
VTABLE(QueryProcessingRate),
VTABLE(ExportSurfaceHandle),
};
__attribute__((visibility("default")))
VAStatus __vaDriverInit_1_0(VADriverContextP ctx);
__attribute__((visibility("default")))
VAStatus __vaDriverInit_1_0(VADriverContextP ctx) {
LOG("Initialising NVIDIA VA-API Driver: %lX", ctx->display_type);
//drm_state can be passed in with any display type, including X11. But if it's X11, we don't
//want to use the fd as it'll likely be an Intel GPU, as NVIDIA doesn't support DRI3 at the moment
bool isDrm = ctx->drm_state != NULL && ((struct drm_state*) ctx->drm_state)->fd > 0 &&
(((ctx->display_type & VA_DISPLAY_MAJOR_MASK) == VA_DISPLAY_DRM) ||
((ctx->display_type & VA_DISPLAY_MAJOR_MASK) == VA_DISPLAY_WAYLAND));
pthread_mutex_lock(&concurrency_mutex);
LOG("Now have %d (%d max) instances", instances, max_instances);
if (max_instances > 0 && instances >= max_instances) {
pthread_mutex_unlock(&concurrency_mutex);
return VA_STATUS_ERROR_HW_BUSY;
}
instances++;
pthread_mutex_unlock(&concurrency_mutex);
//check to make sure we initialised the CUDA functions correctly
if (cu == NULL || cv == NULL) {
return VA_STATUS_ERROR_OPERATION_FAILED;
}
NVDriver *drv = (NVDriver*) calloc(1, sizeof(NVDriver));
ctx->pDriverData = drv;
drv->cu = cu;
drv->cv = cv;
drv->useCorrectNV12Format = true;
drv->cudaGpuId = gpu;
//make sure that we want the default GPU, and that a DRM fd that we care about is passed in
drv->drmFd = (gpu == -1 && isDrm && ctx->drm_state != NULL) ? ((struct drm_state*) ctx->drm_state)->fd : -1;
if (backend == EGL) {
LOG("Selecting EGL backend");
drv->backend = &EGL_BACKEND;
} else if (backend == DIRECT) {
LOG("Selecting Direct backend");
drv->backend = &DIRECT_BACKEND;
}
ctx->max_profiles = MAX_PROFILES;
ctx->max_entrypoints = 1;
ctx->max_attributes = 1;
ctx->max_display_attributes = 1;
ctx->max_image_formats = ARRAY_SIZE(formatsInfo) - 1;
ctx->max_subpic_formats = 1;
if (backend == DIRECT) {
ctx->str_vendor = "VA-API NVDEC driver [direct backend]";
} else if (backend == EGL) {
ctx->str_vendor = "VA-API NVDEC driver [egl backend]";
}
pthread_mutexattr_t attrib;
pthread_mutexattr_init(&attrib);
pthread_mutexattr_settype(&attrib, PTHREAD_MUTEX_RECURSIVE);
pthread_mutex_init(&drv->objectCreationMutex, &attrib);
pthread_mutex_init(&drv->imagesMutex, &attrib);
pthread_mutex_init(&drv->exportMutex, NULL);
if (!drv->backend->initExporter(drv)) {
LOG("Exporter failed");
free(drv);
return VA_STATUS_ERROR_OPERATION_FAILED;
}
if (CHECK_CUDA_RESULT(cu->cuCtxCreate(&drv->cudaContext, CU_CTX_SCHED_BLOCKING_SYNC, drv->cudaGpuId))) {
drv->backend->releaseExporter(drv);
free(drv);
return VA_STATUS_ERROR_OPERATION_FAILED;
}
*ctx->vtable = vtable;
return VA_STATUS_SUCCESS;
}
0707010000003F000081A4000000000000000000000001663926A700001C42000000000000000000000000000000000000002B00000000nvidia-vaapi-driver-0.0.12/src/vabackend.h#ifndef VABACKEND_H
#define VABACKEND_H
#include <ffnvcodec/dynlink_loader.h>
#include <va/va_backend.h>
#include <EGL/egl.h>
#include <EGL/eglext.h>
#include <stdbool.h>
#include <va/va_drmcommon.h>
#include <pthread.h>
#include "list.h"
#include "direct/nv-driver.h"
#include "common.h"
#define SURFACE_QUEUE_SIZE 16
#define MAX_IMAGE_COUNT 64
typedef struct {
void *buf;
uint64_t size;
uint64_t allocated;
} AppendableBuffer;
typedef enum
{
OBJECT_TYPE_CONFIG,
OBJECT_TYPE_CONTEXT,
OBJECT_TYPE_SURFACE,
OBJECT_TYPE_BUFFER,
OBJECT_TYPE_IMAGE
} ObjectType;
typedef struct Object_t
{
ObjectType type;
VAGenericID id;
void *obj;
} *Object;
typedef struct
{
unsigned int elements;
int size;
VABufferType bufferType;
void *ptr;
int offset;
} NVBuffer;
struct _NVContext;
struct _BackingImage;
typedef struct
{
uint32_t width;
uint32_t height;
cudaVideoSurfaceFormat format;
cudaVideoChromaFormat chromaFormat;
int bitDepth;
int pictureIdx;
struct _NVContext *context;
int progressiveFrame;
int topFieldFirst;
int secondField;
int order_hint; //needed for AV1
struct _BackingImage *backingImage;
int resolving;
pthread_mutex_t mutex;
pthread_cond_t cond;
} NVSurface;
typedef enum
{
NV_FORMAT_NONE,
NV_FORMAT_NV12,
NV_FORMAT_P010,
NV_FORMAT_P012,
NV_FORMAT_P016,
NV_FORMAT_444P,
NV_FORMAT_Q416
} NVFormat;
typedef struct
{
int width;
int height;
NVFormat format;
NVBuffer *imageBuffer;
} NVImage;
typedef struct {
CUexternalMemory extMem;
CUmipmappedArray mipmapArray;
} NVCudaImage;
typedef struct _BackingImage {
NVSurface *surface;
EGLImage image;
CUarray arrays[3];
uint32_t width;
uint32_t height;
int fourcc;
int fds[4];
int offsets[4];
int strides[4];
uint64_t mods[4];
uint32_t size[4];
//direct backend only
NVCudaImage cudaImages[3];
NVFormat format;
uint32_t totalSize;
CUexternalMemory extMem;
} BackingImage;
struct _NVDriver;
typedef struct {
const char *name;
bool (*initExporter)(struct _NVDriver *drv);
void (*releaseExporter)(struct _NVDriver *drv);
bool (*exportCudaPtr)(struct _NVDriver *drv, CUdeviceptr ptr, NVSurface *surface, uint32_t pitch);
void (*detachBackingImageFromSurface)(struct _NVDriver *drv, NVSurface *surface);
bool (*realiseSurface)(struct _NVDriver *drv, NVSurface *surface);
bool (*fillExportDescriptor)(struct _NVDriver *drv, NVSurface *surface, VADRMPRIMESurfaceDescriptor *desc);
void (*destroyAllBackingImage)(struct _NVDriver *drv);
} NVBackend;
typedef struct _NVDriver
{
CudaFunctions *cu;
CuvidFunctions *cv;
CUcontext cudaContext;
Array/*<Object>*/ objects;
pthread_mutex_t objectCreationMutex;
VAGenericID nextObjId;
bool useCorrectNV12Format;
bool supports16BitSurface;
bool supports444Surface;
int cudaGpuId;
int drmFd;
int surfaceCount;
pthread_mutex_t exportMutex;
pthread_mutex_t imagesMutex;
Array/*<NVEGLImage>*/ images;
const NVBackend *backend;
//fields for direct backend
NVDriverContext driverContext;
//fields for egl backend
EGLDeviceEXT eglDevice;
EGLDisplay eglDisplay;
EGLContext eglContext;
EGLStreamKHR eglStream;
CUeglStreamConnection cuStreamConnection;
int numFramesPresented;
} NVDriver;
struct _NVCodec;
typedef struct _NVContext
{
NVDriver *drv;
VAProfile profile;
VAEntrypoint entrypoint;
int width;
int height;
CUvideodecoder decoder;
NVSurface *renderTarget;
void *lastSliceParams;
unsigned int lastSliceParamsCount;
AppendableBuffer bitstreamBuffer;
AppendableBuffer sliceOffsets;
CUVIDPICPARAMS pPicParams;
const struct _NVCodec *codec;
int currentPictureId;
pthread_t resolveThread;
pthread_mutex_t resolveMutex;
pthread_cond_t resolveCondition;
NVSurface* surfaceQueue[SURFACE_QUEUE_SIZE];
int surfaceQueueReadIdx;
int surfaceQueueWriteIdx;
bool exiting;
pthread_mutex_t surfaceCreationMutex;
} NVContext;
typedef struct
{
VAProfile profile;
VAEntrypoint entrypoint;
cudaVideoSurfaceFormat surfaceFormat;
cudaVideoChromaFormat chromaFormat;
int bitDepth;
cudaVideoCodec cudaCodec;
} NVConfig;
typedef void (*HandlerFunc)(NVContext*, NVBuffer* , CUVIDPICPARAMS*);
typedef cudaVideoCodec (*ComputeCudaCodec)(VAProfile);
//padding/alignment is very important to this structure as it's placed in it's own section
//in the executable.
struct _NVCodec {
ComputeCudaCodec computeCudaCodec;
HandlerFunc handlers[VABufferTypeMax];
int supportedProfileCount;
const VAProfile *supportedProfiles;
};
typedef struct _NVCodec NVCodec;
typedef struct
{
uint32_t bppc; // bytes per pixel per channel
uint32_t numPlanes;
uint32_t fourcc;
bool is16bits;
bool isYuv444;
NVFormatPlane plane[3];
VAImageFormat vaFormat;
} NVFormatInfo;
extern const NVFormatInfo formatsInfo[];
void appendBuffer(AppendableBuffer *ab, const void *buf, uint64_t size);
int pictureIdxFromSurfaceId(NVDriver *ctx, VASurfaceID surf);
NVSurface* nvSurfaceFromSurfaceId(NVDriver *drv, VASurfaceID surf);
bool checkCudaErrors(CUresult err, const char *file, const char *function, const int line);
void logger(const char *filename, const char *function, int line, const char *msg, ...);
#define CHECK_CUDA_RESULT(err) checkCudaErrors(err, __FILE__, __func__, __LINE__)
#define CHECK_CUDA_RESULT_RETURN(err, ret) if (checkCudaErrors(err, __FILE__, __func__, __LINE__)) { return ret; }
#define cudaVideoCodec_NONE ((cudaVideoCodec) -1)
#define LOG(...) logger(__FILE__, __func__, __LINE__, __VA_ARGS__);
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#define PTROFF(base, bytes) ((void *)((unsigned char *)(base) + (bytes)))
#define DECLARE_CODEC(name) \
__attribute__((used)) \
__attribute__((retain)) \
__attribute__((section("nvd_codecs"))) \
__attribute__((aligned(__alignof__(NVCodec)))) \
NVCodec name
#define DECLARE_DISABLED_CODEC(name) \
__attribute__((section("nvd_disabled_codecs"))) \
__attribute__((aligned(__alignof__(NVCodec)))) \
NVCodec name
#endif // VABACKEND_H
07070100000040000081A4000000000000000000000001663926A700001535000000000000000000000000000000000000002500000000nvidia-vaapi-driver-0.0.12/src/vc1.c#include "vabackend.h"
static void copyVC1PicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VAPictureParameterBufferVC1* buf = (VAPictureParameterBufferVC1*) buffer->ptr;
picParams->PicWidthInMbs = (ctx->width + 15)/16;
picParams->FrameHeightInMbs = (ctx->height + 15)/16;
int interlaced = buf->picture_fields.bits.frame_coding_mode == 2;
int field_mode = buf->sequence_fields.bits.interlace && interlaced;
ctx->renderTarget->progressiveFrame = !interlaced;
picParams->field_pic_flag = buf->sequence_fields.bits.interlace && interlaced;
picParams->bottom_field_flag = field_mode && !(buf->picture_fields.bits.top_field_first ^ !buf->picture_fields.bits.is_first_field);
picParams->second_field = !buf->picture_fields.bits.is_first_field;
if (interlaced) {
picParams->intra_pic_flag = buf->picture_fields.bits.picture_type == 0 || //Intra
buf->picture_fields.bits.picture_type == 7; //Bi-Intra
picParams->ref_pic_flag = buf->picture_fields.bits.picture_type == 0 || //Intra
buf->picture_fields.bits.picture_type == 3; //Predicted
} else {
picParams->intra_pic_flag = buf->picture_fields.bits.picture_type == 0 || //Intra
buf->picture_fields.bits.picture_type == 3; //Bi-Intra
picParams->ref_pic_flag = buf->picture_fields.bits.picture_type == 0 || //Intra
buf->picture_fields.bits.picture_type == 1 || //Predicted
buf->picture_fields.bits.picture_type == 4; //Predicted - skipped?
}
CUVIDVC1PICPARAMS *pps = &picParams->CodecSpecific.vc1;
pps->ForwardRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->forward_reference_picture);
pps->BackwardRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->backward_reference_picture);
pps->FrameWidth = ctx->width;
pps->FrameHeight = ctx->height;
pps->progressive_fcm = buf->picture_fields.bits.frame_coding_mode == 0;
pps->profile = buf->sequence_fields.bits.profile;
pps->postprocflag = buf->post_processing != 0;
pps->pulldown = buf->sequence_fields.bits.pulldown;
pps->interlace = buf->sequence_fields.bits.interlace;
pps->tfcntrflag = buf->sequence_fields.bits.tfcntrflag;
pps->finterpflag = buf->sequence_fields.bits.finterpflag;
pps->psf = buf->sequence_fields.bits.psf;
pps->multires = buf->sequence_fields.bits.multires;
pps->syncmarker = buf->sequence_fields.bits.syncmarker;
pps->rangered = buf->sequence_fields.bits.rangered;
pps->maxbframes = buf->sequence_fields.bits.max_b_frames;
pps->refdist_flag = buf->reference_fields.bits.reference_distance_flag;
pps->extended_mv = buf->mv_fields.bits.extended_mv_flag;
pps->dquant = buf->pic_quantizer_fields.bits.dquant;
pps->vstransform = buf->transform_fields.bits.variable_sized_transform_flag;
pps->loopfilter = buf->entrypoint_fields.bits.loopfilter;
pps->fastuvmc = buf->fast_uvmc_flag;
pps->overlap = buf->sequence_fields.bits.overlap;
pps->quantizer = buf->pic_quantizer_fields.bits.quantizer;
pps->extended_dmv = buf->mv_fields.bits.extended_dmv_flag;
pps->range_mapy_flag = buf->range_mapping_fields.bits.luma_flag;
pps->range_mapy = buf->range_mapping_fields.bits.luma;
pps->range_mapuv_flag = buf->range_mapping_fields.bits.chroma_flag;
pps->range_mapuv = buf->range_mapping_fields.bits.chroma;
pps->rangeredfrm = buf->range_reduction_frame;
}
static void copyVC1SliceParam(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
ctx->lastSliceParams = buf->ptr;
ctx->lastSliceParamsCount = buf->elements;
picParams->nNumSlices += buf->elements;
}
static void copyVC1SliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
VASliceParameterBufferVC1 *sliceParams = &((VASliceParameterBufferVC1*) ctx->lastSliceParams)[i];
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
picParams->nBitstreamDataLen += sliceParams->slice_data_size;
}
}
static void copyVC1BitPlane(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
//not sure anything needs to be done here, but this method is here to suppress the unhandled type error
}
static cudaVideoCodec computeVC1CudaCodec(VAProfile profile) {
if (profile == VAProfileVC1Advanced || profile == VAProfileVC1Main || profile == VAProfileVC1Simple) {
return cudaVideoCodec_VC1;
}
return cudaVideoCodec_NONE;
}
static const VAProfile vc1SupportedProfiles[] = {
VAProfileVC1Simple,
VAProfileVC1Main,
VAProfileVC1Advanced,
};
const DECLARE_CODEC(vc1Codec) = {
.computeCudaCodec = computeVC1CudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyVC1PicParam,
[VASliceParameterBufferType] = copyVC1SliceParam,
[VASliceDataBufferType] = copyVC1SliceData,
[VABitPlaneBufferType] = copyVC1BitPlane,
},
.supportedProfileCount = ARRAY_SIZE(vc1SupportedProfiles),
.supportedProfiles = vc1SupportedProfiles,
};
07070100000041000081A4000000000000000000000001663926A700000C79000000000000000000000000000000000000002500000000nvidia-vaapi-driver-0.0.12/src/vp8.c#include "vabackend.h"
static void copyVP8PicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
//Untested, my 1060 (GP106) doesn't support this, however it's simple enough that it should work
VAPictureParameterBufferVP8* buf = (VAPictureParameterBufferVP8*) buffer->ptr;
picParams->PicWidthInMbs = (buf->frame_width + 15) / 16;
picParams->FrameHeightInMbs = (buf->frame_height + 15) / 16;
picParams->CodecSpecific.vp8.width = buf->frame_width;
picParams->CodecSpecific.vp8.height = buf->frame_height;
picParams->CodecSpecific.vp8.LastRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->last_ref_frame);
picParams->CodecSpecific.vp8.GoldenRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->golden_ref_frame);
picParams->CodecSpecific.vp8.AltRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->alt_ref_frame);
picParams->CodecSpecific.vp8.vp8_frame_tag.frame_type = buf->pic_fields.bits.key_frame;
picParams->CodecSpecific.vp8.vp8_frame_tag.version = buf->pic_fields.bits.version;
picParams->CodecSpecific.vp8.vp8_frame_tag.show_frame = 1;//?
picParams->CodecSpecific.vp8.vp8_frame_tag.update_mb_segmentation_data = buf->pic_fields.bits.segmentation_enabled ? buf->pic_fields.bits.update_segment_feature_data : 0;
}
static void copyVP8SliceParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VASliceParameterBufferVP8* buf = (VASliceParameterBufferVP8*) buffer->ptr;
picParams->CodecSpecific.vp8.first_partition_size = buf->partition_size[0] + ((buf->macroblock_offset + 7) / 8);
ctx->lastSliceParams = buffer->ptr;
ctx->lastSliceParamsCount = buffer->elements;
picParams->nNumSlices += buffer->elements;
}
static void copyVP8SliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
//manually pull out the show_frame field, no need to get the full bitstream parser involved
picParams->CodecSpecific.vp8.vp8_frame_tag.show_frame = (((uint8_t*) buf->ptr)[0] & 0x10) != 0;
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
VASliceParameterBufferVP8 *sliceParams = &((VASliceParameterBufferVP8*) ctx->lastSliceParams)[i];
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size + buf->offset);
picParams->nBitstreamDataLen += sliceParams->slice_data_size + buf->offset;
}
}
static cudaVideoCodec computeVP8CudaCodec(VAProfile profile) {
if (profile == VAProfileVP8Version0_3) {
return cudaVideoCodec_VP8;
}
return cudaVideoCodec_NONE;
}
static const VAProfile vp8SupportedProfiles[] = {
VAProfileVP8Version0_3,
};
const DECLARE_CODEC(vp8Codec) = {
.computeCudaCodec = computeVP8CudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyVP8PicParam,
[VASliceParameterBufferType] = copyVP8SliceParam,
[VASliceDataBufferType] = copyVP8SliceData,
},
.supportedProfileCount = ARRAY_SIZE(vp8SupportedProfiles),
.supportedProfiles = vp8SupportedProfiles,
};
07070100000042000081A4000000000000000000000001663926A7000020BF000000000000000000000000000000000000002500000000nvidia-vaapi-driver-0.0.12/src/vp9.c#include "vabackend.h"
//squash a compile warning, we know this is an unstable API
#define GST_USE_UNSTABLE_API
#include <gst/codecparsers/gstvp9parser.h>
static void copyVP9PicParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
VADecPictureParameterBufferVP9* buf = (VADecPictureParameterBufferVP9*) buffer->ptr;
picParams->PicWidthInMbs = (buf->frame_width + 15) / 16;
picParams->FrameHeightInMbs = (buf->frame_height + 15) / 16;
picParams->CodecSpecific.vp9.width = buf->frame_width;
picParams->CodecSpecific.vp9.height = buf->frame_height;
picParams->CodecSpecific.vp9.LastRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->reference_frames[buf->pic_fields.bits.last_ref_frame]);
picParams->CodecSpecific.vp9.GoldenRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->reference_frames[buf->pic_fields.bits.golden_ref_frame]);
picParams->CodecSpecific.vp9.AltRefIdx = pictureIdxFromSurfaceId(ctx->drv, buf->reference_frames[buf->pic_fields.bits.alt_ref_frame]);
picParams->CodecSpecific.vp9.profile = buf->profile;
picParams->CodecSpecific.vp9.frameContextIdx = buf->pic_fields.bits.frame_context_idx;
picParams->CodecSpecific.vp9.frameContextIdx = buf->pic_fields.bits.frame_context_idx;
picParams->CodecSpecific.vp9.frameType = buf->pic_fields.bits.frame_type;
picParams->CodecSpecific.vp9.showFrame = buf->pic_fields.bits.show_frame;
picParams->CodecSpecific.vp9.errorResilient = buf->pic_fields.bits.error_resilient_mode;
picParams->CodecSpecific.vp9.frameParallelDecoding = buf->pic_fields.bits.frame_parallel_decoding_mode;
picParams->CodecSpecific.vp9.subSamplingX = buf->pic_fields.bits.subsampling_x;
picParams->CodecSpecific.vp9.subSamplingY = buf->pic_fields.bits.subsampling_y;
picParams->CodecSpecific.vp9.intraOnly = buf->pic_fields.bits.intra_only;
picParams->CodecSpecific.vp9.allow_high_precision_mv = buf->pic_fields.bits.allow_high_precision_mv;
picParams->CodecSpecific.vp9.refreshEntropyProbs = buf->pic_fields.bits.refresh_frame_context;
picParams->CodecSpecific.vp9.bitDepthMinus8Luma = buf->bit_depth - 8;
picParams->CodecSpecific.vp9.bitDepthMinus8Chroma = buf->bit_depth - 8;
picParams->CodecSpecific.vp9.loopFilterLevel = buf->filter_level;
picParams->CodecSpecific.vp9.loopFilterSharpness = buf->sharpness_level;
picParams->CodecSpecific.vp9.log2_tile_columns = buf->log2_tile_columns;
picParams->CodecSpecific.vp9.log2_tile_rows = buf->log2_tile_rows;
picParams->CodecSpecific.vp9.segmentEnabled = buf->pic_fields.bits.segmentation_enabled;
picParams->CodecSpecific.vp9.segmentMapUpdate = buf->pic_fields.bits.segmentation_update_map;
picParams->CodecSpecific.vp9.segmentMapTemporalUpdate = buf->pic_fields.bits.segmentation_temporal_update;
picParams->CodecSpecific.vp9.resetFrameContext = buf->pic_fields.bits.reset_frame_context;
picParams->CodecSpecific.vp9.mcomp_filter_type = buf->pic_fields.bits.mcomp_filter_type;
picParams->CodecSpecific.vp9.frameTagSize = buf->frame_header_length_in_bytes;
picParams->CodecSpecific.vp9.offsetToDctParts = buf->first_partition_size;
for (int i = 0; i < 7; i++) {
picParams->CodecSpecific.vp9.mb_segment_tree_probs[i] = buf->mb_segment_tree_probs[i];
}
//yes, refFrameSignBias is meant to be offset by 1
picParams->CodecSpecific.vp9.activeRefIdx[0] = buf->pic_fields.bits.last_ref_frame;
picParams->CodecSpecific.vp9.refFrameSignBias[1] = buf->pic_fields.bits.last_ref_frame_sign_bias;
picParams->CodecSpecific.vp9.activeRefIdx[1] = buf->pic_fields.bits.golden_ref_frame;
picParams->CodecSpecific.vp9.refFrameSignBias[2] = buf->pic_fields.bits.golden_ref_frame_sign_bias;
picParams->CodecSpecific.vp9.activeRefIdx[2] = buf->pic_fields.bits.alt_ref_frame;
picParams->CodecSpecific.vp9.refFrameSignBias[3] = buf->pic_fields.bits.alt_ref_frame_sign_bias;
for (int i = 0; i < 3; i++) {
picParams->CodecSpecific.vp9.segment_pred_probs[i] = buf->segment_pred_probs[i];
}
}
static GstVp9Parser *parser;
static void parseExtraInfo(void *buf, uint32_t size, CUVIDPICPARAMS *picParams) {
//TODO a bit of a hack as we don't have per decoder init/deinit functions atm
if (parser == NULL) {
parser = gst_vp9_parser_new ();
}
//parse all the extra information that VA-API doesn't support, but NVDEC requires
GstVp9FrameHdr hdr;
GstVp9ParserResult res = gst_vp9_parser_parse_frame_header(parser, &hdr, buf, size);
if (res == GST_VP9_PARSER_OK) {
for (int i = 0; i < 8; i++) {
picParams->CodecSpecific.vp9.segmentFeatureEnable[i][0] = hdr.segmentation.data[i].alternate_quantizer_enabled;
picParams->CodecSpecific.vp9.segmentFeatureEnable[i][1] = hdr.segmentation.data[i].alternate_loop_filter_enabled;
picParams->CodecSpecific.vp9.segmentFeatureEnable[i][2] = hdr.segmentation.data[i].reference_frame_enabled;
picParams->CodecSpecific.vp9.segmentFeatureEnable[i][3] = hdr.segmentation.data[i].reference_skip;
picParams->CodecSpecific.vp9.segmentFeatureData[i][0] = hdr.segmentation.data[i].alternate_quantizer;
picParams->CodecSpecific.vp9.segmentFeatureData[i][1] = hdr.segmentation.data[i].alternate_loop_filter;
picParams->CodecSpecific.vp9.segmentFeatureData[i][2] = hdr.segmentation.data[i].reference_frame;
picParams->CodecSpecific.vp9.segmentFeatureData[i][3] = 0;
}
picParams->CodecSpecific.vp9.segmentFeatureMode = hdr.segmentation.abs_delta;
picParams->CodecSpecific.vp9.modeRefLfEnabled = hdr.loopfilter.mode_ref_delta_enabled;
for (int i = 0; i < 2; i++)
picParams->CodecSpecific.vp9.mbModeLfDelta[i] = hdr.loopfilter.mode_deltas[i];
for (int i = 0; i < 4; i++)
picParams->CodecSpecific.vp9.mbRefLfDelta[i] = hdr.loopfilter.ref_deltas[i];
picParams->CodecSpecific.vp9.qpYAc = hdr.quant_indices.y_ac_qi;
picParams->CodecSpecific.vp9.qpYDc = hdr.quant_indices.y_dc_delta;
picParams->CodecSpecific.vp9.qpChDc = hdr.quant_indices.uv_dc_delta;
picParams->CodecSpecific.vp9.qpChAc = hdr.quant_indices.uv_ac_delta;
picParams->CodecSpecific.vp9.colorSpace = parser->color_space;
}
//gst_vp9_parser_free(parser);
}
static void copyVP9SliceParam(NVContext *ctx, NVBuffer* buffer, CUVIDPICPARAMS *picParams)
{
//don't bother doing anything here, we can just read it from the reparsed header
ctx->lastSliceParams = buffer->ptr;
ctx->lastSliceParamsCount = buffer->elements;
picParams->nNumSlices += buffer->elements;
}
static void copyVP9SliceData(NVContext *ctx, NVBuffer* buf, CUVIDPICPARAMS *picParams)
{
for (unsigned int i = 0; i < ctx->lastSliceParamsCount; i++)
{
VASliceParameterBufferVP9 *sliceParams = &((VASliceParameterBufferVP9*) ctx->lastSliceParams)[i];
uint32_t offset = (uint32_t) ctx->bitstreamBuffer.size;
appendBuffer(&ctx->sliceOffsets, &offset, sizeof(offset));
appendBuffer(&ctx->bitstreamBuffer, PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size);
//TODO this might not be the best place to call as we may not have a complete packet yet...
parseExtraInfo(PTROFF(buf->ptr, sliceParams->slice_data_offset), sliceParams->slice_data_size, picParams);
picParams->nBitstreamDataLen += sliceParams->slice_data_size;
}
}
static cudaVideoCodec computeVP9CudaCodec(VAProfile profile) {
switch (profile) {
case VAProfileVP9Profile0:
case VAProfileVP9Profile1:
case VAProfileVP9Profile2:
case VAProfileVP9Profile3:
return cudaVideoCodec_VP9;
default:
return cudaVideoCodec_NONE;
}
}
static const VAProfile vp9SupportedProfiles[] = {
VAProfileVP9Profile0,
VAProfileVP9Profile1,
VAProfileVP9Profile2,
VAProfileVP9Profile3,
};
const DECLARE_CODEC(vp9Codec) = {
.computeCudaCodec = computeVP9CudaCodec,
.handlers = {
[VAPictureParameterBufferType] = copyVP9PicParam,
[VASliceParameterBufferType] = copyVP9SliceParam,
[VASliceDataBufferType] = copyVP9SliceData,
},
.supportedProfileCount = ARRAY_SIZE(vp9SupportedProfiles),
.supportedProfiles = vp9SupportedProfiles,
};
07070100000043000041ED000000000000000000000002663926A700000000000000000000000000000000000000000000002700000000nvidia-vaapi-driver-0.0.12/subprojects07070100000044000081A4000000000000000000000001663926A70000022B000000000000000000000000000000000000003F00000000nvidia-vaapi-driver-0.0.12/subprojects/ff-nvcodec-headers.wrap[wrap-file]
directory = nv-codec-headers-11.1.5.1
source_url = https://github.com/FFmpeg/nv-codec-headers/releases/download/n11.1.5.1/nv-codec-headers-11.1.5.1.tar.gz
source_filename = nv-codec-headers-11.1.5.1.tar.gz
source_hash = a28cdde3ac0e9e02c2dde7a1b4de5333b4ac6148a8332ca712da243a3361a0d9
patch_filename = ff-nvcodec-headers_11.1.5.1-0_patch.zip
patch_url = https://wrapdb.mesonbuild.com/v2/ff-nvcodec-headers_11.1.5.1-0/get_patch
patch_hash = 5ecf67ad26f1e4a3f2a8e10b22b37130dea8c867058ba79271441fdfd4f524a6
[provide]
ffnvcodec = ffnvcodec_dep
07070100000045000081ED000000000000000000000001663926A70000033B000000000000000000000000000000000000002300000000nvidia-vaapi-driver-0.0.12/test.sh#!/bin/sh
#make sure we use our driver
export LIBVA_DRIVER_NAME=nvidia
#export LIBVA_DRIVERS_PATH=$(dirname $(realpath $0))/build
#enable our logging
export NVD_LOG=1
#--hwdec=vaapi-copy is needed as NVDEC/Cuda has no support for DMA-BUF currently, so buffers need to be copied back to the CPU
#--hwdec-codecs=all FFMpeg will only use hardware decoding for specific codecs, this overrides that
#--vd-lavc-check-hw-profile=no FFMpeg will only use hardware decoding for specific profiles of some codec, this overrides that
#mpv -v --hwdec=vaapi-copy --hwdec-codecs=all --vd-lavc-check-hw-profile=no $@
#mpv -v -v --msg-level=all=debug --hwdec=vaapi --hwdec-codecs=all --vd-lavc-check-hw-profile=no $@
mpv -v --msg-color=no --msg-level=all=debug --hwdec=vaapi --gpu-debug --hwdec-codecs=all --vd-lavc-check-hw-profile=no "$@"
07070100000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000B00000000TRAILER!!!1646 blocks
