File qucs-digisim-verilog.patch of Package qucs

diff --git a/qucs/components/digi_sim.cpp b/qucs/components/digi_sim.cpp
index bf5067289..b7bc36273 100644
--- a/qucs/components/digi_sim.cpp
+++ b/qucs/components/digi_sim.cpp
@@ -45,7 +45,7 @@ Digi_Sim::Digi_Sim()
 	QObject::tr("type of simulation")+" [TruthTable, TimeList]"));
   Props.push_back(qucs::Property("time", "10 ns", false,
 	QObject::tr("duration of TimeList simulation")));
-  Props.push_back(qucs::Property("Model", "VHDL", false,
+  Props.push_back(qucs::Property("Model", "Verilog", false,
 	QObject::tr("netlist format")+" [VHDL, Verilog]"));
 }