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crystalhd
unused-variable.patch
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File unused-variable.patch of Package crystalhd
--- crystalhd_hw.c 2010-12-07 18:18:41.000000000 +0100 +++ crystalhd_hw.c 2011-03-16 10:45:04.498009062 +0100 @@ -716,7 +716,7 @@ { struct device *dev; struct tx_dma_pkt *tx_dma_packet = NULL; - uint32_t low_addr, high_addr; + //uint32_t low_addr, high_addr; addr_64 desc_addr; BC_STATUS sts, add_sts; uint32_t dummy_index = 0; @@ -772,8 +772,8 @@ } desc_addr.full_addr = tx_dma_packet->desc_mem.phy_addr; - low_addr = desc_addr.low_part; - high_addr = desc_addr.high_part; + //low_addr = desc_addr.low_part; + //high_addr = desc_addr.high_part; tx_dma_packet->call_back = call_back; tx_dma_packet->cb_event = cb_event; --- crystalhd_fleafuncs.c 2010-12-07 18:18:41.000000000 +0100 +++ crystalhd_fleafuncs.c 2011-03-16 10:51:22.826009081 +0100 @@ -168,7 +168,7 @@ { int32_t ddr2_speed_grade[2]; uint32_t sd_0_col_size, sd_0_bank_size, sd_0_row_size; - uint32_t sd_1_col_size, sd_1_bank_size, sd_1_row_size; + //uint32_t sd_1_col_size, sd_1_bank_size, sd_1_row_size; uint32_t ddr3_mode[2]; uint32_t regVal; bool bDDR3Detected=false; /*Should be filled in using the detection logic. Default to DDR2 */ @@ -182,9 +182,9 @@ sd_0_bank_size = BANK_SIZE_8; sd_0_row_size = ROW_SIZE_8K; /* DDR2 */ /* sd_0_row_size = ROW_SIZE_16K; // DDR3 */ - sd_1_col_size = COL_BITS_10; - sd_1_bank_size = BANK_SIZE_8; - sd_1_row_size = ROW_SIZE_8K; + //sd_1_col_size = COL_BITS_10; + //sd_1_bank_size = BANK_SIZE_8; + //sd_1_row_size = ROW_SIZE_8K; ddr3_mode[0] = 0; ddr3_mode[1] = 0; @@ -193,7 +193,7 @@ { ddr3_mode[0] = 1; sd_0_row_size = ROW_SIZE_16K; /* DDR3 */ - sd_1_row_size = ROW_SIZE_16K; /* DDR3 */ + //sd_1_row_size = ROW_SIZE_16K; /* DDR3 */ } @@ -844,7 +844,7 @@ bool StChangeSuccess=false; uint32_t tempFLL = 0; uint32_t freeListLen = 0; - BC_STATUS sts; + //BC_STATUS sts; struct crystalhd_rx_dma_pkt *rx_pkt = NULL; freeListLen = crystalhd_dioq_count(hw->rx_freeq); @@ -868,7 +868,7 @@ { rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); if (rx_pkt) - sts = hw->pfnPostRxSideBuff(hw, rx_pkt); + hw->pfnPostRxSideBuff(hw, rx_pkt); } /*printk(" Success\n"); */ @@ -892,7 +892,7 @@ { rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); if (rx_pkt) - sts = hw->pfnPostRxSideBuff(hw, rx_pkt); + hw->pfnPostRxSideBuff(hw, rx_pkt); } if (hw->PwrDwnTxIntr) { --- crystalhd_flea_ddr.c 2010-12-07 18:18:41.000000000 +0100 +++ crystalhd_flea_ddr.c 2011-03-16 10:56:14.138009092 +0100 @@ -317,11 +317,11 @@ uint8_t DIS_ODT = 0; uint8_t EN_2T_TIMING = 0; uint8_t CWL = 0; - uint8_t DQ_WIDTH = 0; + //uint8_t DQ_WIDTH = 0; - uint8_t DM_IDLE_MODE = 0; - uint8_t CTL_IDLE_MODE = 0; - uint8_t DQ_IDLE_MODE = 0; + //uint8_t DM_IDLE_MODE = 0; + //uint8_t CTL_IDLE_MODE = 0; + //uint8_t DQ_IDLE_MODE = 0; uint8_t DIS_LATENCY_CTRL = 0; @@ -452,9 +452,9 @@ DIS_ODT = 0; /*Power Saving Controls */ - DM_IDLE_MODE = 0; - CTL_IDLE_MODE = 0; - DQ_IDLE_MODE = 0; + //DM_IDLE_MODE = 0; + //CTL_IDLE_MODE = 0; + //DQ_IDLE_MODE = 0; /*Latency Control Setting */ DIS_LATENCY_CTRL = 0; @@ -462,7 +462,7 @@ /* ****** Start of Grain/Flea specific fixed settings ***** */ CS0_ONLY = 1 ; /* 16-bit mode only */ INTLV_DISABLE = 1 ; /* Interleave is always disabled */ - DQ_WIDTH = 16 ; + //DQ_WIDTH = 16 ; /* ****** End of Grain specific fixed settings ***** */ #if 0
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