File 0001-net-phy-motorcomm-Add-support-for-YT8521-PHY.patch of Package uboot-imx
From 4cc994159a90c98b3cf13746ac039fe433dc1983 Mon Sep 17 00:00:00 2001
From: "haidong.zheng" <haidong.zheng@nxp.com>
Date: Fri, 31 May 2024 17:02:11 +0800
Subject: [PATCH 1/4] net: phy: motorcomm: Add support for YT8521 PHY
Signed-off-by: haidong.zheng <haidong.zheng@nxp.com>
---
drivers/net/phy/Kconfig | 2 +-
drivers/net/phy/motorcomm.c | 126 ++++++++++++++++++++++++++++++------
2 files changed, 109 insertions(+), 19 deletions(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index faffb28ac48..844c48c5ac6 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -287,7 +287,7 @@ config PHY_MOTORCOMM
tristate "Motorcomm PHYs"
help
Enables support for Motorcomm network PHYs.
- Currently supports the YT8511 and YT8531 Gigabit Ethernet PHYs.
+ Currently supports the YT8511/YT8521/YT8531 Gigabit Ethernet PHYs.
config PHY_MSCC
bool "Microsemi Corp Ethernet PHYs support"
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index a2c763c8791..ffcbda8053c 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -12,6 +12,7 @@
#include <linux/bitfield.h>
#define PHY_ID_YT8511 0x0000010a
+#define PHY_ID_YT8521 0x0000011a
#define PHY_ID_YT8531 0x4f51e91b
#define PHY_ID_MASK GENMASK(31, 0)
@@ -58,10 +59,22 @@
#define YT8511_DELAY_FE_TX_EN (0xf << 12)
#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
+#define YT8521_SCR_SYNCE_ENABLE BIT(5)
+/* 1b0 output 25m clock
+ * 1b1 output 125m clock *default*
+ */
+#define YT8521_SCR_CLK_FRE_SEL_125M BIT(3)
+#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1)
+#define YT8521_SCR_CLK_SRC_PLL_125M 0
+#define YT8521_SCR_CLK_SRC_UTP_RX 1
+#define YT8521_SCR_CLK_SRC_SDS_RX 2
+#define YT8521_SCR_CLK_SRC_REF_25M 3
+
#define YT8531_SCR_SYNCE_ENABLE BIT(6)
/* 1b0 output 25m clock *default*
* 1b1 output 125m clock
*/
+
#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4)
#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1)
#define YT8531_SCR_CLK_SRC_PLL_125M 0
@@ -271,7 +284,7 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
break;
case PHY_INTERFACE_MODE_RGMII_ID:
val |= FIELD_PREP(YT8531_RC1R_RX_DELAY_MASK, rx_reg) |
- FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
+ FIELD_PREP(YT8531_RC1R_GE_TX_DELAY_MASK, tx_reg);
break;
default: /* do not support other modes */
return -EOPNOTSUPP;
@@ -438,8 +451,7 @@ static int yt8511_config(struct phy_device *phydev)
if (ret < 0)
return ret;
/* sleep control, disable PLL in sleep for now */
- ret = ytphy_modify_ext(phydev, YT8511_EXT_SLEEP_CTRL, YT8511_PLLON_SLP,
- 0);
+ ret = ytphy_modify_ext(phydev, YT8511_EXT_SLEEP_CTRL, YT8511_PLLON_SLP, 0);
if (ret < 0)
return ret;
@@ -551,6 +563,73 @@ static int yt8531_set_ds(struct phy_device *phydev)
return 0;
}
+static int yt8521_config(struct phy_device *phydev)
+{
+ struct ytphy_plat_priv *priv = phydev->priv;
+ u16 mask, val;
+ int ret;
+
+ ret = genphy_config_aneg(phydev);
+ if (ret < 0)
+ return ret;
+
+ ytphy_dt_parse(phydev);
+ switch (priv->clk_out_frequency) {
+ case YTPHY_DTS_OUTPUT_CLK_DIS:
+ mask = YT8521_SCR_SYNCE_ENABLE;
+ val = 0;
+ break;
+ case YTPHY_DTS_OUTPUT_CLK_25M:
+ mask = YT8521_SCR_SYNCE_ENABLE |
+ YT8521_SCR_CLK_SRC_MASK |
+ YT8521_SCR_CLK_FRE_SEL_125M;
+ val = YT8521_SCR_SYNCE_ENABLE |
+ FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
+ YT8521_SCR_CLK_SRC_REF_25M);
+ break;
+ case YTPHY_DTS_OUTPUT_CLK_125M:
+ mask = YT8521_SCR_SYNCE_ENABLE |
+ YT8521_SCR_CLK_SRC_MASK |
+ YT8521_SCR_CLK_FRE_SEL_125M;
+ val = YT8521_SCR_SYNCE_ENABLE |
+ YT8521_SCR_CLK_FRE_SEL_125M |
+ FIELD_PREP(YT8521_SCR_CLK_SRC_MASK,
+ YT8521_SCR_CLK_SRC_PLL_125M);
+ break;
+ default:
+ pr_warn("Freq err:%u\n", priv->clk_out_frequency);
+ return -EINVAL;
+ }
+
+ ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask, val);
+ if (ret < 0)
+ return ret;
+
+ ret = ytphy_rgmii_clk_delay_config(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (priv->flag & AUTO_SLEEP_DISABLED) {
+ /* disable auto sleep */
+ ret = ytphy_modify_ext(phydev,
+ YT8531_EXTREG_SLEEP_CONTROL1_REG,
+ YT8531_ESC1R_SLEEP_SW, 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (priv->flag & KEEP_PLL_ENABLED) {
+ /* enable RXC clock when no wire plug */
+ ret = ytphy_modify_ext(phydev,
+ YT8531_CLOCK_GATING_REG,
+ YT8531_CGR_RX_CLK_EN, 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
static int yt8531_config(struct phy_device *phydev)
{
struct ytphy_plat_priv *priv = phydev->priv;
@@ -634,22 +713,33 @@ static int yt8531_probe(struct phy_device *phydev)
}
U_BOOT_PHY_DRIVER(motorcomm8511) = {
- .name = "YT8511 Gigabit Ethernet",
- .uid = PHY_ID_YT8511,
- .mask = PHY_ID_MASK,
- .features = PHY_GBIT_FEATURES,
- .config = &yt8511_config,
- .startup = &genphy_startup,
- .shutdown = &genphy_shutdown,
+ .name = "YT8511 Gigabit Ethernet",
+ .uid = PHY_ID_YT8511,
+ .mask = PHY_ID_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .config = &yt8511_config,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+U_BOOT_PHY_DRIVER(motorcomm8521) = {
+ .name = "YT8521 Gigabit Ethernet",
+ .uid = PHY_ID_YT8521,
+ .mask = PHY_ID_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .probe = &yt8531_probe,
+ .config = &yt8521_config,
+ .startup = &yt8531_startup,
+ .shutdown = &genphy_shutdown,
};
U_BOOT_PHY_DRIVER(motorcomm8531) = {
- .name = "YT8531 Gigabit Ethernet",
- .uid = PHY_ID_YT8531,
- .mask = PHY_ID_MASK,
- .features = PHY_GBIT_FEATURES,
- .probe = &yt8531_probe,
- .config = &yt8531_config,
- .startup = &yt8531_startup,
- .shutdown = &genphy_shutdown,
+ .name = "YT8531 Gigabit Ethernet",
+ .uid = PHY_ID_YT8531,
+ .mask = PHY_ID_MASK,
+ .features = PHY_GBIT_FEATURES,
+ .probe = &yt8531_probe,
+ .config = &yt8531_config,
+ .startup = &yt8531_startup,
+ .shutdown = &genphy_shutdown,
};
--
2.25.1
