File 0015-sipeed-slogic-analyzer-fix-initial-threshold-voltage.patch of Package libsigrok

From a8eaa209d51c74f0dac2d0cf1e195efef8116a75 Mon Sep 17 00:00:00 2001
From: Mikhail Paulyshka <me@mixaill.net>
Date: Sun, 14 Dec 2025 18:45:44 +0300
Subject: [PATCH 15/17] sipeed-slogic-analyzer: fix initial threshold voltage
 value

---
 src/hardware/sipeed-slogic-analyzer/api.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/hardware/sipeed-slogic-analyzer/api.c b/src/hardware/sipeed-slogic-analyzer/api.c
index 5b05c950a..737a53a17 100644
--- a/src/hardware/sipeed-slogic-analyzer/api.c
+++ b/src/hardware/sipeed-slogic-analyzer/api.c
@@ -255,7 +255,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 				devc->cur_samplerate = devc->limit_samplerate;
 				devc->cur_pattern_mode_idx = PATTERN_MODE_NORMAL;
 				devc->voltage_threshold[0] =
-					devc->voltage_threshold[1] = 1.7f;
+					devc->voltage_threshold[1] = 1.7000000000000004;
 
 				devc->digital_group =
 					sr_channel_group_new(sdi, "LA", NULL);
@@ -334,7 +334,8 @@ static int dev_open(struct sr_dev_inst *sdi)
 	if (devc->model->operation.remote_reset)
 		devc->model->operation.remote_reset(sdi);
 
-	devc->voltage_threshold[0] = devc->voltage_threshold[1] = 1.6f;
+	devc->voltage_threshold[0] = devc->voltage_threshold[1] = 1.7000000000000004;
+
 	sr_config_set(sdi, NULL, SR_CONF_VOLTAGE_THRESHOLD,
 				g_variant_new("(dd)", &devc->voltage_threshold[0],
 			      &devc->voltage_threshold[1]));
-- 
2.52.0