File ipxe.5f85cbb9ee1c00cec81a848a9e871ad5d1e7f53f.p... of Package xen

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File ipxe.5f85cbb9ee1c00cec81a848a9e871ad5d1e7f53f.patch of Package xen (Revision 1b049f727c9e7d4aec4eb434d870b455)

Currently displaying revision 1b049f727c9e7d4aec4eb434d870b455 , Show latest

From: Michael Brown <mcb30@ipxe.org>
Date: Wed, 29 Mar 2017 10:36:03 +0300
Subject: 5f85cbb9ee1c00cec81a848a9e871ad5d1e7f53f

[build] Avoid implicit-fallthrough warnings on GCC 7

Reported-by: Vinson Lee <vlee@freedesktop.org>
Reported-by: Liang Yan <lyan@suse.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
---
 src/arch/i386/image/bzimage.c                |  2 ++
 src/drivers/net/ath/ath9k/ath9k_ar5008_phy.c |  2 ++
 src/drivers/net/ath/ath9k/ath9k_ar9002_phy.c |  1 +
 src/drivers/net/ath/ath9k/ath9k_ar9003_phy.c |  1 +
 src/drivers/net/igbvf/igbvf_vf.c             |  1 +
 src/drivers/net/tg3.c                        | 16 ++++++++++++++++
 6 files changed, 23 insertions(+)

--- a/src/arch/i386/image/bzimage.c
+++ b/src/arch/i386/image/bzimage.c
@@ -266,27 +266,29 @@ static int bzimage_parse_cmdline ( struct image *image,
 			}
 		}
 	}
 
 	/* Look for "mem=" */
 	if ( ( mem = strstr ( cmdline, "mem=" ) ) ) {
 		mem += 4;
 		bzimg->mem_limit = strtoul ( mem, &mem, 0 );
 		switch ( *mem ) {
 		case 'G':
 		case 'g':
 			bzimg->mem_limit <<= 10;
+			/* Fall through */
 		case 'M':
 		case 'm':
 			bzimg->mem_limit <<= 10;
+			/* Fall through */
 		case 'K':
 		case 'k':
 			bzimg->mem_limit <<= 10;
 			break;
 		case '\0':
 		case ' ':
 			break;
 		default:
 			DBGC ( image, "bzImage %p strange \"mem=\" "
 			       "terminator '%c'\n", image, *mem );
 			break;
 		}
--- a/src/drivers/net/ath/ath9k/ath9k_ar5008_phy.c
+++ b/src/drivers/net/ath/ath9k/ath9k_ar5008_phy.c
@@ -631,30 +631,32 @@ static void ar5008_hw_init_bb(struct ath_hw *ah,
 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
 {
 	int rx_chainmask, tx_chainmask;
 
 	rx_chainmask = ah->rxchainmask;
 	tx_chainmask = ah->txchainmask;
 
 
 	switch (rx_chainmask) {
 	case 0x5:
 		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 			    AR_PHY_SWAP_ALT_CHAIN);
+		/* Fall through */
 	case 0x3:
 		if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
 			REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 			REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 			break;
 		}
+		/* Fall through */
 	case 0x1:
 	case 0x2:
 	case 0x7:
 		ENABLE_REGWRITE_BUFFER(ah);
 		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
 		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
 		break;
 	default:
 		ENABLE_REGWRITE_BUFFER(ah);
 		break;
 	}
 
--- a/src/drivers/net/ath/ath9k/ath9k_ar9002_phy.c
+++ b/src/drivers/net/ath/ath9k/ath9k_ar9002_phy.c
@@ -113,24 +113,25 @@ static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 	} else {
 		bMode = 0;
 		fracMode = 0;
 
 		switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
 		case 0:
 			if ((freq % 20) == 0)
 				aModeRefSel = 3;
 			else if ((freq % 10) == 0)
 				aModeRefSel = 2;
 			if (aModeRefSel)
 				break;
+			/* Fall through */
 		case 1:
 		default:
 			aModeRefSel = 0;
 			/*
 			 * Enable 2G (fractional) mode for channels
 			 * which are 5MHz spaced.
 			 */
 			fracMode = 1;
 			refDivA = 1;
 			channelSel = CHANSEL_5G(freq);
 
 			/* RefDivA setting */
--- a/src/drivers/net/ath/ath9k/ath9k_ar9003_phy.c
+++ b/src/drivers/net/ath/ath9k/ath9k_ar9003_phy.c
@@ -530,24 +530,25 @@ static void ar9003_hw_init_bb(struct ath_hw *ah,
 	 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
 	 * does not happen.
 	 */
 	udelay(synthDelay + BASE_ACTIVATE_DELAY);
 }
 
 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 {
 	switch (rx) {
 	case 0x5:
 		REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 			    AR_PHY_SWAP_ALT_CHAIN);
+		/* Fall through */
 	case 0x3:
 	case 0x1:
 	case 0x2:
 	case 0x7:
 		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 		break;
 	default:
 		break;
 	}
 
 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
--- a/src/drivers/net/igbvf/igbvf_vf.c
+++ b/src/drivers/net/igbvf/igbvf_vf.c
@@ -348,24 +348,25 @@ void igbvf_rlpml_set_vf(struct e1000_hw *hw, u16 max_size)
 s32 igbvf_promisc_set_vf(struct e1000_hw *hw, enum e1000_promisc_type type)
 {
 	struct e1000_mbx_info *mbx = &hw->mbx;
 	u32 msgbuf = E1000_VF_SET_PROMISC;
 	s32 ret_val;
 
 	switch (type) {
 	case e1000_promisc_multicast:
 		msgbuf |= E1000_VF_SET_PROMISC_MULTICAST;
 		break;
 	case e1000_promisc_enabled:
 		msgbuf |= E1000_VF_SET_PROMISC_MULTICAST;
+		/* Fall through */
 	case e1000_promisc_unicast:
 		msgbuf |= E1000_VF_SET_PROMISC_UNICAST;
 	case e1000_promisc_disabled:
 		break;
 	default:
 		return -E1000_ERR_MAC_INIT;
 	}
 
 	 ret_val = mbx->ops.write_posted(hw, &msgbuf, 1, 0);
 
 	if (!ret_val)
 		ret_val = mbx->ops.read_posted(hw, &msgbuf, 1, 0);
--- a/src/drivers/net/tg3.c
+++ b/src/drivers/net/tg3.c
@@ -2257,39 +2257,55 @@ static int tg3_setup_hw(struct tg3 *tp)
 	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
 	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
 
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
 	    || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
 		limit = 8;
 	else
 		limit = 16;
 	if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
 		limit -= 4;
 	switch (limit) {
 	case 16:	tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
+	/* Fall through */
 	case 15:	tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
+	/* Fall through */
 	case 14:	tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
+	/* Fall through */
 	case 13:	tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
+	/* Fall through */
 	case 12:	tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
+	/* Fall through */
 	case 11:	tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
+	/* Fall through */
 	case 10:	tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
+	/* Fall through */
 	case 9:		tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
+	/* Fall through */
 	case 8:		tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
+	/* Fall through */
 	case 7:		tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
+	/* Fall through */
 	case 6:		tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
+	/* Fall through */
 	case 5:		tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
+	/* Fall through */
 	case 4:		/* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
+	/* Fall through */
 	case 3:		/* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
+	/* Fall through */
 	case 2:
+	/* Fall through */
 	case 1:
+	/* Fall through */
 	default:
 		break;
 	};
 
 	return err;
 }
 
 
 
 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 static void tg3_nvram_init(struct tg3 *tp)
 {

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File ipxe.5f85cbb9ee1c00cec81a848a9e871ad5d1e7f53f.patch of Package xen (Revision 1b049f727c9e7d4aec4eb434d870b455)

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