File glibc-2.4-ppcsync.diff of Package glibc

Overview Repositories Revisions Requests Users Attributes Meta

File glibc-2.4-ppcsync.diff of Package glibc

2006-04-03  Steven Munroe  <sjmunroe@us.ibm.com>

[BZ #2505]
	* sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR4]:
	Define atomic_read_barrier and __ARCH_REL_INSTR using lwsync.

diff -urN libc24-cvstip-20060331/sysdeps/powerpc/powerpc32/bits/atomic.h libc24/sysdeps/powerpc/powerpc32/bits/atomic.h
--- sysdeps/powerpc/powerpc32/bits/atomic.h	2004-09-08 00:16:09.000000000 -0500
+++ sysdeps/powerpc/powerpc32/bits/atomic.h	2006-03-31 17:33:32.598312040 -0600
@@ -89,12 +89,27 @@
 # define __arch_atomic_decrement_if_positive_64(mem) \
     ({ abort (); (*mem)--; })
 
+#ifdef _ARCH_PWR4
+/*
+ * Newer powerpc64 processors support the new "light weight" sync (lwsync)
+ * So if the build is using -mcpu=[power4,power5,power5+,970] we can
+ * safely use lwsync.
+ */
+# define atomic_read_barrier()	__asm ("lwsync" ::: "memory")
+/*
+ * "light weight" sync can also be used for the release barrier.
+ */
+# ifndef UP
+#  define __ARCH_REL_INSTR	"lwsync"
+# endif
+#else
 /*
  * Older powerpc32 processors don't support the new "light weight"
  * sync (lwsync).  So the only safe option is to use normal sync
  * for all powerpc32 applications.
  */
 # define atomic_read_barrier()	__asm ("sync" ::: "memory")
+#endif
 
 /*
  * Include the rest of the atomic ops macros which are common to both

Places

File glibc-2.4-ppcsync.diff of Package glibc

Places