File ovmf-Revert-MdeModulePkg-Replace-Opcode-with-th... of Package ovmf

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File ovmf-Revert-MdeModulePkg-Replace-Opcode-with-the-correspo.patch of Package ovmf

From 8133c7453f729c7db7ee8850c491683f33e2c3d2 Mon Sep 17 00:00:00 2001
From: "Lee, Chun-Yi" <jlee@suse.com>
Date: Tue, 23 Aug 2022 16:57:41 +0800
Subject: [PATCH 5/5] Revert "MdeModulePkg: Replace Opcode with the
 corresponding instructions."

This reverts commit 84338c0d498555f860a480693ee8647a1795fba3.

Signed-off-by: Lee, Chun-Yi <jlee@suse.com>
---
 .../DebugSupportDxe/Ia32/AsmFuncs.nasm        | 20 +++++++++++++++---
 .../DebugSupportDxe/X64/AsmFuncs.nasm         | 21 ++++++++++++++++---
 2 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm
index 07fc912fe8..cfb418748f 100644
--- a/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm
+++ b/MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm
@@ -1,7 +1,7 @@
 ;/** @file
 ;  Low leve IA32 specific debug support functions.
 ;
-;  Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
+;  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
 ;  SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ;**/
@@ -26,6 +26,20 @@
 
 %define FXSTOR_FLAG 0x1000000         ; bit cpuid 24 of feature flags
 
+;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87,
+;; MMX, SSE, SSE2, etc registers.  The initialization of the debugsupport driver
+;; MUST check the CPUID feature flags to see that these instructions are available
+;; and fail to init if they are not.
+
+;; fxstor [edi]
+%macro FXSTOR_EDI 0
+                         db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [edi]
+%endmacro
+
+;; fxrstor [esi]
+%macro FXRSTOR_ESI 0
+                         db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [esi]
+%endmacro
 SECTION .data
 
 global ASM_PFX(OrigVector)
@@ -334,7 +348,7 @@ ExtraPushDone:
                 ; IMPORTANT!! The debug stack has been carefully constructed to
                 ; insure that esp and edi are 16 byte aligned when we get here.
                 ; They MUST be.  If they are not, a GP fault will occur.
-                fxsave  [edi]
+                FXSTOR_EDI
 
 ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
                 cld
@@ -358,7 +372,7 @@ ExtraPushDone:
 
 ;; FX_SAVE_STATE_IA32 FxSaveState;
                 mov     esi, esp
-                fxrstor [esi]
+                FXRSTOR_ESI
                 add     esp, 512
 
 ;; UINT32  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
index c6c5e49189..9cc38a3128 100644
--- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
+++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
@@ -1,7 +1,7 @@
 ;/** @file
 ;  Low level x64 routines used by the debug support driver.
 ;
-;  Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
+;  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
 ;  SPDX-License-Identifier: BSD-2-Clause-Patent
 ;
 ;**/
@@ -26,6 +26,21 @@
 
 %define FXSTOR_FLAG 0x1000000         ; bit cpuid 24 of feature flags
 
+;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87,
+;; MMX, SSE, SSE2, etc registers.  The initialization of the debugsupport driver
+;; MUST check the CPUID feature flags to see that these instructions are available
+;; and fail to init if they are not.
+
+;; fxstor [rdi]
+%macro FXSTOR_RDI 0
+                         db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [rdi]
+%endmacro
+
+;; fxrstor [rsi]
+%macro FXRSTOR_RSI 0
+                         db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [rsi]
+%endmacro
+
 SECTION .data
 
 global ASM_PFX(OrigVector)
@@ -366,7 +381,7 @@ ExtraPushDone:
                 ; IMPORTANT!! The debug stack has been carefully constructed to
                 ; insure that rsp and rdi are 16 byte aligned when we get here.
                 ; They MUST be.  If they are not, a GP fault will occur.
-                fxsave  [rdi]
+                FXSTOR_RDI
 
 ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
                 cld
@@ -389,7 +404,7 @@ ExtraPushDone:
 
 ;; FX_SAVE_STATE_X64 FxSaveState;
                 mov     rsi, rsp
-                fxrstor [rsi]
+                FXRSTOR_RSI
                 add     rsp, 512
 
 ;; UINT64  Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
-- 
2.26.2

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