File 5f6a05a0-pv-Handle-the-Intel-specific-MSR_MISC_... of Package xen

Overview Repositories Revisions Requests Users Attributes Meta

File 5f6a05a0-pv-Handle-the-Intel-specific-MSR_MISC_ENABLE-correctly.patch of Package xen (Revision d4df08e2f3fe7a86db20018815932372)

Currently displaying revision d4df08e2f3fe7a86db20018815932372 , Show latest

Subject: x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly
From: Andrew Cooper andrew.cooper3@citrix.com Tue Sep 22 16:09:36 2020 +0200
Date: Tue Sep 22 16:09:36 2020 +0200:
Git: b04d6731eedd639e078e0f0d8147c6b156875ac3

This MSR doesn't exist on AMD hardware, and switching away from the safe
functions in the common MSR path was an erroneous change.

Partially revert the change.

This is XSA-333.

Fixes: 4fdc932b3cc ("x86/Intel: drop another 32-bit leftover")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Wei Liu <wl@xen.org>

diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 7c21076dd0..85a9fd4767 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -913,7 +913,8 @@ static int read_msr(unsigned int reg, uint64_t *val,
         return X86EMUL_OKAY;
 
     case MSR_IA32_MISC_ENABLE:
-        rdmsrl(reg, *val);
+        if ( rdmsr_safe(reg, *val) )
+            break;
         *val = guest_misc_enable(*val);
         return X86EMUL_OKAY;
 
@@ -1053,7 +1054,8 @@ static int write_msr(unsigned int reg, uint64_t val,
         break;
 
     case MSR_IA32_MISC_ENABLE:
-        rdmsrl(reg, temp);
+        if ( rdmsr_safe(reg, temp) )
+            break;
         if ( val != guest_misc_enable(temp) )
             goto invalid;
         return X86EMUL_OKAY;

Places

File 5f6a05a0-pv-Handle-the-Intel-specific-MSR_MISC_ENABLE-correctly.patch of Package xen (Revision d4df08e2f3fe7a86db20018815932372)

Places