File 0001-tensile-ignore-cache-check.patch of Package python-tensile

From d6e13358f5960fd49e799b5250a329550545535a Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@amd.com>
Date: Sat, 20 Sep 2025 08:54:24 -0700
Subject: [PATCH] tensile ignore cache check

---
 Tensile/Common.py | 12 +-----------
 1 file changed, 1 insertion(+), 11 deletions(-)

diff --git a/Tensile/Common.py b/Tensile/Common.py
index 69f4e94039ec..a09e92c4f06d 100644
--- a/Tensile/Common.py
+++ b/Tensile/Common.py
@@ -2104,17 +2104,7 @@ def GetAsmCaps(isaVersion: IsaVersion, hipVersion: SemanticVersion, cachedAsmCap
 
     derivedAsmCaps["SupportedSource"] = True
 
-    ignoreCacheCheck = globalParameters["IgnoreAsmCapCache"]
-
-    # disable cache checking for < rocm 5.3
-    if len(hipVersion) >= 2:
-      ignoreCacheCheck = ignoreCacheCheck or \
-                         hipVersion.major < 5 or \
-                         (hipVersion.major == 5 and hipVersion.minor <= 2) 
-    
-    if not derivedAsmCaps["SupportedISA"] and cachedAsmCaps[isaVersion]["SupportedISA"]:
-      printWarning("Architecture {} not supported by ROCm {}".format(isaVersion, globalParameters['HipClangVersion']), DeveloperWarning)
-      ignoreCacheCheck = True
+    ignoreCacheCheck = True
 
     # check if derived caps matches asm cap cache
     if not ignoreCacheCheck:
-- 
2.51.0