File add-dsmr6-board.patch of Package imx93-devicetree
From 4c567a61f8dc536c79cd61a7a117d7da2229c01a Mon Sep 17 00:00:00 2001
From: Oetze van den Broek <vandenbroek@inventeers.nl>
Date: Tue, 12 Aug 2025 12:14:42 +0200
Subject: [PATCH] Add devicetree file.
---
.../boot/dts/freescale/imx93-11x11-dsmr6.dts | 945 ++++++++++++++++++
1 file changed, 945 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-dsmr6.dts
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-dsmr6.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-dsmr6.dts
new file mode 100644
index 000000000000..8dc1fe227ead
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-dsmr6.dts
@@ -0,0 +1,945 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx93.dtsi"
+
+/ {
+ model = "NXP i.MX93 11X11 DSMR6 board";
+ compatible = "fsl,imx93-11x11-dsmr6", "fsl,imx93";
+
+ aliases {
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ };
+
+ chosen {
+ stdout-path = &lpuart2;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0 0x80000000 0 0x30000000>;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4010000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@2021e000 {
+ reg = <0 0x2021e000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+
+ ele_reserved: ele-reserved@a4120000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4120000 0 0x100000>;
+ no-map;
+ };
+ };
+
+
+ // Regulator CAN2 not present on DSMR6 board.
+ // reg_can2_stby: regulator-can2-stby {
+ // compatible = "regulator-fixed";
+ // regulator-name = "can2-stby";
+ // regulator-min-microvolt = <3300000>;
+ // regulator-max-microvolt = <3300000>;
+ // gpio = <&pcal6524 23 GPIO_ACTIVE_LOW>;
+ // enable-active-low;
+ // };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ // usdhc2 is not used on DSMR6 board.
+ // reg_usdhc2_vmmc: regulator-usdhc2 {
+ // compatible = "regulator-fixed";
+ // pinctrl-names = "default";
+ // pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ // regulator-name = "VSD_3V3";
+ // regulator-min-microvolt = <3300000>;
+ // regulator-max-microvolt = <3300000>;
+ // gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ // off-on-delay-us = <12000>;
+ // enable-active-high;
+ // };
+
+ // Disabled because there is no 12 volt regulator on the FRDM board, so we disabled on the DSMR6 board to be sure.
+ // reg_vdd_12v: regulator-vdd-12v {
+ // compatible = "regulator-fixed";
+ // regulator-name = "reg_vdd_12v";
+ // regulator-min-microvolt = <12000000>;
+ // regulator-max-microvolt = <12000000>;
+ // gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
+ // enable-active-high;
+ // };
+
+
+ // reg_usdhc3_vmmc: regulator-usdhc3 {
+ // compatible = "regulator-fixed";
+ // regulator-name = "WLAN_EN";
+ // regulator-min-microvolt = <3300000>;
+ // regulator-max-microvolt = <3300000>;
+ // gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
+ // /*
+ // * IW612 wifi chip needs more delay than other wifi chips to complete
+ // * the host interface initialization after power up, otherwise the
+ // * internal state of IW612 may be unstable, resulting in the failure of
+ // * the SDIO3.0 switch voltage.
+ // */
+ // startup-delay-us = <20000>;
+ // enable-active-high;
+ // };
+
+ // usdhc3_pwrseq: usdhc3_pwrseq {
+ // compatible = "mmc-pwrseq-simple";
+ // reset = <&pcal6524 12 GPIO_ACTIVE_LOW>;
+ // };
+
+ // sound-mqs {
+ // compatible = "fsl,imx6sx-sdb-mqs",
+ // "fsl,imx-audio-mqs";
+ // model = "mqs-audio";
+ // audio-cpu = <&sai1>;
+ // audio-codec = <&mqs1>;
+ // };
+
+ // sw-keys {
+ // compatible = "gpio-keys";
+
+ // K2: user_btn1 {
+ // label = "User Button1";
+ // linux,code = <BTN_1>;
+ // gpios = <&pcal6524 5 GPIO_PULL_UP>;
+ // interrupt-parent = <&pcal6524>;
+ // interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ // };
+
+ // K3: user_btn2 {
+ // label = "User Button2";
+ // linux,code = <BTN_2>;
+ // gpios = <&pcal6524 6 GPIO_PULL_UP>;
+ // interrupt-parent = <&pcal6524>;
+ // interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ // };
+ // };
+};
+
+// Disabled, we don't have audio support on DSMR6
+// &sai1 {
+// #sound-dai-cells = <0>;
+// clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+// <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+// <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>;
+// clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k";
+// assigned-clocks = <&clk IMX93_CLK_SAI1>;
+// assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+// assigned-clock-rates = <24576000>;
+// fsl,sai-mclk-direction-output;
+// status = "okay";
+// };
+
+// Disabled, we don't have medium quality sound on DSMR6
+// &mqs1 {
+// pinctrl-names = "default";
+// pinctrl-0 = <&pinctrl_mqs1>;
+// clocks = <&clk IMX93_CLK_MQS1_GATE>;
+// clock-names = "mclk";
+// status = "okay";
+// };
+
+// Probably the temperature sensor, not sure, disabled for now.
+// &adc1 {
+// vref-supply = <®_vref_1v8>;
+// status = "okay";
+// };
+
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu1 0 1>,
+ <&mu1 1 1>,
+ <&mu1 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ fsl,startup-delay-ms = <500>;
+ status = "okay";
+};
+
+// Disabled, we don't have CANBUS on dsmr6
+// &flexcan2 {
+// pinctrl-names = "default", "sleep";
+// pinctrl-0 = <&pinctrl_flexcan2>;
+// pinctrl-1 = <&pinctrl_flexcan2_sleep>;
+// xceiver-supply = <®_can2_stby>;
+// status = "okay";
+// };
+
+// Keeping mailboxes.
+&mu1 {
+ status = "okay";
+};
+
+&mu2 {
+ status = "okay";
+};
+
+// Disabled for now
+// &eqos {
+// pinctrl-names = "default", "sleep";
+// pinctrl-0 = <&pinctrl_eqos>;
+// pinctrl-1 = <&pinctrl_eqos_sleep>;
+// phy-mode = "rgmii-id";
+// phy-handle = <ðphy1>;
+// status = "okay";
+
+// mdio {
+// compatible = "snps,dwmac-mdio";
+// #address-cells = <1>;
+// #size-cells = <0>;
+// clock-frequency = <5000000>;
+
+// ethphy1: ethernet-phy@1 {
+// reg = <1>;
+// reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+// reset-assert-us = <10000>;
+// reset-deassert-us = <80000>;
+// };
+// };
+// };
+
+// Disabled for now.
+// &fec {
+// pinctrl-names = "default", "sleep";
+// pinctrl-0 = <&pinctrl_fec>;
+// pinctrl-1 = <&pinctrl_fec_sleep>;
+// phy-mode = "rgmii-id";
+// phy-handle = <ðphy2>;
+// fsl,magic-packet;
+// status = "okay";
+
+// mdio {
+// #address-cells = <1>;
+// #size-cells = <0>;
+// clock-frequency = <5000000>;
+
+// ethphy2: ethernet-phy@2 {
+// reg = <2>;
+// eee-broken-1000t;
+// reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+// reset-assert-us = <10000>;
+// reset-deassert-us = <80000>;
+// };
+// };
+// };
+
+/*
+ * When add, delete or change any target device setting in &lpi2c1,
+ * please synchronize the changes to the &i3c1 bus in imx93-11x11-evk-i3c.dts.
+ */
+&lpi2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ // Disabled, we don't have this on the DSMR6 board
+ // pcal6408: gpio@20 {
+ // compatible = "nxp,pcal9554b";
+ // reg = <0x20>;
+ // gpio-controller;
+ // #gpio-cells = <2>;
+ // vcc-supply = <®_usdhc3_vmmc>;
+ // status = "okay";
+ // };
+
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2237500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ // Removed on the DSMR6 board
+ // pcal6524: gpio@22 {
+ // compatible = "nxp,pcal6524";
+ // pinctrl-names = "default";
+ // pinctrl-0 = <&pinctrl_pcal6524>;
+ // reg = <0x22>;
+ // gpio-controller;
+ // #gpio-cells = <2>;
+ // interrupt-controller;
+ // #interrupt-cells = <2>;
+ // interrupt-parent = <&gpio3>;
+ // interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ // };
+
+ // Still present in DSMR6 board, was on i2c3, now on i2c2.
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&gpio2>; // Updated the interrupt parent to gpio2 from pcal6524
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+ };
+};
+
+// Disabled i2c3, because the pins are used for a radio now.
+// &lpi2c3 {
+// #address-cells = <1>;
+// #size-cells = <0>;
+// clock-frequency = <400000>;
+// pinctrl-names = "default", "sleep";
+// pinctrl-0 = <&pinctrl_lpi2c3>;
+// pinctrl-1 = <&pinctrl_lpi2c3>;
+// status = "okay";
+
+// ptn5110: tcpc@50 {
+// compatible = "nxp,ptn5110", "tcpci";
+// reg = <0x50>;
+// interrupt-parent = <&gpio3>;
+// interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+// status = "okay";
+
+// port {
+// typec1_dr_sw: endpoint {
+// remote-endpoint = <&usb1_drd_sw>;
+// };
+// };
+
+// typec1_con: connector {
+// compatible = "usb-c-connector";
+// label = "USB-C";
+// power-role = "dual";
+// data-role = "dual";
+// try-power-role = "sink";
+// source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+// sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+// PDO_VAR(5000, 20000, 3000)>;
+// op-sink-microwatt = <15000000>;
+// self-powered;
+// };
+// };
+// };
+
+&lpuart2 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+// Disabled, we don't have a uart5 on the board.
+// &lpuart5 {
+// /* BT */
+// pinctrl-names = "default";
+// pinctrl-assert-gpios = <&pcal6524 19 GPIO_ACTIVE_HIGH>;
+// pinctrl-0 = <&pinctrl_uart5>;
+// status = "okay";
+
+// bluetooth {
+// compatible = "nxp,88w8987-bt";
+// };
+// };
+
+// Disabled USB for now.
+// &usbotg1 {
+// dr_mode = "otg";
+// hnp-disable;
+// srp-disable;
+// adp-disable;
+// usb-role-switch;
+// disable-over-current;
+// samsung,picophy-pre-emp-curr-control = <3>;
+// samsung,picophy-dc-vol-level-adjust = <7>;
+// status = "okay";
+
+// port {
+// usb1_drd_sw: endpoint {
+// remote-endpoint = <&typec1_dr_sw>;
+// };
+// };
+// };
+
+// &usbotg2 {
+// dr_mode = "host";
+// disable-over-current;
+// samsung,picophy-pre-emp-curr-control = <3>;
+// samsung,picophy-dc-vol-level-adjust = <7>;
+// status = "okay";
+
+// };
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+// Disabled, we don't have a usdhc2 on the board.
+// &usdhc2 {
+// pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+// pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+// pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+// pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+// pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+// cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+// fsl,cd-gpio-wakeup-disable;
+// vmmc-supply = <®_usdhc2_vmmc>;
+// bus-width = <4>;
+// status = "okay";
+// no-sdio;
+// no-mmc;
+// };
+
+// Disabled, we don't have a usdhc3 on the board.
+// &usdhc3 {
+// pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+// pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
+// pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
+// pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
+// pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
+// mmc-pwrseq = <&usdhc3_pwrseq>;
+// vmmc-supply = <®_usdhc3_vmmc>;
+// pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>;
+// bus-width = <4>;
+// keep-power-in-suspend;
+// non-removable;
+// wakeup-source;
+// status = "okay";
+
+// wifi-wake-host {
+// compatible = "nxp,wifi-wake-host";
+// interrupt-parent = <&gpio3>;
+// interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+// interrupt-names = "host-wake";
+// };
+// };
+
+&ocotp {
+ imx93_uid: soc-uid@c0 {
+ reg = <0xc0 0x10>;
+ };
+
+ imx93_soc: imx93-soc {
+ compatible = "fsl,imx93";
+ nvmem-cells = <&imx93_uid>;
+ nvmem-cell-names = "soc_unique_id";
+ };
+};
+
+// Keep off for now.
+// &wdog3 {
+// fsl,ext-reset-output;
+// status = "okay";
+// };
+
+// Keep disabled for now.
+// &tpm3 {
+// pinctrl-names = "default";
+// pinctrl-0 = <&pinctrl_led1>;
+// status = "okay";
+// };
+
+// &tpm4 {
+// pinctrl-names = "default";
+// pinctrl-0 = <&pinctrl_led2>;
+// status = "okay";
+// };
+
+&iomuxc {
+ // Disabled for now
+ // pinctrl_eqos: eqosgrp {
+ // fsl,pins = <
+ // MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ // MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ // MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ // MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ // MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ // MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ // MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
+ // MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ // MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ // MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ // MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ // MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ // MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
+ // MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ // >;
+ // };
+
+ // pinctrl_eqos_sleep: eqosgrpsleep {
+ // fsl,pins = <
+ // MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
+ // MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
+ // MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
+ // MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
+ // MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
+ // MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ // MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
+ // MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
+ // MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
+ // MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
+ // MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
+ // MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
+ // MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
+ // MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
+ // >;
+ // };
+
+ // Disabled for now.
+ // pinctrl_fec: fecgrp {
+ // fsl,pins = <
+ // MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ // MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ // MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ // MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ // MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ // MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ // MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
+ // MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ // MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ // MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ // MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ // MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ // MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
+ // MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ // >;
+ // };
+
+ // pinctrl_fec_sleep: fecsleepgrp {
+ // fsl,pins = <
+ // MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
+ // MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
+ // MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
+ // MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
+ // MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
+ // MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
+ // MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
+ // MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
+ // MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
+ // MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
+ // MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
+ // MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
+ // MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
+ // MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
+ // >;
+ // };
+
+
+ // Disabled, we don't have canbus on the dsmr6 board.
+ // pinctrl_flexcan2: flexcan2grp {
+ // fsl,pins = <
+ // MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ // MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ // >;
+ // };
+ // pinctrl_flexcan2_sleep: flexcan2sleepgrp {
+ // fsl,pins = <
+ // MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e
+ // MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e
+ // >;
+ // };
+
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ // disabled because i2c3 is disabled
+ // pinctrl_lpi2c3: lpi2c3grp {
+ // fsl,pins = <
+ // MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ // MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ // >;
+ // };
+
+ // Disabled because we don't have a pcal6524 on the DSMR6 board.
+ // pinctrl_pcal6524: pcal6524grp {
+ // fsl,pins = <
+ // MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ // >;
+ // };
+
+ // Renamed to uart2
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
+ MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
+ >;
+ };
+
+ // Disabled, we don't have a uart5 on the board.
+ // pinctrl_uart5: uart5grp {
+ // fsl,pins = <
+ // MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ // MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
+ // MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ // MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ // >;
+ // };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ // USDHC disabled, we are not using it on DSMR6
+ // pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ // fsl,pins = <
+ // MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ // >;
+ // };
+
+ // pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ // fsl,pins = <
+ // MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ // >;
+ // };
+
+ // pinctrl_usdhc2_gpio_sleep: usdhc2gpiogrpsleep {
+ // fsl,pins = <
+ // MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
+ // >;
+ // };
+
+ // Disabled, we don't have a usdhc2 on the board.
+ // /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ // pinctrl_usdhc2: usdhc2grp {
+ // fsl,pins = <
+ // MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ // MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
+ // MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
+ // MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
+ // MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
+ // MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
+ // MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ // >;
+ // };
+
+ // /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ // pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ // fsl,pins = <
+ // MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ // MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
+ // MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
+ // MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
+ // MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
+ // MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
+ // MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ // >;
+ // };
+
+ // /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ // pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ // fsl,pins = <
+ // MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ // MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
+ // MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
+ // MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
+ // MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
+ // MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
+ // MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ // >;
+ // };
+
+ // pinctrl_usdhc2_sleep: usdhc2grpsleep {
+ // fsl,pins = <
+ // MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
+ // MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
+ // MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
+ // MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
+ // MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
+ // MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
+ // MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
+ // >;
+ // };
+
+ // DIsabled, we don't have a usdhc3 on the board.
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ // pinctrl_usdhc3: usdhc3grp {
+ // fsl,pins = <
+ // MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582
+ // MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382
+ // MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382
+ // MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382
+ // MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382
+ // MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382
+ // >;
+ // };
+
+ // /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ // pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ // fsl,pins = <
+ // MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e
+ // MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e
+ // MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
+ // MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
+ // MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
+ // MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
+ // >;
+ // };
+
+ // /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ // pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ // fsl,pins = <
+ // MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe
+ // MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe
+ // MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe
+ // MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe
+ // MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe
+ // MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe
+ // >;
+ // };
+
+ // pinctrl_usdhc3_sleep: usdhc3grpsleep {
+ // fsl,pins = <
+ // MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e
+ // MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e
+ // MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e
+ // MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e
+ // MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e
+ // MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e
+ // >;
+ // };
+
+ // pinctrl_usdhc3_wlan: usdhc3wlangrp {
+ // fsl,pins = <
+ // MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ // >;
+ // };
+
+ // Disabled, we don't have a mqs1 on the board.
+ // pinctrl_mqs1: mqs1grp {
+ // fsl,pins = <
+ // MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e
+ // MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e
+ // >;
+ // };
+
+
+ // Disabled for now, we have SPI3 (and4), But test later
+ // pinctrl_lpspi3: lpspi3grp {
+ // fsl,pins = <
+ // MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe
+ // MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe
+ // MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe
+ // MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe
+ // >;
+ // };
+
+
+ // Disabled for now.
+ // pinctrl_led1: ledsgrp1 {
+ // fsl,pins = <
+ // MX93_PAD_GPIO_IO04__TPM3_CH0 0x02
+ // MX93_PAD_GPIO_IO12__TPM3_CH2 0x02
+ // >;
+ // };
+ // pinctrl_led2: ledsgrp2 {
+ // fsl,pins = <
+ // MX93_PAD_GPIO_IO13__TPM4_CH2 0x02
+ // >;
+ // };
+};
+
+// Enable later
+// &lpspi3 {
+// fsl,spi-num-chipselects = <1>;
+// pinctrl-names = "default", "sleep";
+// pinctrl-0 = <&pinctrl_lpspi3>;
+// pinctrl-1 = <&pinctrl_lpspi3>;
+// cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+// pinctrl-assert-gpios = <&pcal6408 0 GPIO_ACTIVE_HIGH>;
+// status = "okay";
+
+// spidev0: spi@0 {
+// reg = <0>;
+// compatible = "lwn,bk4";
+// spi-max-frequency = <1000000>;
+// };
+// };
+
+
+&ele_if0 {
+ memory-region = <&ele_reserved>;
+};
--
2.46.0.windows.1
