File 0005-enable-spi3-spi7.patch of Package imx93-devicetree
From 00bb5cd6d5f032e37dc7ba2c9dfafa4934d82220 Mon Sep 17 00:00:00 2001
From: Michael van der Raad <vanderraad@inventeers>
Date: Fri, 12 Sep 2025 13:10:03 +0000
Subject: [PATCH] Enable spi7
---
.../boot/dts/freescale/imx93-11x11-frdm.dts | 36 ++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
index 44790c397387..8dd93a303b69 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
@@ -916,6 +916,24 @@ MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe
MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe
>;
};
+
+ pinctrl_lpspi7: lpspi7grp { /*!< Function assigned for the core: Cortex-A55[ca55] */
+ fsl,pins = <
+ MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0000111E
+ MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0000031E
+ MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0000011E
+ MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0000011E
+ MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x0000011E
+ /*
+ MX93_PAD_GPIO_IO12__LPUART8_TX 0x0000011E
+ MX93_PAD_GPIO_IO13__LPUART8_RX 0x0000011E
+ */
+ MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0000031E
+ MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x0000111E
+ MX93_PAD_SAI1_TXC__GPIO1_IO12 0x0000011E
+ >;
+ };
+
pinctrl_led1: ledsgrp1 {
fsl,pins = <
MX93_PAD_GPIO_IO04__TPM3_CH0 0x02
@@ -956,7 +974,22 @@ &lpspi3 {
pinctrl-0 = <&pinctrl_lpspi3>;
pinctrl-1 = <&pinctrl_lpspi3>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
- pinctrl-assert-gpios = <&pcal6408 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ reg = <0>;
+ compatible = "lwn,bk4";
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&lpspi7 {
+ fsl,spi-num-chipselects = <2>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpspi7>;
+ pinctrl-1 = <&pinctrl_lpspi7>;
+ cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW
+ &gpio2 25 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
@@ -969,3 +1002,4 @@ spidev0: spi@0 {
&ele_if0 {
memory-region = <&ele_reserved>;
};
+
--
2.50.1
