File configure-eqos.patch of Package uboot-imx

From ffe31d5869fab3452ca31bafe3349469625aacf6 Mon Sep 17 00:00:00 2001
From: dewit <dewit@inventeers.nl>
Date: Fri, 29 Aug 2025 09:53:56 +0200
Subject: [PATCH] Enable and reconfigure eqos as per AN14149

---
 arch/arm/dts/imx93-11x11-frdm.dts     | 51 +++++++++++++++------------
 arch/arm/dts/imx93.dtsi               |  3 +-
 arch/arm/mach-imx/imx9/native/clock.c |  2 +-
 3 files changed, 31 insertions(+), 25 deletions(-)

diff --git a/arch/arm/dts/imx93-11x11-frdm.dts b/arch/arm/dts/imx93-11x11-frdm.dts
index 2e6fde837f9..a553156810b 100644
--- a/arch/arm/dts/imx93-11x11-frdm.dts
+++ b/arch/arm/dts/imx93-11x11-frdm.dts
@@ -95,32 +95,34 @@
 	status = "okay";
 };
 
-// &eqos {
-// 	pinctrl-names = "default";
-// 	pinctrl-0 = <&pinctrl_eqos>;
-// 	phy-mode = "rgmii-id";
-// 	phy-handle = <&ethphy1>;
-// 	status = "okay";
-//  local-mac-address = [ 55 44 33 22 11 00 ];
-// 
-// 	mdio {
-// 		compatible = "snps,dwmac-mdio";
-// 		#address-cells = <1>;
-// 		#size-cells = <0>;
-// 		clock-frequency = <5000000>;
-// 
-// 		ethphy1: ethernet-phy@1 {
-// 			reg = <1>;
-// 			eee-broken-1000t;
-// 		};
-// 	};
-// };
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+    local-mac-address = [ 55 44 33 22 11 00 ];
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
+
+		ethphy1: ethernet-phy@1 {
+			reg = <1>;
+			eee-broken-1000t;
+            reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
+		};
+	};
+};
 
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "rmii";
-	phy-handle = <&ethphy1>;
+	phy-handle = <&ethphy2>;
 	fsl,magic-packet;
 	status = "okay";
     local-mac-address = [ 00 11 22 33 44 55 ];
@@ -128,12 +130,14 @@
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clock-frequency = <2500000>;
+		clock-frequency = <5000000>;
 
-		ethphy1: ethernet-phy@1 {
+		ethphy2: ethernet-phy@1 {
             compatible = "ti,dp83822";
 			reg = <1>;
 			eee-broken-1000t;
+            reset-assert-us = <10000>;
+			reset-deassert-us = <80000>;
 		};
 	};
 };
@@ -422,6 +426,7 @@
 			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
 			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
 			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
+            MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK     0x4000057e
 		>;
 	};
 
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
index 4c1e743a805..268fe37aca6 100644
--- a/arch/arm/dts/imx93.dtsi
+++ b/arch/arm/dts/imx93.dtsi
@@ -1144,8 +1144,9 @@
 						  <&clk IMX93_CLK_ENET>;
 				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
 							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
-				assigned-clock-rates = <100000000>, <250000000>;
+				assigned-clock-rates = <100000000>, <100000000>;
 				intf_mode = <&wakeupmix_gpr 0x28>;
+                enet_clk_sel = <&wakeupmix_gpr 0x2C>;
 				snps,clk-csr = <0>;
 				status = "disabled";
 			};
diff --git a/arch/arm/mach-imx/imx9/native/clock.c b/arch/arm/mach-imx/imx9/native/clock.c
index 116bfdad81b..f9f18781365 100644
--- a/arch/arm/mach-imx/imx9/native/clock.c
+++ b/arch/arm/mach-imx/imx9/native/clock.c
@@ -959,8 +959,8 @@ int set_clk_enet(enum enet_freq type)
 		return -EINVAL;
 	}
 
+	ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div);
 	ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
-	ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div * 2);
 
 #ifdef CONFIG_FEC_MXC_25M_REF_CLK
 	ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20);
-- 
2.51.0.windows.1