File debian.control of Package verilator

Source: verilator
Section: electronics
Priority: extra
Maintainer: Staf Verhaegen <staf@fibraservi.eu>
Build-Depends: debhelper (>= 9), coreutils, findutils, flex, bison, perl

Package: verilator
Architecture: any
Depends: zlib1g-dev, ${shlibs:Depends}
Description: A fast simulator for synthesizable Verilog
 Verilator is the fastest free Verilog HDL simulator. It compiles
 synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis
 assertions into C++ or SystemC code. It is designed for large projects
 where fast simulation performance is of primary concern, and is
 especially well suited to create executable models of CPUs for
 embedded software design teams.