File qucs-digisim-verilog.patch of Package qucs

diff -up qucs-0.0.20/qucs/components/digi_sim.cpp.aaa qucs-0.0.20/qucs/components/digi_sim.cpp
--- qucs-0.0.20/qucs/components/digi_sim.cpp.aaa	2024-07-06 17:57:31.157452863 +0200
+++ qucs-0.0.20/qucs/components/digi_sim.cpp	2024-07-06 17:58:26.389728678 +0200
@@ -44,7 +44,7 @@ Digi_Sim::Digi_Sim()
 	QObject::tr("type of simulation")+" [TruthTable, TimeList]"));
   Props.append(new Property("time", "10 ns", false,
 	QObject::tr("duration of TimeList simulation")));
-  Props.append(new Property("Model", "VHDL", false,
+  Props.append(new Property("Model", "Verilog", false,
 	QObject::tr("netlist format")+" [VHDL, Verilog]"));
 }