File 0074-vmxnet3-Support-reading-IMR-registe.patch of Package qemu.5295

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File 0074-vmxnet3-Support-reading-IMR-registe.patch of Package qemu.5295

From d64784d3e73a6ef7ae15b034a838f2085bb04b8d Mon Sep 17 00:00:00 2001
From: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com>
Date: Mon, 21 Sep 2015 17:09:02 +0300
Subject: [PATCH] vmxnet3: Support reading IMR registers on bar0

Instead of asserting, return the actual IMR register value.
This is aligned with what's returned on ESXi.

Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com>
Tested-by: Dana Rubin <dana.rubin@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
(cherry picked from commit c6048f849c7e3f009786df76206e895a69de032c)
[CYL: BSC#960708 CVE-2015-8745]
Signed-off-by: Chunyan Liu <cyliu@suse.com>
---
 hw/net/vmxnet3.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index dfb328d..4631c0b 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -1108,9 +1108,13 @@ vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
 static uint64_t
 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
 {
+    VMXNET3State *s = opaque;
+
     if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
                         VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
-        g_assert_not_reached();
+        int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
+                                         VMXNET3_REG_ALIGN);
+        return s->interrupt_states[l].is_masked;
     }
 
     VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);

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File 0074-vmxnet3-Support-reading-IMR-registe.patch of Package qemu.5295

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