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cross-i386-gcc48-icecream-backend.7695
gcc48-bnc1050947.patch
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File gcc48-bnc1050947.patch of Package cross-i386-gcc48-icecream-backend.7695
CVE-2017-11671 2017-03-25 Uros Bizjak <ubizjak@gmail.com> PR target/80180 * config/i386/i386.c (ix86_expand_builtin) <IX86_BUILTIN_RDSEED{16,32,64}_STEP>: Do not expand arg0 between flags reg setting and flags reg using instructions. <IX86_BUILTIN_RDRAND{16,32,64}_STEP>: Ditto. Use non-flags reg clobbering instructions to zero extend op2. Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c (revision 246478) +++ gcc/config/i386/i386.c (revision 246479) @@ -39533,9 +39533,6 @@ ix86_expand_builtin (tree exp, rtx targe mode0 = DImode; rdrand_step: - op0 = gen_reg_rtx (mode0); - emit_insn (GEN_FCN (icode) (op0)); - arg0 = CALL_EXPR_ARG (exp, 0); op1 = expand_normal (arg0); if (!address_operand (op1, VOIDmode)) @@ -39543,6 +39540,10 @@ rdrand_step: op1 = convert_memory_address (Pmode, op1); op1 = copy_addr_to_reg (op1); } + + op0 = gen_reg_rtx (mode0); + emit_insn (GEN_FCN (icode) (op0)); + emit_move_insn (gen_rtx_MEM (mode0, op1), op0); op1 = gen_reg_rtx (SImode); @@ -39551,8 +39552,20 @@ rdrand_step: /* Emit SImode conditional move. */ if (mode0 == HImode) { - op2 = gen_reg_rtx (SImode); - emit_insn (gen_zero_extendhisi2 (op2, op0)); + if (TARGET_ZERO_EXTEND_WITH_AND + && optimize_function_for_speed_p (cfun)) + { + op2 = force_reg (SImode, const0_rtx); + + emit_insn (gen_movstricthi + (gen_lowpart (HImode, op2), op0)); + } + else + { + op2 = gen_reg_rtx (SImode); + + emit_insn (gen_zero_extendhisi2 (op2, op0)); + } } else if (mode0 == SImode) op2 = op0; @@ -39584,9 +39597,6 @@ rdrand_step: mode0 = DImode; rdseed_step: - op0 = gen_reg_rtx (mode0); - emit_insn (GEN_FCN (icode) (op0)); - arg0 = CALL_EXPR_ARG (exp, 0); op1 = expand_normal (arg0); if (!address_operand (op1, VOIDmode)) @@ -39594,6 +39604,10 @@ rdseed_step: op1 = convert_memory_address (Pmode, op1); op1 = copy_addr_to_reg (op1); } + + op0 = gen_reg_rtx (mode0); + emit_insn (GEN_FCN (icode) (op0)); + emit_move_insn (gen_rtx_MEM (mode0, op1), op0); op2 = gen_reg_rtx (QImode);
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